KR20000060386A - Substrate bias generator circuit of memory device - Google Patents

Abstract

PURPOSE: A substrate bias circuit of a memory device is provided which can reduce the power consumption and also can reach a VBB level rapidly. CONSTITUTION: A substrate bias circuit of a memory device comprises: an oscillation part(10) to oscillate; a first pumping part(42) and a second pumping part(44) with different electrostatic capacity pumping charges to generate a substrate bias voltage(VBB); a first driver(22) and a second driver(24) each pumping charges through the first pumping part and the second pumping part by receiving an oscillation signal generated in the oscillation part; and a substrate bias voltage level detection part(50) selecting the driving of the first driver and the second driver by detecting the substrate bias voltage. The circuit uses a pump capacitor(34) with a large capacitance and a pump capacitance with a small capacitance together until the substrate bias voltage reaches a desired value stably, and then if the substrate bias voltage level detection part detects that the substrate bias voltage reaches a stable voltage level, the circuit uses only the pump capacitance with a small capacitance. Therefore, the circuit reduces the power consumption and can reach the stable substrate bias voltage rapidly.

Description

Substrate bias generator circuit of memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate bias circuit of a memory device, and more particularly, a pump capacitor having a small capacity and a large capacity, and a large capacity pump capacitor and a small capacity pump until the substrate bias voltage reaches a desired value stably. The present invention relates to a substrate bias circuit of a memory device that reduces power consumption by using only a small capacity pump capacitor when all capacitors are reached stably.

A memory device is a general term used to temporarily or permanently store data or instructions used in computers, communication systems, image processing systems, and the like, and includes semiconductors, tapes, disks, and optical methods. have.

Such semiconductor memory devices are also classified into DRAM, SRAM, Flash memory, and ROM according to the electrical characteristics of the data storage method. The characteristic of the DRAM (Dynamic Random Access Memory), which occupies most of the entire semiconductor memory market, is that random access is possible, and data can be read and written electrically. In particular, there is no limit on the number of writes. It is a volatile memory that loses existing data, needs refresh periodically, and requires a precharge time every operation cycle to satisfy the restore operation.

In such a DRAM, a voltage of -2V to -3V is applied to the P-WELL surrounding the NMOS from a power supply of VCC = 5V as the VBB voltage. This VBB voltage is also called a substrate bias voltage because it is also applied to a P-type silicon substrate generally used as a DRAM substrate.

By applying the substrate bias voltage, the PN junction in the DRAM chip is prevented from being partially forward biased, thereby preventing data loss or latch-up of the memory cell, and reducing the change in the threshold voltage of the MOS to stabilize the circuit operation. In addition, the threshold voltage of the parasitic MOS transistor can be increased. In addition, applying a reverse bias reduces the PN junction capacitance formed between the N + region of the NMOS and the P-WELL, thereby increasing the speed of the circuit.

1 is a circuit diagram illustrating a substrate bias circuit of a general memory device.

As shown here, the oscillation unit 10 for oscillation includes a ring oscillator including an odd number of inverters, a pumping unit 40 for pumping charges to generate a substrate bias voltage VBB, and an oscillation signal generated in the ring oscillator. It receives the input is made of a driver 20 for pumping the charge through the pumping unit (40).

In addition, the pumping unit 40 may have a source and a drain of two first NMOS transistors Q1 and a second NMOS transistor Q2 diode-connected to the pump capacitor 30 connected to each other by a point A, and the first NMOS transistor Q1 may The drain is connected to the VBB terminal and the source of the second NMOS transistor Q2 is respectively connected to the ground.

Referring to the operation of the substrate bias circuit of the memory device made as described above is as follows.

First, both the voltage at point A and VBB become 0V. At this time, if the output value of the driver 20 rises from 0V to VCC, the point A is raised to high potential by the pump capacitor 30. However, the first NMOS transistor Q1 is turned on, and soon A point is dropped to the VT level. At this time, the second NMOS transistor Q2 is turned off. When the voltage at point A drops below the VT level, the first NMOS transistor Q1 is also turned off.

Next, when the driver output falls from VCC to 0V, the point A is dropped to the VT-VCC level by the pump capacitor 30. Accordingly, the second NMOS transistor Q2 is turned on to supply electrons from the point A to the VBB. As a result, the potential at the point A rises from the VT-VCC level to the level of -VT. At this time, the first NMOS transistor Q1 is turned off. When the potential of the point A becomes -VT, the second NMOS transistor Q2 is turned off, and as a result, the potential of VBB becomes slightly "-".

If the above operation is repeated, the potential of VBB gradually becomes "-", and when VBB = 2VT-VCC, the supply of electrons from point A to VBB is stopped through the second NMOS transistor Q2. Therefore, the VBB value is stabilized to-(VCC-2VT).

When the capacity of the pump capacitor 30 is large in the substrate bias circuit configured as described above, it arrives to the desired VBB level early and is stable, but there is a problem that the power consumption is large and the power consumption is large, and when the capacity of the pump capacitor 30 is small There is a problem that the power consumption is small, so the power consumption is small, but it takes a long time to reach the desired VBB level and stabilize.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a small capacity and a large capacity of the pump capacitor until the substrate bias voltage stably reaches a desired value, When all the pump capacitors of the capacity are used and the stable voltage level is reached, only a small pump capacitor is used to reduce the power consumption, and the board of the memory device to be stabilized by reaching the VBB level quickly. To provide a bias circuit.

1 is a circuit diagram illustrating a general substrate bias circuit.

2 is a circuit diagram showing a substrate bias circuit according to the present invention.

-Explanation of symbols for the main parts of the drawings

10: oscillation unit 20: driver

22: first driver 24: second driver

30 pump capacitor 32 first pump capacitor

34: second pump capacitor 40: pumping unit

42: first pumping section 44: second pumping section

50: substrate bias voltage level detection unit

Q1 to Q6: first to sixth NMOS transistors

The present invention for realizing the above object is an oscillation unit for oscillation, the first pumping unit and the second pumping unit and the oscillation signal generated from the capacitance different from each other to pump the charge to generate a substrate bias voltage The first and second drivers for pumping the charge through the first pumping unit and the second pumping unit respectively, and the substrate bias voltage level detection unit for detecting the substrate bias voltage to select the driving of the first driver and the second driver Characterized in that consisting of.

The capacitance of the pump capacitor of the first pumping unit and the second pumping unit is different from each other.

Referring to the operation of the present invention made as described above are as follows.

First, in the normal state, both the first driver and the second driver are operated to supply the oscillation signal oscillated from the oscillator to the first pumping unit and the second pumping unit so that the pump is quickly reached to the set substrate bias voltage level so as to be stable at the set voltage level. When the substrate bias voltage level detection unit detects this, the second driver and the second pump unit are turned off so that only the first driver and the first pump unit are activated, thereby reducing power consumption required to generate and maintain the substrate bias voltage. It operates to reach the bias voltage quickly.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2 is a circuit diagram showing a substrate bias circuit of the memory device according to the present invention.

As shown here, the oscillation unit 10 for oscillating, the first pumping unit 42 and the second pumping unit 44 having different capacitances for generating charge to generate the substrate bias voltage VBB, and The first driver 22 and the second driver 24 which receive the oscillation signal generated by the oscillator 10 and pump the electric charges through the first pump 42 and the second pump 44, respectively; The substrate bias voltage level detector 50 detects the substrate bias voltage VBB level and selects driving of the first driver 22 and the second driver 24.

When the substrate bias voltage VBB reaches a predetermined level, the oscillation signal input to the second driver 24 to stop the operation of the second driver 24 includes the oscillation signal output from the oscillator 10 and the substrate. It is input through the NOR gate NOR which has an output value of the bias voltage level detection part 50 as an input.

The first pumping part 42 has a source and a drain of two third NMOS transistors Q3 and a fourth NMOS transistor Q4 diode-connected to the first pump capacitor 32 having a small capacitance and are connected to each other by a point B. A drain of the 3NMOS transistor Q3 is connected to the VBB terminal, and a source of the fourth NMOS transistor Q4 is connected to the ground, respectively. In addition, the second pumping unit 44 is connected to the source and the drain of the two fifth NMOS transistor Q5 and the sixth NMOS transistor Q6 diode-connected to the second pump capacitor 34 having a large capacitance by C point. The drain of the fifth NMOS transistor Q5 is connected to the VBB terminal and the source of the sixth NMOS transistor Q6 is connected to ground, respectively.

Referring to the operation of the present invention made as described above are as follows.

First, since the VBB voltage is not stabilized by the substrate bias voltage level detecting unit 50, both the first driver 22 and the second driver 24 are activated, and thus the first pumping unit 42 and the second driver 24 are activated. Both of the pumping sections 44 are activated so that the voltages at the B and C points and the VBB are both 0V. At this time, when the output value of the first driver 22 and the second driver 24 rises from 0V to VCC, points B and C are raised to high potential by the first pump capacitor 32 and the second pump capacitor 34. . However, the third NMOS transistor Q3 and the fifth NMOS transistor Q5 are turned on, so that the B and C points are dropped to the VT level. At this time, the fourth NMOS transistor Q4 and the sixth NMOS transistor Q6 are turned off. When the voltages at points B and C fall below the VT level, the third NMOS transistor Q3 and the fifth NMOS transistor Q5 are also turned off.

Next, when the output of the first driver 22 and the second driver 24 drops from VCC to 0V, the points B and C are set by the first pump capacitor 32 and the second pump capacitor 34 by VT −. Fall to the VCC level. Therefore, the fourth NMOS transistor Q4 and the sixth NMOS transistor Q6 are turned on, and electrons are supplied to the VBB from points B and C. As a result, the potentials of the points B and C rise from the VT-VCC level to the level of -VT. At this time, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are turned off. When the potentials of the points B and C become -VT, the fourth NMOS transistor Q4 and the sixth NMOS transistor Q6 are turned off, and as a result, the potential of VBB becomes slightly "-".

If the above operation is repeated, the potential of VBB gradually becomes "-" value, and when VBB = 2VT-VCC value, electron supply from point B and point C to VBB through the 4th NMOS transistor Q4 and the 6th NMOS transistor Q6. Will stop. Therefore, the VBB value is stabilized to-(VCC-2VT).

When the substrate bias voltage VBB is stabilized as described above, the substrate bias voltage level detector 50 detects this and stops the operation of the second driver 24 so that only the first driver 22 is operated, so that the first capacitance has a small capacitance. The pump capacitor 32 maintains a stable substrate bias voltage VBB.

As described above, the present invention provides both a large capacity pump capacitor and a small capacity pump capacitor until the substrate bias voltage reaches a desired value by providing a small capacity and a large capacity of the pump capacitor of the substrate bias circuit of the memory device. When the battery reaches a stable level of use, only a small capacity pump capacitor can be used to reduce power consumption and maintain a stable voltage level in a short time.

Claims (2)

An oscillation unit for oscillating, A first pumping unit and a second pumping unit having different capacitances for pumping charges to generate a substrate bias voltage; A first driver and a second driver receiving the oscillation signal generated by the oscillator and pumping electric charges through the first pumping unit and the second pumping unit, respectively; A substrate bias voltage level detection unit which detects the substrate bias voltage and selects driving of the first driver and the second driver Substrate bias circuit of a memory device, characterized in that consisting of. The substrate bias circuit of claim 1, wherein the pump capacitors of the first pumping unit and the second pumping unit have different capacitances.