KR20000057990A - Capacitive element, semiconductor device having the capacitive element and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A capacitor and a semiconductor device are provided to have a high operational reliability by enabling a fabrication process of the capacitor to be proceeded under 700°C. CONSTITUTION: A lower electrode(1) has HSG(hemispherical grain) formed on the surface thereof. A dielectric film(2) is composed of silicon nitride and covers the surface of the lower electrode(1). An upper electrode(3) covers the dielectric film(2). In the prior art, an impurity-doped polysilicon was adopted for an upper electrode. In that case, the impurity-doped polysilicon did not function as an upper electrode when heat treated under 700°C. However, an upper electrode(3) of the invention is composed of metal or electrically conducting compound. So the upper electrode(3), even though formed under 700°C, can sufficiently function as an electrode.

Description

Capacitive element, semiconductor device using same and manufacturing method thereof {Capacitive element, semiconductor device having the capacitive element and method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor, and more particularly, to a capacitance having a lower electrode including silicon forming HSG (hemisperical grains). The present invention also relates to a semiconductor device having a capacitance and a method of manufacturing the capacitance and the semiconductor device.

In recent years, integrated circuits such as DRAM (Dynamic Random Access Memory) included in semiconductor devices have been miniaturized, and a capacitor having a high capacity and designed to occupy a small area has been demanded. In response to such a requirement, one method for forming HSG on the surface of a lower electrode included in one capacitor is proposed.

1 is a cross-sectional view illustrating an electrode portion of a conventional capacitor. In the electrode portion of the capacitor, the capacitor film 32 formed of a silicon nitride film is formed on the surface of the lower electrode 31 made of polysilicon. The upper electrode 33 made of polysilicon is formed on the surface of the capacitor film 32.

The HSG 43 is formed on the surface of the lower electrode 31. The individual HSGs 43 are formed convex, for example, in the form of mushrooms having a diameter of 30 to 70 nm or almost hemispheres, or a combination of the two. If the HSG 43 is formed on the surface of the lower electrode 31, the capacitor element can have a large surface area while occupying a small area. When the capacity increase rate is the same as the surface area increase rate of the lower electrode 31, if the surface area of the lower electrode 31 is doubled as compared with the capacitance element that does not include the HSG 43 on the surface of the lower electrode 31, The capacitor having the HSG 43 formed on the lower electrode 31 can obtain a capacitance value almost twice that of the original value.

The general process of forming the HSG 43 on the lower electrode 31 is as follows. First, a lower electrode layer, which is a doped amorphous silicon film such as a guided amorphous silicon film, is formed and patterned to form the lower electrode 31. Next, the HSG 43 is formed on the surface of the lower electrode 31 in accordance with the ongoing process. By performing the heat treatment during the formation of the HSG, the doped amorphous silicon forming the lower electrode 31 is converted into polysilicon. The surface of the lower electrode 31 on which the HSG 43 is formed is covered with the capacitor film 32. A doped polysilicon film, such as a guided polysilicon, is formed on the capacitor film 32 to form the upper electrode 33, thereby completing the capacitor.

In this manufacturing process, after the doped polysilicon film used to form the upper electrode 33 is formed on the capacitor film 32, heat treatment is performed at 800 ° C. or higher to sufficiently obtain electrical conductivity. As a result, impurities such as phosphorus are activated.

The capacitor is formed after the formation of a transistor such as a MOSFET. If the capacitor is heat-treated at an extremely high temperature of 800 ° C. or higher during the formation of the capacitor, the impurities contained in the diffusion layer of the transistor are further diffused, resulting in a shorter gap (channel length) between the source diffusion layer and the drain diffusion layer. do. In the above circumstances, if the conventional capacitor is downsized, a problem arises in that an efficient channel length is not sufficiently secured and a punch-throw phenomenon occurs.

If an integrated circuit including a DRAM and a transistor used in a logic circuit requiring high speed operation is heat-treated at a temperature of 800 ° C. or higher, a punch-throw may occur in the transistor used in the logic circuit, or The resistance of the silicon compound formed on the source diffusion layer, the drain diffusion layer, and the gate electrode included in the transistor used in the logic circuit may increase.

Considering the above method, if the capacitor element is manufactured at a temperature of 700 DEG C or lower during the entire manufacturing process, the impurity depletion layer 34 is formed of the capacitor film in the upper electrode 33 made of the doped polysilicon described in FIG. In the area adjacent to it. In the impurity depletion layer 34, impurities such as phosphorous do not diffuse as desired. In this structure, the thickness of the insulating film is substantially increased, and the capacitance value is not sufficiently obtained. In particular, when the upper electrode 33 is set to a positive potential compared to the lower electrode 31, electrons move from the lower side of the upper electrode 33 adjacent to the capacitor film 32 to the upper side of the upper electrode 33. For this reason, the thickness of the impurity depletion layer 34 increases and the capacitance value decreases.

As described above, if the capacitance value decreases, the electric charge is not completely accumulated in the capacitance portion. Therefore, a predetermined amount of electrical charging is not made in a given time. To eliminate these incomplete characteristics, it is necessary to increase the number of refresh cycles or increase the area of the capacity. However, an increase in the number of refresh cycles lowers the read speed, and an increase in the capacity area leads to an increase in the chip area.

Japanese Patent Application Laid-Open No. 8-139288 discloses an improvement in the leakage current characteristics due to an increase in the lower electrode on the rough surface of the lower electrode, and a capacitance element, tantalum oxide, which forms the lower electrode using HSG tungsten formed on the surface of silicon. A capacitive film formed and an upper electrode formed of titanium nitride and tungsten are disclosed. However, the manufacturing method disclosed in the publication has two drawbacks:

First, many manufacturing processes are required, and each of these manufacturing processes requires a dedicated manufacturing apparatus. Moreover, such dedicated manufacturing equipment is expensive on equipment.

Secondly, the thermal stability of the capacitive film formed of tantalum oxide is not sufficiently obtained. After the formation of the capacitor, when the peripheral circuit in the formation process requires heat treatment at a temperature of, for example, 700 占 폚, the capacitor film inevitably deteriorates. This increases the leakage current flowing into the capacitive film and exceeds the set tolerance. Therefore, the operation reliability of the disclosed capacitor film is lowered, and the operation reliability of the semiconductor element having such a capacitor element is also lowered.

The foregoing publications are incorporated herein.

Accordingly, it is an object of the present invention to provide a capacitor and a semiconductor device having high operational reliability. Another object of the present invention is to provide a semiconductor device comprising a capacitor device and a capacitor device made of HSG having high thermal stability and silicon forming a capacitor film. It is still another object of the present invention to provide a method of manufacturing a capacitor, a method of providing a semiconductor device having a capacitor, wherein the entire capacitor is manufactured at a temperature of 700 ° C. or lower, as opposed to a capacitor manufactured by the prior art. To provide.

1 is a cross-sectional view illustrating an electrode portion of a conventional capacitor.

2 is a cross-sectional view illustrating a structure of a semiconductor device including a capacitor according to a first embodiment of the present invention.

3 is an enlarged cross-sectional view illustrating a capacitor element of the semiconductor device illustrated in FIG. 2.

4 is an enlarged cross-sectional view illustrating an electrode part of the capacitor illustrated in FIG. 3.

5 is a cross-sectional view for describing a manufacturing process of the semiconductor device including the capacitor according to the first embodiment of the present invention.

6 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a capacitor according to a first embodiment of the present invention.

7 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a capacitor according to a first embodiment of the present invention.

8 is a cross-sectional view for describing a manufacturing process of the semiconductor device including the capacitor according to the first embodiment of the present invention.

9A and 9B are cross-sectional views each illustrating a manufacturing process of a semiconductor device including a capacitor according to a first embodiment of the present invention.

10 is an enlarged cross-sectional view illustrating an electrode part of a capacitor according to a second exemplary embodiment of the present invention.

11A and 11B are cross-sectional views each illustrating a manufacturing process of a semiconductor device including a capacitor according to a second embodiment of the present invention.

12 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a capacitor according to a second embodiment of the present invention.

13 is a view showing the characteristics of the capacitor according to the comparative example and the capacitor according to the first embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings.

1: lower electrode 2: capacitor film

3: upper electrode 3B: auxiliary upper electrode

4: HSG 5: device isolation film

6: silicon substrate 7S: source diffusion layer

7D: Drain diffusion layer 8: Gate electrode

9A, 9B: Interlayer insulating film 10: First contact

11: second contact 12: bit line

15: guiding amorphous silicon 21: gate oxide film

23: titanium nitride film 24: guided polysilicon film

The capacitive element according to the first aspect of the present invention for achieving the above object is formed of silicon and having a lower electrode (1) having an HSG on its surface, formed of silicon nitride to cover the surface of the lower electrode (1) And the upper electrode 3 formed of the capacitive film 2 and the metal or the electrically conductive compound covering the capacitive film 2.

According to the present invention, since the capacitor includes an upper electrode formed of a metal or an electrically conductive compound, the entire process of forming the capacitor is performed at a temperature of 700 ° C. or less. Therefore, even when a semiconductor element such as a transistor is formed on the semiconductor substrate before forming the capacitor, the characteristics of the semiconductor element do not deteriorate.

The upper electrode 3 may be formed of high melting point metal nitride or high melting point metal oxide.

The capacitor film 2 may have a stacked structure in which a silicon nitride film and a silicon oxide film are formed.

The upper electrode 3 may be formed on the silicon oxide film.

According to a second aspect of the present invention, there is provided a method of fabricating a capacitive element, the method comprising: forming a lower electrode 1 having HSG on a surface thereof, and a capacitive film made of a silicon nitrogen compound on the lower electrode 1; 2) and forming an upper electrode 3 made of a metal or an electrically conductive metal compound on the capacitor film.

The formation of the lower electrode 1, the formation of the capacitor film 2 and the formation of the upper electrode 3 may be carried out at a temperature of 700 ° C or less.

The formation of the upper electrode 3 may include the formation of the upper electrode 3 by chemical vapor deposition (CVD).

The formation of the upper electrode 3 includes the formation of the upper electrode using a high melting point metal nitride or a high melting point metal oxide.

Formation of the capacitive film 2 includes the steps of nitriding the surface of the lower electrode 1 by a thermal nitriding technique, forming a silicon nitride film on the lower electrode 1 by a chemical vapor deposition technique, and forming a surface of the silicon nitride film. Oxidizing.

The semiconductor device including the capacitor according to the third aspect of the present invention is a capacitor formed of silicon and having a HSG on its surface, a capacitor formed of silicon nitride and covering the surface of the lower electrode 1. It consists of the membrane 2 and the upper electrode 3 which consists of a metal or an electrically conductive compound and covers the capacitance membrane 2.

The semiconductor device manufacturing method of the capacitive device manufacturing method according to the fourth aspect of the present invention comprises the step of forming a lower electrode 1 made of silicon and having an HSG on the surface thereof, and silicon nitride on the lower electrode 1 surface. And a step of forming an upper electrode 3 made of a metal or an electrically conductive compound on the capacitor film 2.

The objects and advantages of the present invention will become more apparent from the following detailed description using the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First embodiment

2 is a cross-sectional view illustrating a structure of a semiconductor device including a capacitor according to a first embodiment of the present invention. In the description, a single transistor to which a capacitive element is added is shown as the illustrated semiconductor element.

The transistor is formed in an element region partitioned by an element isolation film 5 formed on the silicon substrate 6. The transistor consists of a source diffusion layer 7S, a drain diffusion layer 7D and a gate electrode 8. The source diffusion layer 7S and the drain diffusion layer 7D are formed on the silicon substrate 6, while the gate electrode 8 is formed on the silicon substrate 6 via the gate insulating film 21.

The interlayer insulating film 9A is formed on the silicon substrate 6, and the interlayer insulating film 9B is formed on the interlayer insulating film 9A.

The capacitor is formed on the interlayer insulating film 9B. The capacitor includes a lower electrode 1 made of polysilicon, an unexemplified capacitor film 2 made of silicon nitride, and an upper electrode 3 made of metal or an electrically conductive metal compound.

The source diffusion layer 7S is connected to the lower electrode 1 via the second contact 11 penetrating through the interlayer insulating films 9A and 9B. The drain diffusion layer 7D is connected to the bit line 12 formed on the interlayer insulating film 9A via the first contact 10 penetrating through the interlayer insulating film 9A.

FIG. 3 is an enlarged cross-sectional view of the capacitor device of the semiconductor device illustrated in FIG. 2. 4 is an enlarged cross-sectional view illustrating the electrode part of the capacitor illustrated in FIG. 3.

As illustrated in FIG. 3, the HSG 4 is formed on the surface of the lower electrode 1 made of xylocone. The upper electrode 3 is formed on the surface of the lower electrode 1 on which the HSG 4 is formed.

In FIG. 4, the capacitor film 2 formed of silicon nitride is formed between the lower electrode 1 and the upper electrode 3. The upper electrode 3 is formed until it fills the space between the HSG 4. By doing so, the substantial thickness of the capacitive insulating film does not increase, and the substantial thickness of the capacitive insulating film can be determined only by the thickness of the effective capacitive film 2. The upper electrode 3 formed on the capacitive film 2 is made of a metal or an electrically conductive metal compound, and does not need impurities required to maintain electrical conductivity. As a result of the above, the electrical conductivity of the upper electrode 3 does not decrease. Moreover, an increase in capacitance is expected in the structure in which the lower electrode 1 has the HSG 4 on its lower electrode surface.

Although all of the capacitor film 2 may be a silicon nitride film, the surface connected to the upper electrode 3 is oxidized, that is, a laminated structure in which the capacitor film 2 is turned on (silicon nitride film and silicon oxide film). It is more preferable). In this embodiment of the present invention, the films including the silicon nitride film on which the silicon oxide film is formed are considered to be silicon nitride films. The thickness of the capacitive film 2 can be any length as long as it functions as a general capacitive film, and is preferably in the range of 2 to 20 nm, preferably 5 to 15 nm.

The metal film or the electrically conductive metal compound film forming the upper electrode 3 is preferably formed at a temperature of 700 ° C or less. In particular, the upper electrode 3 includes a high melting point metal (tungsten, titanium, cobalt, etc.), a high melting point metal nitride (tungsten nitride, titanium nitride, etc.), a high melting point metal oxide (ruthenium oxide, iridium oxide, etc.) or a high melting point metal silicon. It may be formed of materials such as compounds (titanium silicide, cobalt silicide, etc.). Among these, high melting point metal nitrides such as tungsten nitride and titanium nitride and high melting point metal oxides such as ruthenium oxide and iridium oxide are preferable in consideration of thermal stability of silicon nitride forming the capacitive film 2.

The upper electrode 3 is preferably formed using a chemical vapor deposition (hereinafter referred to as CVD) technique.

Hereinafter, the manufacturing method of the capacitor shown in FIG. 2 according to the first embodiment of the present invention will be described.

5 to 9B are cross-sectional views for explaining a manufacturing process of a semiconductor device having a capacitor according to a first embodiment of the present invention, respectively, each showing a single transistor portion as a semiconductor device.

As shown in Fig. 5, a conventional capacitor and a single transistor are formed. As the device isolation film 5, a LOCOS (Local Oxidation Of Silicon) film is formed on the silicon substrate 6 using the LOCOS technique. The gate electrode 8 is formed of polysilicon in a region partitioned by the device isolation film 5. Next, the source diffusion layer 7S and the drain diffusion layer 7D are formed using an ion implantation technique, thereby forming a transistor. An interlayer insulating film 9A is formed on the silicon substrate 6 on which the transistor is formed. Next, the first contact hole 10A is formed on the drain diffusion layer 7D. The first contact hole 10A is filled with guided amorphous silicon or polysilicon to form the first contact 10. Next, the bit lines 12 are formed on the surface of the interlayer insulating film 9A in an arrangement such as WSi, and the interlayer insulating film 9B is formed on the interlayer insulating film 9A and the bit line 12.

As shown in FIG. 6, the second contact hole 11A is formed through the interlayer insulating films 9A and 9B and connected to the source diffusion layer 7S. The second contact hole 11A is filled with a guided amorphous silicon containing phosphorus at a concentration of 1 × 10 ²⁰ cm ⁻³ . Next, the guiding amorphous silicon film 15 is formed to a thickness of 0.2 to 1 탆 by depositing a guiding amorphous silicon containing phosphorus at a concentration of 1x10 ²⁰ cm ^-3 on the surface of the interlayer insulating film 9B. do.

As shown in FIG. 7, the guided amorphous silicon film 15 is patterned to form the lower electrode 1 having a predetermined shape.

As shown in FIG. 8, the HSG 4 irradiates about 30 minutes of silane or desilane on the lower electrode in the furnace shown in FIG. The nuclei of silicon are formed on the lower electrode 1, and the lower electrode 1 is formed on the surface of the lower electrode 1 under the processing conditions under which the vacuum is not vacuumed at a temperature in the range of 550 ° C to 700 ° C.

Impurities may not diffuse sufficiently in the upper electrode, whereby the HSG 4 formed on the lower electrode may not contain impurities. After formation of the HSG 4, phosphorus is injected into the HSG 4 in an amount of, for example, 1 × 10 ¹⁵ cm ⁻² and with an energy acceleration of 20 KeV, or phosphorus, for example, of POCl ₃ , PH _3, etc. Heat treated in gas and doped. By doing so, phosphorus is efficiently diffused in the HSG 4 formed on the lower electrode 1. This can solve the problem of the reduction in capacitance caused by the impurities unevenly diffused in the lower electrode 1.

Following the formation of the HSG 4, the surface of the lower electrode 1 is nitrided in ammonia gas to a thickness of 1 to 1.5 nm in ammonia gas, for example, at a temperature of 700 ° C. Further, a silicon nitride film is formed on the nitrided surface of the lower electrode 1 to a thickness of 5 to 8 nm at a temperature of 700 ° C. or less using CVD technique. Thereafter, the surface of the silicon nitride film is thermally oxidized at a temperature of 700 ° C., for example, to form a silicon oxide film having a thickness of, for example, 0.5 to 1 nm so that the warm film as the capacitor film 2 is the same as that shown in Fig. 9A. Formed together.

As shown in FIG. 9B, the titanium nitride film 23 is formed on the capacitor film 2 by using a CVD technique, for example, at a temperature of 700 ° C., for example, in a thickness of 100 nm to 300 nm, where natural As gas, TiCl ₄ and ammonia are used.

Next, the titanium nitride film 23 is patterned in a set manner to form the upper electrode 3 and the wirings, thereby completely forming the capacitor shown in FIG.

Although not shown, a preferred interlayer insulating film, wiring, and the like are formed, and further, peripheral circuits are formed as necessary to complete the semiconductor device.

Second embodiment

10 is an enlarged cross-sectional view illustrating an electrode part of a capacitor according to a second exemplary embodiment of the present invention. In the second embodiment of the present invention, the structure and manufacturing method of the semiconductor element are the same except for the electrode portion and those described in the first embodiment. Therefore, only the electrode portion is described in this embodiment.

The thickness of the upper electrode 3 shown in FIG. 4 and described in the first embodiment is in the range of 100 nm to 300 nm, which is the same as that of the conventional upper electrode. It is understood that the upper electrode 3 fills the space between the HSGs 4 and, unlike the first embodiment, does not require a flat surface thereon. As shown in FIG. 10, the upper electrode 3 performs its function as long as the upper electrode covers the capacitor film 2. Therefore, the metal film or the electrically conductive metal compound film as the upper electrode 3 has, for example, a thickness of 10 nm or much larger. When the thickness of the upper electrode 3 is very thin, the auxiliary upper electrode 3B made of doped polysilicon or the like is preferably formed on the surface of the upper electrode 3, so that the upper electrode 3 can be easily connected and wired. Is connected. For example, the upper electrode 3 is formed with a thickness of 50 nm, and the auxiliary upper electrode 3B is formed thereon with a thickness of 100 nm to 300 nm.

The manufacturing process of the capacitor according to the second embodiment is substantially the same as described in the first embodiment up to the steps shown in Fig. 9A. After the step shown in Fig. 9A, the following steps proceed.

As shown in FIG. 11A, the titanium nitride film 23 is formed on the capacitor film 2 by using a CVD technique, for example, at a temperature of 700 ° C., for example, at a thickness of 10 nm, where TiCl ₄ And ammonia are used as natural gas.

As shown in Fig. 11B, the guided polysilicon film 24 is formed on the titanium nitride film 23 to a thickness of 100 to 300 nm.

As shown in FIG. 12, the titanium nitride film 23 and the guided polysilicon film 24 are patterned in a set form, respectively, and the upper electrode 3, the auxiliary upper electrode 3B, and the wiring are formed. The capacitor according to the second embodiment of the present invention is completed.

Although not shown, a preferable interlayer insulating film, wiring, and the like are formed, and further, a peripheral circuit is formed as necessary to complete the semiconductor device.

Comparative example

As described in the first and second embodiments, the upper electrode 3 is formed of a metal or an electrically conductive metal compound, whereby the capacitance value of the capacitor is increased compared to that of the conventional capacitor. The measurement results showing the increased capacitance of the capacitor are as follows.

A capacitance element for comparing the capacitance of the capacitor of the present invention and the capacitor of the present invention with the capacitance thereof is formed. The capacitor of the present invention is substantially the same as that described in the first embodiment. The capacitor used to compare the capacitance with the capacitance of the present invention has a capacitor formed on the surface of the capacitor film 2 in the state where the upper electrode formed of the guided polysilicon is shown in Fig. 9A. It is substantially the same as that described in the first embodiment except that it is heat-annealed at the temperature of.

13 is a view showing the characteristics of the capacitor according to the comparative example and the capacitor according to the first embodiment of the present invention.

It is apparent from FIG. 13 that the degree of improvement in the capacitance value of the capacitor of the present invention can be known as compared with the comparative example. In particular, the capacitance value of the capacitor is further improved when a positive voltage is applied thereto (i.e., when the upper electrode is set to the positive potential).

As described above, the upper electrode included in the capacitor is made of a metal or an electrically conductive metal compound, from which a capacitor having a high capacitance is formed at a temperature of 700 ° C. or lower. Therefore, even when a semiconductor element such as a transistor is formed on the semiconductor substrate before formation of the capacitor, the characteristics of the semiconductor element do not deteriorate.

Unlike the conventional capacitance element in which the upper electrode is formed of doped silicon, the capacitance value of the capacitor element of the present invention is clearly higher than that of the conventional capacitor element. In other words, preferred dose values are obtained according to the invention.

Various embodiments and modifications are possible within the broad spirit and scope of the invention. The above-described embodiments are intended to illustrate the present invention and do not limit the scope of the present invention. The scope of the invention is illustrated by the claims rather than the examples. Various modifications are possible within the meaning of equivalents of the claims of the invention and within the claims regarded as the scope of the invention.

This application claims priority based on Japanese Patent Application No. 11-031234 for which it applied on February 9, 1999.

As described above, the capacitor 2 is made of a silicon nitrogen compound, whereby the capacitor can be formed without causing any dynamic change during the manufacturing process. Although the upper electrode is heat-treated at a temperature of, for example, 700 ° C. to form a peripheral circuit, the capacitor 2 does not deteriorate. In other words, the thermal stability of the capacitor film 2 is maintained. As a result, the capacitor and semiconductor element having such a capacitor have a high operational reliability.

Therefore, the capacitive element and the method of manufacturing the capacitive element of the present invention include a miniaturized element, for example, a highly integrated structure having a memory size of 256 mega or more, a DRAM having a transistor used in a logic circuit having a design rule of 0.25 mu m, It is beneficial when used and applied to.

Claims (12)

In the capacitive element: A lower electrode formed of silicon and having HSG on the surface; A capacitor film formed of silicon nitride and covering the surface of the lower electrode; And A capacitive element formed of a metal or an electrically conductive compound and composed of an upper electrode covering the capacitive layer. 2. The capacitor device of claim 1, wherein the upper electrode is made of a high melting point metal nitride or a high melting point metal oxide. The capacitor as claimed in claim 1, wherein the capacitor film has a stacked structure in which a silicon nitride film and a silicon oxide film are formed, and the upper electrode is formed on the silicon oxide film. The capacitor as claimed in claim 2, wherein the capacitor film has a stacked structure in which a silicon nitride film and a silicon oxide film are formed, and the upper electrode is formed on the silicon oxide film. In the capacitive element manufacturing method: Forming a bottom electrode made of silicon and having an HSG on the surface; Forming a capacitor film made of silicon nitride on the surface of the lower electrode; And Forming an upper electrode made of a metal or an electrically conductive compound on the capacitor film. The method of claim 5, wherein the forming of the lower electrode, the forming of the capacitor film, and the forming of the upper electrode are performed at a temperature of 700 ° C. or less. 7. The method of claim 6, wherein the forming of the upper electrode comprises forming the upper electrode by CVD. The method of claim 6, wherein the forming of the upper electrode comprises forming the upper electrode using a high melting point metal nitride or a high melting point metal oxide. The method of claim 7, wherein the forming of the upper electrode comprises forming the upper electrode using a high melting point metal nitride or a high melting point metal oxide. The method of claim 9, wherein the capacitive film forming step is Nitriding the surface of the lower electrode using a thermal nitriding technique; Forming a silicon nitride film on the lower electrode by using a CVD technique; And And oxidizing the surface of the silicon nitride film. A semiconductor device comprising the capacitor according to claim 1. A semiconductor device manufacturing method comprising the method of manufacturing a capacitor device according to claim 5