KR20000046530A - Small capacity exchange - Google Patents

Abstract

PURPOSE: A small capacity exchange having a T-T(Time switch-Time switch) structure without using an INS(Interconnection Network Subsystem) is provided. CONSTITUTION: A small capacity exchange is composed of a CCS(Central Control Subsystem)(100) and an ASS(Access Switching Subsystem)(110,120). The CCS(100) carries out overall control, operation and maintenance functions for the system. The ASS(110,120) is configured so as to transmit and receive PCM(Pulse Code Modulation) data with the CCS(100). The CCS(100) is composed of a central control processor(102), an auxiliary memory group(103), an operator interface group(104), a TP(Telephony Processor)(105), a network synchronization unit(106), an Ethernet & X.25 interface processor(107), a LAN link(108), an X.25 link(109) and a super performance control inter-working unit(101). The ASS(110,120) is composed of an access switching processor(111,121), a message switch control inter-working unit(112,122), a time switch & link unit(113,123), a TP(116,126), a local & global service interface unit(117,127), a subscriber/trunk interface unit(118,128) and an RI/SRI(119,129).

Description

Small SMALL SIZE SWITCHING SYSTEM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small capacity exchange, and more particularly, to a small capacity exchange implemented with a time switch-time switch (T-T) structure without an interconnection network subsystem.

The existing small capacity exchanger is configured to combine a single time switch (T_SW) into a redundant structure through the main processor (MP) and the L-bus. The single time switch has a capacity of less than 500 lines and its capacity is too small. There is this.

It is an object of the present invention to provide a small capacity exchanger that can accommodate more circuits than a conventional small capacity exchanger with a simple structure.

Another object of the present invention is to provide a small capacity exchanger implemented in a T-T structure without having a network subsystem (INS).

In order to achieve the above object, the apparatus according to the present invention comprises a central control subsystem (CCS) for performing the overall control, operation and maintenance functions of the small capacity exchanger; A system clock and frame pulse are received and operated from a network synchronizer (NES) provided in the central control subsystem (CCS), and the interaction controller (SPCI) in the central control subsystem (CCS) and the matching processor (ASP) in itself are operated. And two subscriber line and relay line matching subsystems with message transfer control unit (MSCI) that provide inter-processor communication channels to enable inter-processor communication between the system and inter-system communication to enable data transmission and reception between systems. It is characterized in that it is configured to directly transmit and receive data in the form of pulse code modulation between link units provided in each of the subsystems.

1 is a block diagram of a small capacity exchanger according to the present invention,

FIG. 2 is a detailed block diagram of the link unit provided in the time switch and link unit TSL shown in FIG.

<Explanation of symbols for main parts of drawing>

100: central control subsystem (CCS) 101: interaction control unit (SPCI)

102: central control processor (CCP) 103: auxiliary storage group

104: Operator matching group 105, 116, 126: Telephony processor (TP)

106: network controller (NES) 107: network matching processor (EXIP)

108: LAN link 109: X. 25 links

110, 120: Subscriber and trunk line matching subsystem (ASS)

111, 121: Matching Processor (ASP) 112, 122: Message Delivery Control Unit (MSCI)

113, 123: Time switch and link section (TSL)

114, 124: Time switch (T_SW)

115, 125: Link section

117, 127: Local and Global Service Matching Unit (LGSI)

118, 128: subscriber and trunk line matching unit 119, 129: remote switch matching unit (RI / SRI)

Hereinafter, embodiments of the present invention will be described in detail.

2 is a block diagram of a small capacity exchange in accordance with the present invention, including a Central Control Subsystem (hereinafter abbreviated as CCS) 100, CCS 100, which performs the overall control, operation and maintenance functions of the system. It consists of subscriber and access switching subsystem (abbreviated ASS) 110, 120 configured to transmit and receive pulse code modulation (PCM) data. The PCM data is directly transmitted and received between the link units 115 and 125 provided between the subscriber and the relay line matching subsystems 110 and 120, respectively.

More specifically, the CCS 100 may include a central control processor (CCP) 102, a disk unit (DKU), a magnetic tape unit (MTU), a digital audio tape recorder (DAT), a cartridge tape unit (CTU), and the like. Operator matching group 104 consisting of a secondary memory group 103, a personal computer (PC), a time display unit (also referred to as a VDU) and a print (PRT), a sub-processor telephony processor (Telephony Processor, also referred to as TP) 105, Network Synchronization Unit (hereinafter referred to as NES) having a redundant structure 106, Network Matching Processor (Eithernet & X.25 Interface Processor, hereinafter referred to as EXIP) 107, LAN link 108, X.25 link 109, and the aforementioned CCP 102, TP 105 and EXIP 107 to connect ASS 110, 120 and PCM data. Super Performance Control Inter-working (hereinafter referred to as SPCI) It consists of a box) 101.

ASS (110, 120) is a matching processor (Access Switching Subsystem, hereinafter abbreviated ASS) (111, 121), Message Switch Control Inter-working (abbreviated as MSCI) (112, 122), time switch and Link part (Time Switch & Link, hereinafter abbreviated as TSL) 113, 123, TP 116, 126, Local & Global Service Interface (abbreviated as LGSI) 117, 127 , Subscriber and trunk line matching units 118, 128, and remote switch matching unit (RI / SRI) 119, 129.

The exchange thus configured is configured as follows.

First, the ASPs 111 and 121 provide overall call processing functions including intelligent network call processing in the corresponding ASS 110 and 120, traffic control, switch control, maintenance in the ASS 110 and 120, and ASS 110 and 120. It performs maintenance and operation management, IPC (Inter-Processor Communication) message exchange, and other services.

The MSCIs 112 and 122 serve to transfer control messages between the distributed functional blocks and constitute an internal communication network of the exchange. Therefore, MSI provides the IPC message channel to enable interprocessor communication between the corresponding ASS (110, 120) and the ASS (110, 120), and monitors and controls various states of all nodes in the MSCI (112, 122). If necessary, the abnormal state is transmitted to the corresponding ASPs 111 and 121 in a message form through the IPC communication channel.

TPs 116 and 126 perform lower levels of work that require real-time processing of signals such as board hernia, malfunction detection and instantaneous analysis of devices in corresponding ASS 110 and 120.

The LGSIs 117 and 127 process PCM voice signals in order to perform a tertiary call or conference call (for example, 6 or 15 characters), and signals such as R2, Dual Tone Multi-Frequency (DTMF), and tone. It performs the function of transmitting and receiving related signals for service and monitoring and testing the operation status of the device. And under the various control from the corresponding TP (116, 126) to generate the necessary R2 MFC, DTMF and tone signal during the call connection and transmit to the corresponding TSL (113, 123) and the corresponding from the TSL (113, 123) Receives and detects signals. It has its own loop test function for maintenance, and if an alarm occurs, it reports to the corresponding TP (116, 126).

RI / SRI (119, 129) selectively performs RASM interface and SRASM interface. RI performs matching and signal processing function with RASM and E1 for RASM call processing, and SRI performs RASM or SRASM call processing. Perform signal processing by matching E1 with mother station.

Subscriber and trunk line matching units 118 and 128 provide analog subscriber monitoring, control and ring, and interface with subscribers in the telephony device, including analog general subscriber, public telephone subscriber, private branch exchange (PABX) subscriber, and Centrix ( CENTREX) Accept subscribers. It also supplies the call signal current and zero-crossing signals required for the subscriber circuit.

The TSLs 113 and 123 manage and manage data links such as multiplexing and demultiplexing functions of PCM data, insertion and extraction of IPC messages, and MP class processors (for example, ASPs 111 and 121) and TPs 116 and 126. Providing a message exchange path of the system, it acts as a message exchange path of MP-class processors between subsystems. Perform data error detection and clock extraction. In addition, it performs a switching function for time slots from peripheral devices and relay line method conversion (conversion between E1 / T1) by a lookup table method.

The TSLs 113 and 123 performing this function are composed of time switches (T_SW) 114 and 124 and link units 115 and 125, respectively. The link units 115 and 125 are shown in FIG. It is composed together.

Referring to FIG. 2, the link units 115 and 125 may include a first data receiver 201, a first latch 202, an L-bus matcher 203, a loop test processor 204, and a first data transmitter ( 205, second latch 206, second data transmitter 207, first clock selector 208, clock transmitter 209, read address generator 210, memory 211, write address generation A unit 212, a third latch 213, a second data receiver 214, a second clock selector 215, and an alarm collector 216 are provided.

The first data receiving unit 201 selects PCM data applied to one input terminal among PCM data transmitted from its time switches 114 and 124 through two data input terminals DATA (A) and DATA (B). To transmit. The selection criterion uses a corresponding valid bit. In other words, data is selected in which the corresponding valid data bits are actively transmitted. The selected data is sent to the first latch 202.

The first latch 202 is controlled by the loop test processor 204 to output the PCM data transmitted from the first data receiver 201 to one of the loop test processor 204 and the first data transmitter 205. . That is, in the normal mode, the PCM data controlled by the loop test processing unit 204 and transmitted from the first data receiving unit 201 is transmitted to the first data transmitting unit 205, and its own time switches 114 and 124 are used. In the case of a mode of testing a connection relationship with the network (called a front loop test), the PCM data transmitted from the first data receiver 201 is transmitted to the loop test processor 204. Accordingly, it is possible to test whether the connection state with the own time switches 114 and 124 is normal. On the other hand, in a mode of testing a connection relationship with other link units 125 and 115 in other ASSs 120 and 110 (called a rear loop test), the PCM data transmitted from the loop test processor 204 is removed. 1 is transmitted to the data transmitter 205. Accordingly, it is possible to test whether the connection state with the other link units 125 and 115 is normal.

The first data transmitter 205 sends the PCM data transmitted from the first latch 202 to the other link units 125 and 115 in the other ASSs 120 and 110.

The second data receiver 214 receives the PCM data transmitted from the other link units 125 and 115 described above and transmits it to the third latch 213. The third latch 213 transfers the applied PCM data to the memory 211.

The memory 211 writes the PCM data transferred from the third latch 213 to an address provided from the write address generator 212 (Write). The write address generator 212 is generated in synchronization with the clock signal provided from the second clock selector 215. The second clock selector 215 selects one of the redundant reception clocks provided from the other link units 125 and 115 and provides it to the write address generator 212.

In this way, the PCM data received from the other link units 125 and 115 written in the memory 211 are read and output by the address provided from the read address generator 210. The output PCM data is transmitted to the second latch 206.

The second latch 206 is controlled by the loop test processor 204 to transmit the PCM data transmitted from the memory 211 to the second data transmitter 207 in the normal mode. However, as described above, in the rear loop test, the PCM data transmitted from the memory 211 is transmitted to the loop test processor 204. Accordingly, as described above, the connection state with the other link units 125 and 115 can be checked. On the other hand, during the front loop test, the PCM data transmitted from the loop test processor 204 is transmitted to the second data transmitter 207 to test the connection relationship with the time switches 114 and 124 described above. .

Meanwhile, the read address generator 210 generates a corresponding read address in synchronization with the selected clock signal transmitted from the first clock selector 208.

When the system clock CP2 and the frame pulse FP2 provided in a redundant structure are received from the NES 106, the first clock selector 208 selects a clock having a normal period. Select the corresponding clock signal. The selected clock signal is transmitted to the read address generator 210 and the clock transmission processor 209, respectively.

The clock transmission processor 209 transmits the clock signal transmitted from the first clock selector 208 to the other link units 125 and 115.

The L-BUS matching unit 203 selects the control address, control data, address enable, data enable, read enable, write enable, and L bus transmitted from the corresponding TSL controller (not shown) via the L bus. It receives a signal and the like, and transmits control data, status data, and alarm information generated from the link units 115 and 125.

The alarm collecting unit 216 collects various alarms generated by the link units 115 and 125 and provides them to the TSL control unit not shown through the L bus matching unit 203.

On the other hand, the CCS 100 is a subsystem that performs the overall maintenance and preservation of the system, can be implemented as a workstation.

The SPCI 101 in the CCS 100 provides a passage between the CCP 102, the TP 105, and the EXIP 107 in the CCS 100, and the MSCI 112, which is provided in the ASS 110, 120. 122) and provide a path for direct transmission of PCM data.

CCP 102 oversees a series of operations and maintenance related functions in the system. Therefore, by controlling each device in the auxiliary storage device group 103 necessary for this to record the charge record, notification, maintenance, operation management information, and the like, the disk (DKU) contains a general program and data. And to control the communication between the operator and the system or between the operating center and the system controls the devices provided in the operator matching group 104.

The EXIP 107 handles a standardized protocol as a dedicated processor for matching with a network operation center, a charging center or another system. For this purpose, it accommodates 4 ports of LAN or X.25 link (108, 109), and operates a load share type link for the reliability of the link.

As described above, the present invention transmits and receives pulse code modulation (PCM) data between the central control subsystem and each subscriber and trunk line matching subsystem (ASS) without using a network subsystem (INS), and matches subscriber and trunk lines. Implementing to transmit the pulse code modulation data directly between the link (ASS) between the subsystems, has the advantage of having a simpler structure than the existing large-capacity switch, and can accommodate more lines than the small-capacity exchange. That is, the existing small capacity exchanger can accommodate about 500 lines or less, whereas the small capacity exchange proposed according to the present invention can accommodate about 3200 lines.

Claims (3)

For small capacity exchanger, A central control subsystem (CCS) that performs the overall control, operation and maintenance functions of the small capacity exchanger; A system clock and a frame pulse are received and operated from a network synchronizing unit (NES) provided in the central control subsystem (CCS), and the matching control unit (SPCI) in the central control subsystem (CCS) and a matching processor in itself ( And two subscriber line and relay line matching subsystems having a message transfer control unit (MSCI) for providing inter-processor communication channels to enable inter-processor communication between the system and inter-system communication to enable data transmission and reception between ASPs. And a pulse code modulation type data is directly transmitted and received between link sections respectively provided in the relay line matching subsystem. 2. The apparatus of claim 1, wherein the link unit transmits pulse code modulation data transmitted from a time switch in the subscriber and relay line matching subsystem to which the link unit belongs, and transmits the pulse code modulation data to another link unit included in another subscriber and relay line matching subsystem. The pulse code modulation data transmitted from the unit is configured to transmit to the time switch, and to test the connection state between the time switch and the link unit or the connection state between the link unit and another link unit. . The method of claim 1, wherein the link unit, A first data receiver for receiving pulse code modulation data transmitted from a time switch in the subscriber and relay line matching subsystem to which the subscriber belongs; A first data transmitter for transmitting the pulse code modulated data transmitted from the first data receiver to other link units provided in other subscriber and relay line matching subsystems; A second data receiver for receiving pulse code modulation data transmitted from the other link unit; A second data transmitter for transmitting the pulse code modulation data transmitted from the second data receiver to the time switch; When the link unit is set to a normal mode, a path for transmitting pulse code modulation data between the first data receiver and the first data transmitter is provided, and a mode for testing a connection state between the time switch and the link unit is provided. If set, provide a path for transmitting pulse code modulation data between the first data receiving unit and the second data transmitting unit, and if the mode for testing the connection state between the link unit and the other link unit is set, the second data receiving unit is set. A first latch providing a path for transmitting pulse code modulated data between the first data transmitter and the first data transmitter; When the link unit is set to a normal mode, a path for transmitting pulse code modulation data between the second data receiver and the second data transmitter is provided, and a mode for testing a connection state between the time switch and the link unit is provided. If set, a path for transmitting pulse code modulation data between the first latch and the second data transmission unit is provided, and if a mode for testing a connection state between the link unit and the other link unit is set, the first latch and the A second latch providing a path through which pulse code modulation data can be transmitted between the second data receivers; A loop test processor configured to control operations of the first latch and the second latch according to an applied test mode control signal; A clock transmission processor for transmitting a clock signal selected from the clock signals provided from the network synchronizer (NES) to the other link unit; Pulse code modulated data output from the second data receiving unit is written by a write address generated in synchronization with the clock signal transmitted from the other link unit, and pulses read by the read address generated in synchronization with the selected clock signal. And a memory for transmitting code modulation data to the second latch.