KR20000044917A - Row decoder circuit of flash memory cell - Google Patents

Abstract

PURPOSE: A row decoder circuit of a flash memory cell is provided to reduce the loading capacitance of a boot strap circuit in the bootstrap of a word line and to prevent the flow of a leakage current. CONSTITUTION: A low decoder circuit of a flash memory cell contains a first PMOS transistor(P11), a first triple P-well NMOS transistor(TN11), a second triple P-well NMOS transistor(TN12), and a second PMOS transistor(P12) and a third triple P-well NMOS transistor(TN13). The first PMOS transistor contains an N-well and a source connected to a first voltage source(VPPX) and a drain connected to a first node(K11). The first triple P-well NMOS transistor contains a source connected to the first node and a drain and a triple N-well connected to a fourth voltage source(Vcc). The second triple P-well NMOS transistor contains a source connected to the first node and a drain connected to a third voltage source(XCOM8). Moreover, the second PMOS transistor and the third triple P-well NMOS transistor are arranged for finally driving a word line.

Description

Row Decoder Circuit of Flash Memory Cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low decoder circuit, and in particular, in a wordline bootstrapping, a flash capable of reducing the load capacitance of the bootstrap circuit and preventing the flow of leakage current. The present invention relates to a row decoder circuit of a memory cell.

In general, a row decoder of a flash memory cell has a different voltage applied to a word line according to a function mode, resulting in a complicated circuit and a large layout area. In read and erase verify modes, the Vcc and 0V voltages are supplied to the word lines. In the program and program verification modes, a positive pumping voltage and a 0V voltage are supplied. In the erase mode, a negative pumping voltage and a 0V voltage are supplied.

1 is a block diagram of a flash memory device to which the present invention is applied. The command register 10 receives a predetermined bit of data DQ0 to DQN and addresses A0 to AM, respectively, and is operated by a write enable signal WEb. The state and looping control circuit 11 is driven according to the output signal of the command register 11 and the write enable signal WEb. The mode control circuit 9 outputs an output signal for controlling program, erase and read operations in accordance with the output signals of the state and looping control circuit 11. The input / output buffer 8 inputs and outputs data DQ0 to DQN according to the write enable signal WEb and the output enable signal OEb. The latch circuit 6 latches data input from the input / output buffer 8. In the memory cell array 1, a plurality of memory cells are connected in a matrix manner between a plurality of word lines WL0 to WLn and bit lines BL0 to BLn. The row decoder 2 selects the word lines WL0 to WLn of the memory cell array 1 according to the output signal of the mode control circuit 9. The column decoder 4 selects the bit lines BL0 to BLn through the Y-gating 3 circuit connected to the memory cell array 1. The Y-gating circuit 3 supplies the latched data to the latch circuit 6 to the bit line selected by the column decoder 4 according to the output signal of the mode control circuit 9, and also the column The bit line data selected by the decoder 4 is output to the input / output buffer 8 through the sense amplifier 5. The comparator 7 outputs a control signal by comparing the data output through the sense amplifier 5 with the data latched in the latch circuit 6. The control signal output from the comparator 7 controls the state and looping control circuit 11 and the mode control circuit 9.

In the present invention, the row decoder 2 circuit of the flash memory device of FIG. 1 will be described in detail.

2 is a row decoder circuit diagram of a conventional flash memory cell.

The output terminal of the row decoder circuit includes a third PMOS transistor P3 and an first triple-P well NMOS transistor TN1 in the form of an inverter for finally driving a word line. A gate of the first triple P-well NMOS transistor TN1 is connected to a first node K1, and a source is triple P-well of the first triple P-well NMOS transistor TN1. In addition, it is connected to the second voltage source VEEX and is negatively biased during an erase operation and biased to a ground potential (0V) during a program or read operation. A fourth voltage source Vcc is connected to the triple N-well of the first triple P-well NMOS transistor TN1. A gate of the third PMOS transistor P3 is connected to the first node K1, an N-well is connected to a first voltage source VPPX, and the first voltage source VPPX is a bootstrap circuit (not shown). Is connected to.

In addition, the N-well and the source of the second PMOS transistor P2 having the word line WL voltage as a gate input are connected to the first voltage source VPPX, and the drain is connected to the first node K1. do.

The source and N-well of the first PMOS transistor P1 are connected to the first voltage source VPPX, the drain is connected to the first node K1, and the first control voltage XRST is supplied to the gate.

A source of the NMOS transistor N1 is connected to the first node K1, a gate of which is connected to the second control voltage XPREAI, and a drain of the NMOS transistor N1 is connected to the third voltage source XCOM8.

This conventional row decoder circuit is composed of three PMOS transistors (P1 to P3), one triple P-well NMOS transistor (TN1) and NMOS transistor (N1), and therefore, due to loading in the bootstrapping circuit, Since the working factors are quite large, the load capacitance needs to be large during bootstrapping, and it takes a long time for the word line voltage to reach the desired voltage.

In a conventional row decoder circuit in which a precharge transistor is a PMOS transistor, when the first voltage source VPPX is bootstrapped and the voltage of the first voltage source VPPX is boosted to a voltage larger than the power supply voltage Vcc, Compared with the first control voltage XRST to which the voltage at the CMOS level is input, the gate-source voltage Vgs of the pull-up PMOS transistor P1 becomes equal to or greater than the threshold voltage Vt, and thus the second control voltage XPREAI. Is selected and a leakage current occurs in the selected row decoder circuit in which the third voltage source XCOM8 falls to the ground level.

Accordingly, the present invention separates the triple N-well of the triple P-well NMOS transistor from the voltage source supplied through the pull-up PMOS transistor in the bootstrap circuit, and supplies the power voltage to the triple N-well of the triple P-well NMOS transistor. Accordingly, an object of the present invention is to provide a row decoder circuit of a flash memory cell that can solve the above disadvantage.

In order to achieve the above object, a row decoder circuit of a flash memory cell according to the present invention includes an N-well and a source connected to a first voltage source, a drain connected to a voltage regulation node, and a word line voltage as a gate input. A first PMOS transistor, a source connected to a voltage regulation node, a drain and a triple N-well connected to a fourth voltage source, a first triple P-well NMOS transistor whose gate input is a first control voltage, and a source; Connected to a voltage regulation node, a drain connected to a third voltage source, triple P-wells connected to a second voltage source, triple N-wells respectively connected to the fourth voltage source, and a second control voltage to the gate input. A second triple P-well NMOS transistor, a second PMOS transistor of an inverter type for finally driving a word line according to the voltage of the voltage adjusting node; And a third triple-P well NMOS transistor.

1 is a block diagram of a flash memory device to which the present invention is applied.

2 is a conventional row decoder circuit diagram.

3 is a row decoder circuit diagram in accordance with the present invention.

4 is a triple P-well bias circuit diagram.

<Explanation of symbols for the main parts of the drawings>

N1: NMOS transistor

P1 to P3, P11, and P12: PMOS transistors

TN1 and TN11 to TN13: Triple P-well NMOS Transistors

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a row decoder circuit diagram of a flash memory cell according to the present invention.

The output terminal of the row decoder circuit is composed of a second PMOS transistor P12 of an inverter type and a third triple-P well NMOS transistor TN13 for finally driving a word line. A gate of the third triple P-well NMOS transistor TN13 is connected to a first node K11, which is a voltage regulation node, and a source is connected to the third triple P-well NMOS transistor TN13. It is connected to the second voltage source VEEX together with the triple P-well, and is biased to a negative bias during erasing operation and to a ground potential (0V) during program or read operation. A fourth voltage source Vcc is connected to the triple N-well of the third triple P-well NMOS transistor TN13. A gate of the second PMOS transistor P12 is connected to the first node K11, an N-well is connected to a first voltage source VPPX, and the first voltage source VPPX is a bootstrap circuit (not shown). Is connected to. In addition, the N-well and the source of the first PMOS transistor P11 having the word line WL voltage as a gate input are connected to the first voltage source VPPX, and the drain is connected to the first node K11. do.

A first triple P-well NMOS transistor TN11 has a source connected to the first node K11, a gate of which is a first control voltage XRST, and a drain of the first triple P-well NMOS transistor TN11. It is connected to the fourth voltage source Vcc together with the triple N-well of (TN11).

The second triple P-well NMOS transistor TN12 has a source connected to the first node K11, a gate of which receives a second control voltage XPREAI, which is an output of a low predecoder, and a drain of a third voltage source. It is connected to (XCOM8). The triple P-well of the second triple P-well NMOS transistor TN12 is connected to the second voltage source VEEX, and the triple N-well is connected to the fourth voltage source Vcc.

Assuming that 256 row decoder circuits configured as described above are configured in one sector, a loading state in the first voltage source VPPX will be described as follows.

Since only one of the first sectors will be selected, the first node K11, which is a voltage adjusting node of the row decoder circuit, becomes the ground voltage level Vss level, and the second PMOS transistor P12 is turned on. At this time, the voltage supplied from the first voltage source VPPX through the second PMOS transistor P12 is supplied to the word line WL. Meanwhile, the remaining 255 unselected row decoder circuits charge the voltage of the first node K11 to the power supply voltage Vcc level to discharge the word line WL to the ground level Vss.

Accordingly, the element acting as a loading in the first voltage source VPPX may be a word line WL connected to the selected row decoder circuit and a first node K11 of the remaining unselected row decoder circuits. A loading value (ie, gate capacitance of the second PMOS transistor P12 and the third triple P-well NMOS transistor TN13), and the first and first triple P-well NMOS transistors TN11 and TN12. Junction capacitance, and when the second voltage source XPREAI is selected, the loading value toward the third voltage source XCOM8 and the N-well of the first PMOS transistor P11. In the conventional low decoder circuit, an N-well and a P-sub of a pull-up PMOS transistor, that is, a first PMOS transistor P1 having a first control voltage XRST as a gate input, are provided. Has additional loading capacitance Since the source of the PMOS transistor P1 is connected to the first voltage source VPPX, the first node K1 is precharged from the first voltage source VPPX when it is precharged. charge) is transferred. Therefore, in the conventional row decoder circuit, the gate capacitance of the first triple P-well NMOS transistor TN1 is included in the loading value of the first voltage source VPPX.

However, in the present invention, by supplying the voltage of the first node (K11) from the fourth voltage source (Vcc), it is possible to reduce the loading capacitance in the bootstrapping circuit.

However, in the conventional row decoder circuit in which the precharge transistor is a PMOS transistor, when the first voltage source VPPX is bootstrapping and the voltage of the first voltage source VPPX is boosted to a voltage larger than the power supply voltage Vcc, Compared with the first control voltage XRST to which the voltage of the CMOS level is input, since the gate-source voltage Vgs of the pull-up PMOS transistor becomes equal to or greater than the threshold voltage Vt, the second control voltage XPREAI is selected. A leakage current occurs in the selected row decoder circuit in which the third voltage source XCOM8 falls to the ground level.

However, in the present invention, the loss of the bootstrap charge from the bootstrapped node to the ground node is not generated by separating the current path from the first voltage source VPPX and applying the power supply voltage Vcc.

FIG. 4 is a triple P-well bias circuit diagram according to the present invention, in which a PMOS transistor P21 and a first resistor R21 having a control signal CS as an input between a power supply terminal Vcc and a first node K21. This series is connected in series, and a second resistor R22 is connected between the first node K21 and the ground terminal Vss. An NMOS transistor N21, which is a pull-up transistor that receives the voltage of the first node K21 as an input, is connected between the power supply terminal Vcc and the output node VEEX. The bipolar transistor B21 is connected between the output node VEEX and the ground terminal Vss.

The bipolar transistor 21 has a collector and a base connected to the output node VEEX and an emitter connected to the ground terminal Vss to operate as a diode.

A bias voltage corresponding to about 60% of the power supply voltage Vcc is applied to the gate of the NMOS transistor N21, and a bipolar transistor B21 having a base and a collector connected to each other as a pull-down transistor is connected. It is possible to apply a bias voltage (V _BE : 0.6V) to the triple P-well. Therefore, when the word line WL is discharged as the threshold voltage Vt of the triple P-well NMOS transistor TN2 of FIG. 3 decreases, that is, when the first node K11 becomes high, The power supply voltage Vcc is not transferred to the first node K11 as a fail, and the threshold voltage Vt of the triple P-well NMOS transistor TN2 is dropped.

As described above, according to the present invention, the triple N-well of the triple P-well NMOS transistor is separated from the voltage source supplied through the pull-up PMOS transistor in the bootstrap circuit, and the power supply voltage is the triple N-well of the triple P-well NMOS transistor. By providing this, it is possible to reduce the loading capacitance in the bootstrapping circuit and to eliminate the leakage current flowing in the selected row decoder circuit after the bootstrapping, thereby having an excellent effect of preventing the loss of the bootstrap charged. .

In addition, by applying a back bias voltage (VBE: 0.6V) to the triple P-well of the triple P-well NMOS transistor, the threshold voltage Vt drop of the NMOS transistor during the word line WL discharge is dropped. It can alleviate the phenomenon.

Claims (5)

A first PMOS transistor having an N-well and a source connected to a first voltage source, a drain connected to a voltage regulation node, and having a word line voltage as a gate input; A first triple P-well NMOS transistor having a source connected to the voltage regulation node, a drain and a triple N-well connected to a fourth voltage source, the first control voltage being a gate input; A source is connected to the voltage regulation node, a drain is connected to a third voltage source, a triple P-well is connected to a second voltage source, a triple N-well is connected to the fourth voltage source, respectively, and a second control voltage is applied. With a second triple P-well NMOS transistor as the gate input, And a second PMOS transistor and a third triple-P well NMOS transistor of an inverter type for finally driving a word line according to the voltage of the voltage adjusting node. The method of claim 1, Further comprising a triple P-well bias circuit for supplying a back bias to the triple P-well of the first to third triple P-well NMOS transistor to prevent the drop of the threshold voltage when the word line voltage discharges; And a row decoder circuit of a flash memory cell. The method of claim 2, The triple P-well bias circuit includes a PMOS transistor and a first resistor connected in series between a power supply terminal and a first node; A second resistor connected between the first node and a ground terminal; A pull-up transistor connected between the power supply terminal and an output node and receiving a voltage of the first node as an input; And a bipolar transistor connected between the output node and the ground terminal. The method of claim 3, wherein And the bipolar transistor is connected to a collector and a base to the output node and an emitter is connected to a ground terminal to operate as a diode. The method of claim 3, wherein And the pull-up transistor comprises an NMOS transistor.