KR20000044663A - Adder for area improvement - Google Patents

Abstract

PURPOSE: An adder for area improvement is provided to reduce implementation area of a adder. CONSTITUTION: A adder for area improvement consists of a first unit addition means that generates a first carry signal and a first part sum about lower four bits among a first and second data, a second unit addition means, a second part sum and the carry prediction circuit part. The adder divide the first and the second data by an arbitrary bit number and generates the part sum. Then the machine decides whether the machine will add the results of the part sum or not through the carry prediction circuit. And the machine outputs the final result of addition.

Description

Adder for Area Improvement

The present invention relates to an arithmetic device, and more particularly to an adder for performing an addition operation on first and second data.

Adders are used in digital signal processors, high performance microprocessors and microcontrollers as processor speed increases and users demand more multimedia data processing. It is used in various ways, and the number of bits of data to be processed gradually increases, and a fast addition operation is required.

Carry select adders, which have a high operating speed and easy to expand the number of bits of data to be added, are generally used.

1 shows a block diagram of an 8-bit carry select adder according to the prior art.

As shown in the figure, the 8-bit carry select adder adds the lower four bits A [3: 0], B [of the first and second data A [7: 0], B [7: 0] to be added. 3: 0]) to output a sum (Sum [3: 0]) for the lower 4 bits, and a carry from the lower 4 bits adder 100. Assuming that it will occur (ie, C0 = 1), the upper 4 bits of the first and second data A [7: 0] and B [7: 0] in parallel with the lower 4 bit adder 100 No carry occurs from the upper 4-bit adder 110 and the lower 4-bit adder 100 that receives and adds A [7: 4] and B [7: 4]) (ie, C0 = 0). ) And the upper four bits (A [7: 4], B of the first and second data A [7: 0], B [7: 0]) in parallel with the lower four-bit adder 100. [7: 4]) input from the upper four-bit adder 120 and the upper four-bit adder 110 in response to a carry signal C0 generated by the lower four-bit adder 100. Sum for 4 bits (Sum1 [7: 4]) and the sum (Sum0 [7: 4]) for the top 4 bits from the upper 4 bit adder 120 to select the final sum (Sum [7: 4]), the carry signal C1 generated from the upper four-bit adder 110 and the upper four bits in response to the carry signal C0 generated by the multiplexer 130 and the lower four-bit adder 100. The multiplexer 140 selects one of the carry signals C2 generated from the adder 120 and outputs the final carry signal COUT for the upper 4 bits.

Referring to Fig. 1, the operation principle of the carry select adder is described below.

The 8-bit first and second data (A [7: 0], B [7: 0]) to be added are divided into 4 bits, respectively, and an addition operation is performed for the lower 4 bits through the lower 4 bit adder 100. The adder for the upper 4 bits is simultaneously performed through the upper 4 bits adders 110 and 120. At this time, since it is not possible to know whether a carry signal is generated by the addition operation when the addition operation of the lower 4 bit adder 100 is not completed, the upper 4 bit adder 110 is the lower 4 bit adder 100. Assuming that a carry signal C0 is generated from the upper 4 bits, the add operation is performed, and the upper 4 bits adder 120 does not generate a carry signal C0 from the lower 4 bits adder 100. Assuming that an add operation is performed for the upper 4 bits, and then the add operation of the lower 4 bit adder 100 is completed, the upper 4 bit adder in the multiplexers 130 and 140 is output as a carry signal C0. Select one of sum (Sum1 [7: 4], Sum0 [7: 4]) and carry signals (C1, C2) output from (110, 120), respectively, and add the final sum (Sum [7: 4]) and the final one. Output by the carry signal (COUT).

Therefore, such a carry selection adder has a faster addition speed than other adders that perform an addition operation for the upper bits after the addition operation for the lower bits is completed, and the expandability of the number of data bits to be added is easy.

On the other hand, there is a problem that the total implementation area of the adder is increased due to the additional addition module performing the addition operation for the upper 4 bits and the multiplexer operating in response to the carry signal C0 as described above.

The present invention has been made to solve the above problems, by dividing the first and second data to be added by an arbitrary number of bits, respectively, generating a subtotal, and determining whether to increase the subtotal result through a carry prediction circuit. The purpose is to provide an adder for area improvement, which outputs the final addition result (final sum and final carry signal).

1 is a block diagram of an 8-bit carry select adder according to the prior art.

2 is a block diagram of one embodiment of an 8-bit adder in accordance with the present invention.

3 is another embodiment block diagram of an 8-bit adder in accordance with the present invention.

4 is an internal circuit diagram of the increasing part of FIGS. 2 and 3 according to the present invention;

5 is a block diagram of one embodiment of a 32-bit adder in accordance with the present invention.

* Description of the main parts of the drawing

200: lower 4 bit adder

210: high 4 bit adder

220: increasing portion

230: carry prediction circuit

The present invention for achieving the above object is an N-bit adder for adding the first data and the second data consisting of the first to N-th bit, the first and second data is divided into an arbitrary M bit of the M bit A first unit adding means, a second unit adding means, and l (where N = M × (l + 2)) third units for performing addition operations on first data and the second data of M bits, respectively; And an adding means, wherein the first unit adding means performs an addition operation on the least significant M bits of the first and second data to output the sum and the first carry signal for the least significant M bits, and The two unit adding means may include: a first addition circuit unit configured to perform an addition operation on a next first higher M bit of the first and second data to output a first subtotal and a second carry signal of the M bits; First increasing means for "1" increasing a first subtotal from said first adding circuit portion in response to said first carry signal; And a first carry prediction circuit unit configured to receive a first partial sum and a second carry signal and the first carry signal from the first adder circuit unit, and to predict and output a partial carry signal, wherein the l third unit adding means A second addition circuit unit for performing an addition operation on the M bits of the first and second data to output a partial sum of the M bits and a carry signal, respectively; Second increasing means for incrementing the subtotal from the second adding circuit portion by one in response to the partial carry signal output from the previous lower unit adding means of the unit adding means; And a second carry prediction circuit unit configured to receive a partial sum and carry signal from the second addition circuit unit and the partial carry signal to predict and output a final carry signal, wherein the second carry prediction circuit unit is configured to estimate and output an N bit of the first and second data. The synthesis is output from the first unit adding means, the first and second increasing means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is an embodiment block diagram of an adder according to the present invention, which is an adder for 8-bit first and second data when there is no carry input (CIN).

As shown in the figure, the 8-bit adder according to the present invention is the lower 4 bits A [3: 0], among the first and second data A [7: 0], B [7: 0] to be added. B [3: 0]) is added to output the subtotals PS [3: 0] and the carry signal Cout0 for the lower 4 bits, and the subtotals PS [3: 0] for the lower 4 bits. Lower 4 bit adder 200 outputting the final sum Sum [3: 0] of the adder, and upper 4 of the first and second data A [7: 0] and B [7: 0] to be added. Higher 4-bit adder 210 that adds bits A [7: 4] and B [7: 4] to output the subtotals PS [3: 0] and carry signal Cout1 for the upper 4 bits. In response to the carry signal Cout0 from the lower 4 bit adder 200, the partial sum PS [3: 0] for the upper 4 bits output from the upper 4 bit adder 210 is increased by “1”. Partial sum (PS [3: 0]) and carry signal (Cout1) for the upper four bits output from the incrementer 220 and the upper four-bit adder 210 that are output as the final sum Sum [7: 4]. ) And the final carry signal COUT for the first and second data A [7: 0] and B [7: 0] to be received by adding the carry signal Cout0 from the lower 4-bit adder 200. The carry prediction circuit unit 230 predicts and outputs the signal.

In this case, the carry prediction circuit 230 may include an AND gate 231 for receiving and logically multiplying each bit value of the partial sum PS [3: 0] for the upper 4 bits output from the upper 4 bit adder 210, The carry signal from the AND gate 232 and the upper 4-bit adder 210 that receive and output the output signal of the AND gate 231 and the carry signal Cout0 from the lower 4-bit adder 200. A logic sum gate 233 that receives the output signal of Cout1 and the AND gate 232 and performs an OR operation.

Referring to Fig. 2, the operation principle of the 8-bit adder according to the present invention is described below.

The 8-bit first and second data A [7: 0] and B [7: 0] to be added are divided into 4 bits, respectively, and the lower 4 bits A [3] through the lower 4-bit adder 200. : 0], add operation for B [3: 0]), and add operation for upper 4 bits A [7: 4] and B [7: 4] through the upper 4-bit adder 210. The lower 4-bit adder 200 outputs the final sum Sum [3: 0] and the carry signal Cout0, and the upper 4-bit adder 210 performs the partial sum PS [3: 0] and The carry signal Cout1 is output. The incrementer 220 receives the partial sum PS [3: 0] from the upper 4-bit adder 210 and the carry signal Cout0 from the lower 4-bit adder 200 is "1". "1" is added to the partial sum PS [3: 0] and output as the final sum Sum [7: 4], and the carry signal Cout0 from the lower four-bit adder 200 is "0". In this case, the subtotals PS [3: 0] are output as the final sums Sum [7: 4].

On the other hand, the carry signal Cout1 is generated from the upper 4 bit adder 210 (Cout1 = "1"), or the carry signal Cout0 is generated from the lower 4 bit adder 200 (Cout0 = "1"). ) First and second data A [7: 0] and B [7: 0 when all bit values of the subtotal PS [3: 0] from the upper four-bit adder 210 are "1". "1" is output as the final carry signal (COUT) for]). Therefore, the carry prediction circuitry 230 multiplies all the bit values of the partial sum PS [3: 0] through the AND gate 231, and then ORs the result of the AND and the carry signal Cout0 again. The final carry signal COUT is output in conjunction with (Cout1).

As an example, a case in which 8-bit first data A [7: 0] = "11101010" and second data B [7: 0] = "11011001" is added through the adder of the present invention. . First, the carry signal Cout0 of the sum (Sum [3: 0]) "11" and "1" for "1010" and "1001" is output from the lower four-bit adder 200, and the upper four bits are added. The carry signal Cout1 of "1011" and "1" is output from the unit 210 for the subtotals PS [3: 0] for "1110" and "1101". The increasing unit 220 outputs the final sum Sum [7: 4] by increasing the partial sum PS [3: 0] by 1 by the carry signal Cout0 of “1”. do. Therefore, the final sum sum (Sum [7: 0]) of 8-bit first data A [7: 0] = "11101010" and the second data B [7: 0] = "11011001" " 11000011 "is output. Next, the last carry signal COUT of "1" is output from the OR gate 233 of the carry prediction circuit 230 by the carry signal Cout1 of "1".

3 is another block diagram of an adder according to the present invention, which is an adder for 8-bit first and second data in the case of a carry input (CIN).

As shown in the figure, the 8-bit adder according to the present invention is the lower 4 bit data A [3: 0] of the first and second data A [7: 0] and B [7: 0] to be added. , The lower four-bit adder 300 for outputting the partial sum PS [3: 0] and the carry signal Cout0 for the lower four bits by adding B [3: 0]), and the first and second to be added. Add the upper four bits (A [7: 4], B [7: 4]) of the data (A [7: 0], B [7: 0]) to add the subtotals of the upper four bits (PS [3: 0] ]) And a partial sum (PS [3] of the lower four bits output from the lower four-bit adder 300 in response to the carry input signal CIN and the upper four-bit adder 310 for outputting the carry signal Cout1. : 0]) increases by 1 and outputs the final sum Sum [3: 0] as an incrementer 320 and a partial sum PS4 of the lower 4 bits output from the lower 4 bits adder 300. : 0]) and the partial carry signal for the lower 4 bits of the first and second data A [7: 0] and B [7: 0] by receiving the carry signal Cout0 and the carry input signal CIN. Yes (PC) In response to the partial carry signal PC from the carry prediction circuit unit 340 and the carry prediction circuit unit 340 outputting side by side, the partial sum PS 4 of the upper four bits output from the upper four bit adder 310 (PS [3:]). 0]) is increased by “1” and the sub-sum (PS [3 :) for the upper four bits output from the increasing unit 330 and the upper four-bit adding unit 310 that are output as the final sum Sum [7: 4]. 0]) and first and second data A [7: 0] and B [7: 0] to be received by adding the carry signal Cout1 and the partial carry signal PC from the carry prediction circuit unit 340. The carry prediction circuit unit 350 predicts and outputs a final carry signal COUT.

In this case, the carry prediction circuit unit 340 may receive a logical AND gate 341 for receiving and bitwise multiplying each bit value of the partial sum PS [3: 0] for the lower 4 bits output from the lower 4 bit adder 300; A carry signal Cout0 and an AND gate 342 from the AND gate 342 and the lower four-bit adder 300 that receive and AND the output signal of the AND gate 341 and the carry input signal CIN. And an OR gate 343 for receiving an OR signal.

In addition, the carry prediction circuit unit 350 may receive a logical AND gate 351 for receiving and bitwise multiplying each bit value of the partial sum PS [3: 0] for the upper four bits output from the upper four bit adder 310, Logic gate 352 for receiving and outputting the output signal of the AND gate 351 and the partial carry signal PC from the carry prediction circuit unit 340 and the carry signal Cout1 from the upper 4 bit adder 310. ) And an OR gate 353 for receiving and outputting the output signal of the AND gate 352.

Referring to Fig. 3, the operation principle of the 8-bit adder according to the present invention when there is a carry input signal CIN is described below.

The eight bits of the first and second data A [7: 0] and B [7: 0] to be added are divided into four bits, respectively, and the lower four bits A [3] are added through the lower four-bit adder 300. : 0], add operation for B [3: 0]), and add operation for upper 4 bits A [7: 4] and B [7: 4] through upper 4 bit adder 310. The lower 4 bit adder 300 outputs a subtotal PS [3: 0] and a carry signal Cout0 for the lower 4 bits, and the upper 4 bit adder 310 subtotals the upper 4 bits. (PS [3: 0]) and the carry signal Cout1 are output. The incrementer 320 receives the partial sum PS [3: 0] from the lower four-bit adder 300, and when the carry input signal CIN is "1", the incrementer PS [ 3: 0]) and adds "1" to the final sum (Sum [3: 0]). When the carry input signal (CIN) is "0", the subtotal (PS [3: 0] for the lower 4 bits is added. ]) Is output as the final sum (Sum [3: 0]). On the other hand, the carry signal Cout0 is generated from the lower 4 bit adder 300 (Cout0 = "1"), or the carry input signal CIN is "1" and the partial sum from the lower 4 bit adder 300 ( The partial carry signal PC for the lower four bits of the first and second data A [7: 0], B [7: 0] when all the bit values of PS [3: 0] are "1". "1" is output. Accordingly, the carry prediction circuit unit 340 performs an AND operation on the bit-wise gate 341 to logically multiply all the bit values of the subtotals PS [3: 0] for the lower four bits, and to multiply the result of the AND and the carry input signal CIN. After the logical multiplication, the logic unit performs a logic OR with the carry signal Cout0 to output a partial carry signal PC.

The incrementer 330 receives the partial sum PS [3: 0] from the upper four bit adder 310 and, when the partial carry signal PC is “1”, the incremental sum PS for the upper four bits. 3: 0]) and adds "1" to the final sum (Sum [7: 4]), and when the partial carry signal PC is "0", the partial sum (PS [3: 0) for the upper 4 bits. ]) Is output as the final sum (Sum [7: 4]). On the other hand, the carry signal Cout1 is generated from the upper 4 bit adder 310 (Cout1 = "1"), or the partial carry signal is "1" and the partial sum from the upper 4 bit adder 310 (PS [3]). "1" is output as the final carry signal COUT for the first and second data A [7: 0], B [7: 0] when all bit values of: 0]) are "1". do. Therefore, the carry prediction circuit unit 350 multiplies all the bit values of the subtotals PS [3: 0] for the upper four bits through the AND gate 351 and multiplies the AND result and the partial carry signal PC. After the logical multiplication again, the logical AND of the carry signal (Cout1) and outputs the final carry signal (COUT).

For example, when the carry input signal CIN is "1", the 8-bit first data A [7: 0] = "11101010" and the second data B through the adder according to the present invention of FIG. [7: 0] = "11011001") will be described. First, a carry signal (Cout0) of "11" and "1" is output from the lower 4 bit adder 300 for the subtotals PS [3: 0] for "1010" and "1001", and the upper 4 bits are added. The carry signal Cout1 of the subtotals PS [3: 0], "1011" and "1" for "1110" and "1101" is output from the unit 310. Then, the incrementing unit 320 adds the final sum "Sum [3: 0" in which the partial sum PS [3: 0] "11" is increased by "1" by the carry input signal CIN of "1". ], And the partial carry signal PC of "1" is output from the OR gate 343 of the carry prediction circuit part 340 by the carry signal Cout0 of "1".

In addition, the increment unit 330 finally adds "1100" by increasing the partial sum signal PS [3: 0] "1011" for the upper 4 bits by "1" by the partial carry signal PC of "1". Sum [7: 4]). Therefore, when the carry input signal CIN is "1", 8-bit first data A [7: 0] = "11101010" and second data B [7: 0] = "11011001" are added. It outputs one final sum (Sum [7: 0]) "11000100". Next, the last carry signal COUT of "1" is output from the OR gate 353 of the carry prediction circuit unit 350 by the carry signal Cout1 of "1".

FIG. 4 is an internal circuit diagram of the increasing part of FIGS. 2 and 3 according to the present invention, and includes a 4-bit input signal IN [3: 0] (partial sum PS of FIGS. 2 and 3 PS [3: 0]). )) And a control signal Control (the carry signal Cout0 of FIG. 2 or the partial carry signal PC or the carry input signal CIN of FIG. 3) are operated.

As shown in the figure, the increasing unit receives an exclusive OR by receiving an input signal IN [0] and a control signal Control 400, an input signal IN [0], and a control signal Control. The logical AND gate 401 for receiving and logically multiplying the input signal IN [1] and the exclusive logical OR gate 402 for receiving the exclusive OR of the signals from the AND gate 401 and the input signal IN [0: 1]) and an exclusive OR gate 404 that receives and ORs a signal from an AND signal IN, an input signal IN [2], and an AND gate 403. ), A signal from an AND gate 405, an input signal IN [3], and an AND gate 405 that receive and AND the input signal IN [0: 2] and the control signal Control. An exclusive AND gate 406 that receives and ORs exclusively, and includes an exclusive AND gates 400, 402, 404, The output signal OUT [0: 3] (Sum in Figs. 2 and 3 above) is output from the 406, respectively.

That is, the Nth output signal OUT [N] is output when the control signal is "1" and all the bits of the input signal [N-1: 0] are "1" and the input signal IN [N] is inverted. In other cases, the input signal IN [N] is output as it is.

5 is a block diagram of an embodiment of a 32-bit adder according to the present invention, which is a 32-bit adder implemented using the 8-bit adder of FIGS. 2 and 3.

As shown in the figure, the 32-bit adder according to the present invention divides the first and second data A [31: 0] and B [31: 0] to be added by 8 bits to perform an addition operation. An 8-bit adder 500 that performs an addition operation for the least significant 8-bit is implemented by the 8-bit adder of FIG. 2 without a carry input signal, and the remaining 8-bit adders 510 to 530 have the carry input signal. Implemented by three 8-bit adders. Therefore, even if the number of bits of data to be added increases, it is possible to simply implement the serial configuration of the adders as shown in FIG.

Here, the critical path delay of the 32-bit adder shown in FIG. 5 is calculated. First, the delay up to the carry signal Cout0 of the 8-bit adder is " Cout0 operation delay of the 4-bit adder " + " operation delay of the carry prediction circuit ", and " arithmetic delay of the carry prediction circuit " Gate delay " + " two input AND gate delay ", the delay of the four input AND gate can be canceled because the output time of the subtotal PS [3: 0] is shorter than the output time of Cout0.

Therefore, the total delay of the 32-bit adder according to the present invention is " Cout0 operation delay of the 4-bit adder " + " 2 input AND gate delay × 7 " + " 2 input AND gate delay × 7 ".

On the other hand, when a 32-bit adder is configured using a conventional carry select adder, the total delay becomes "Cout0 operation delay of a 4-bit adder" + "2: 1 multiplexer delay x 7".

As a result, when the 2: 1 multiplexer delay is equal to two gate delays, it is possible to construct the adder of the present invention having the same operation speed with a smaller area compared to the conventional carry select adder.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the first and second data to be added are divided by an arbitrary number of bits, and each is added to generate a subtotal, and the final sum and the final are determined by determining whether to increase the result of the subtotal generated through the carry prediction circuit. By implementing the carry signal, the implementation area can be reduced while maintaining the same operation speed as the conventional adder.

Claims (10)

In the N-bit adder for adding the first data and the second data consisting of the first to Nth bits, First unit adding means, second unit adding means, and l (1) for dividing the first and second data into arbitrary M bits and performing an addition operation on the first data of the M bits and the second data of the M bits, respectively; Provided that N = M × (l + 2) third unit addition means, The first unit adding means, Perform an addition operation on the least significant M bits of the first and second data to output a sum and a first carry signal for the least significant M bits, The second unit adding means, A first addition circuit unit configured to perform an addition operation on a next first higher M bit of the first and second data to output a first partial sum of the M bits and a second carry signal; First increasing means for "1" increasing a first subtotal from said first adding circuit portion in response to said first carry signal; And A first carry prediction circuit unit configured to receive a first partial sum and a second carry signal and the first carry signal from the first adder circuit unit, and predict and output a partial carry signal; The l third unit adding means, respectively A second addition circuit unit configured to perform an addition operation on M bits of the first and second data to output a partial sum of M bits and a carry signal; Second increasing means for incrementing the subtotal from the second adding circuit portion by one in response to the partial carry signal output from the previous lower unit adding means of the unit adding means; And A second carry prediction circuit unit configured to receive the partial sum and carry signals from the second addition circuit unit and the partial carry signal, and predict and output a final carry signal; And a final sum of N bits of the first and second data is output from the first unit adding means, the first and second increasing means. The method of claim 1, wherein the first and second carry prediction circuit unit, First logical AND means for receiving and multiplying each bit value of the subtotals respectively input to the carry prediction circuitry; Second logical AND means for receiving and outputting the output signal from the first AND product and the partial carry signal input to the first carry signal or the carry prediction circuit unit; And Logic sum means for receiving and carrying the carry signal from the addition circuit portion and the output signal from the second AND product N-bit adder comprising a. In the 8-bit adder for adding the first data and the second data consisting of 8 bits when there is no carry input signal input from the outside, First unit adding means for adding a lower four bits of the first and second data to output a first partial sum and a first carry signal for the lower four bits; Second unit adding means for adding a higher four bits of the first and second data to output a second partial sum and a second carry signal for the upper four bits; Increasing means for "1" increasing the second subtotal output from the second unit adding means in response to a first carry signal from the first unit adding means; And The second partial sum from the second unit adding means, the second carry signal, and the first carry signal from the first unit adding means are received to predict a final carry signal for the first and second data. A carry prediction circuit unit for outputting And the final sum of the 8-bit adders is output from the first unit adding means and the increasing means. The carry prediction circuit unit of claim 3, First logical AND means for receiving and multiplying each bit value of the second subtotal from the second unit adding means; Second logical AND means for receiving and outputting the output signal from the first AND product and the first carry signal from the first unit addition means; And Logic sum means for receiving and ORing the second carry signal from the second unit addition means and the output signal from the second AND product 8-bit adder comprising a. The method of claim 3, wherein the increasing means, First exclusive logical sum means for receiving an exclusive logical OR based on the first bit value of the second partial sum and the first carry signal output from the second unit adding means; First AND product for receiving and ORing the first bit value and the first carry signal; Second exclusive OR means which receives an exclusive OR of the second bit value of the second subtotal and the signal from the first AND product output from the second unit adding means; Second logical AND means for receiving and ANDing the first and second bit values and the first carry signal; Third exclusive OR means for receiving and ORing the third bit value of the second subtotal and the signal from the second AND product output from the second unit adding means; Third logical AND means for receiving and ORing the first to third bit values and the first carry signal; And Fourth exclusive OR means for receiving and ORing the fourth bit value of the second subtotal and the signal from the third AND product output from the second unit adding means; 8-bit adder comprising a. In the 8-bit adder for adding the first data and the second data consisting of 8 bits when there is a carry input signal input from the outside, First unit adding means for adding a lower four bits of the first and second data to output a first partial sum and a first carry signal for the lower four bits; Second unit adding means for adding a higher four bits of the first and second data to output a second partial sum and a second carry signal for the upper four bits; First increasing means for "1" increasing the first subtotal output from the first unit adding means in response to the carry input signal; A first partial sum output from the first unit adding means, a first carry signal and a carry input signal; a first carry for predicting and outputting a partial carry signal for the lower 4 bits of the first and second data A carry prediction circuit unit; Second increasing means for "1" increasing the second partial sum output from the second unit adding means in response to the partial carry signal from the first carry prediction circuit portion; And The second partial sum output from the second unit adding means and the second carry signal and the partial carry signal from the first carry prediction circuit unit are input to predict and output a final carry signal for the first and second data. A second carry prediction circuit unit, And the final sum of the 8-bit adders is output from the first and second increasing means. The method of claim 6, wherein the first carry prediction circuit unit, First logical AND means for receiving and multiplying each bit value of the first subtotal from the first unit adding means; Second logical AND means for receiving and outputting the output signal from the first AND product and the carry input signal; And Logical sum means for receiving the first carry signal from the first unit adding means and the output signal from the second AND product and outputting the result of the partial carry signal. 8-bit adder comprising a. The method of claim 6, wherein the second carry prediction circuit unit, First logical AND means for receiving and multiplying each bit value of the second subtotal from the second unit adding means; Second logical AND means for receiving and outputting the output signal from the first AND product and the partial carry signal; And Logic sum means for receiving and ORing the second carry signal from the second unit addition means and the output signal from the second AND product 8-bit adder comprising a. The method of claim 6, wherein the first increasing means, First exclusive logical sum means for receiving an exclusive logical OR based on the first bit value of the first partial sum and the carry input signal output from the first unit adding means; First AND product for receiving and ORing the first bit value and the carry input signal; Second exclusive OR means for receiving and ORing the second bit value of the first subtotal and the signal from the first AND product output from the first unit adding means; Second logical AND means for receiving and ANDing the first and second bit values and the carry input signal; Third exclusive OR means for receiving and ORing the third bit value of the first subtotal and the signal from the second AND product output from the first unit adding means; Third logical AND means for receiving and logically multiplying the first to third bit values and the carry input signal; And Fourth exclusive OR means for receiving the OR of the fourth bit value of the first subtotal and the signal from the third AND product output from the first unit adding means. 8-bit adder comprising a. The method of claim 6, wherein the second increasing means, First exclusive logical sum means for receiving an exclusive OR of the first bit value of the second partial sum and the partial carry signal output from the second unit adding means; First AND product for receiving and ORing the first bit value and the partial carry signal; Second exclusive OR means which receives an exclusive OR of the second bit value of the second subtotal and the signal from the first AND product output from the second unit adding means; Second logical AND means for receiving and ANDing the first and second bit values and the partial carry signal; Third exclusive OR means for receiving and ORing the third bit value of the second subtotal and the signal from the second AND product output from the second unit adding means; Third logical AND means for receiving and logically multiplying the first to third bit values and the partial carry signal; And Fourth exclusive OR means for receiving and ORing the fourth bit value of the second subtotal and the signal from the third AND product output from the second unit adding means; 8-bit adder comprising a.