KR20000044432A - Method for minimizing error of clock data in exchanger system - Google Patents

Abstract

PURPOSE: A method for minimizing an error of clock data in exchanger system is provided to send the updated clock data every constant period and to offer the clock data in msec unit of minimum clock unit. CONSTITUTION: A method for minimizing an error of clock data in exchanger system is as follows. A SCM(system clock management block)(151) sends a request message of hardware clock data to a NSP(network synchronization processor)(113) through a CCPI(call control processor interface)(140) every established period. The NSP(113) receives the request message of hardware clock data and sends IRQ(interrupt request message) to a first NSCMA(network synchronization clock management)(115). The first NSCMA(115) send the present hardware clock data stored in a memory 1 to the NSP(113). The NSP(113) checks the present hardware clock data received from the NSCMA(115). If the present hardware clock data is void, the NSP(113) re-sends the IRQ to the NSCMA(115) and receives the present hardware clock data again. If the present hardware clock data is valid, the NSP(113) stores the received present hardware clock data to a memory and sends the clock data to the SCM(151). The SCM(151) sends the present hardware clock data stored to a memory when an OS time management unit(160) requests the clock data to the OS time management unit(160). The OS time management unit(160) receives the minimum unit of clock data and utilizes the clock data in the exchanger system.

Description

Minimizing Visual Data Error in Exchange System

The present invention relates to an exchange system, and more particularly, to a method for minimizing an error of visual data operated in an exchange system.

In general, all times of the exchange system must be synchronized with the international standard time, but since there is no direct synchronization equipment in the exchange system, they must be synchronized indirectly. Has Since the time processing of the switching system uses the internal software time, the internal time must be monitored through the external hardware time and the operator time, and the time error must be corrected. In addition, due to the nature of the distributed system, errors can occur between internal times, and error monitoring and correction functions must also be performed. Software for system time management is common to all main processors and is provided by all processors that require visual data from the entire system in operation.

The method for managing the time data is first, the processor for controlling the network device is configured to manage the network device of the network device through the TD-BUS interface the hardware time data provided by the network device at a predetermined period, for example, 80msec period After storing the time data on the memory included in the network synchronization clock maintenance (NSCMA) in the local memory of the processor controlling the network synchronizer device, the time data on the memory is stored at a predetermined period, for example, one second. Read and update in the local memory. The hardware visual data of the network synchronizer is self-operated in the same manner as described above, and upon receiving an update request for the hardware visual data from the system time management block (SCM) of the switching system, the processor controlling the apparatus is controlled. Read the local memory of the device to update the hardware time data. Therefore, the actual current time of the hardware time data is transmitted to the system time management block is delayed by about 2 seconds due to the processing time between the processing routines and the interprocessor communication (IPC) as described above and only the scanning process of the hardware time data. May occur.

In addition, the exchange system multiplexes and operates the predetermined number of the synchronizer clock management boards, for example, four, in order to ensure the stability of system management. In this case, the exchange system set the current time data as software time data, and an error occurred with the normal hardware time data actually being operated.

In addition, the operating system time manager of the switching system ignores the predetermined time unit, for example, the time data of 40 msec unit time or less among the current time data provided by the system time management block, and the time data of the unit time or less is stored. By operating the ignored time data as the current time data, an error occurred with the actual current time data. Therefore, the current time data operated in the exchange system has an error of the actual current time data, causing a problem in the reliability of the exchange system.

Accordingly, an object of the present invention is to provide a method for minimizing an error of visual data operated in an exchange system.

In order to achieve the above object, the present invention provides a predetermined number of network synchronizer clock management boards for managing each piece of hardware time data and hardware time data of the network synchronizer clock management board at predetermined intervals, and receives time data requests. And a system for performing time correction and software time data provided by an operating system time management unit of an exchange system to obtain hardware time data through interfacing with the network device, and the interlock processor for transmitting the stored time data. A method of minimizing time data error in a switching system having a clock time management block, the method comprising: receiving a hardware time data request message transmitted from the system clock time management block, and receiving the hardware time data request message in response to receiving the hardware time data request message; dog Transmitting an interrupt request message to a master synchronizer clock management board of the number of synchronizer clock management boards, and receiving current hardware time data transmitted from the synchronizer clock management board in response to receiving the interrupt request message; And checking whether the received hardware time data is valid data, and transmitting the hardware time data to the system time management block when the hardware time data is valid.

1 is a block diagram showing an internal configuration of an exchange system for performing a function in an embodiment of the present invention.

2 is a flowchart illustrating a process of minimizing visual data error according to an embodiment of the present invention.

3 is a flowchart illustrating a process of minimizing visual data error according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

1 is a block diagram showing an internal configuration of an exchange system for performing a function in an embodiment of the present invention.

The switching system includes an Interconnection Network Subsystem (INS) 100, a Central Control Subsystem (CCS) 150, an Operating System (OS) Time Management Unit 160, and an operator terminal. And a Call Control Processor Interface (CCPI) 140 that performs call processing interfacing between the INS 100 and the CCS 150.

First, the INS 100 includes a Network Synchronization Block (NES) 111 for generating a predetermined number of clocks to match the synchronizers of the respective processors included in the switching system, and the NES 111. A NSCMA (Network Synchronization Processor) 113 is provided with a memory 123 to control the overall operation of the NES 111, and a first NSCMA (Network Synchronization Clock Management) having a memory 1 119. A second NSCMA 117 including a network synchronizer clock management board 115 and a memory 2 121.

Operation and Maintenance Processor (OMP) 153 of the NSP 113 and the CCS 150 is controlled by a Telephony Device Control BUS (TD-BUS) through the CCPI 140. Data transmission / reception using a bus). The OMP 153 controls all operations and maintenance functions of the exchange system, and in particular, the embodiment of the present invention includes a system clock management block (SCM) 151 for time management of the system. The OS time management unit 160 of the exchange system and time data of the exchange system are managed. In addition, an interface such as a command input and a predetermined data output from the operator through an interface with the operator terminal 170 is provided, and a memory 155 is provided to store current time data.

2 is a flowchart illustrating a process of minimizing visual data error according to an embodiment of the present invention.

As shown, the SCM 151 transmits a hardware time data request message to the NSP 113 through the CCPI 140 at set intervals, for example, in 1 minute increments. Receiving the hardware time data request message, the NSP 113 receives a predetermined number of actual hardware time data, for example, four (first NSCMA 115 and second NSCMA 117 and two not shown). NSCMA) The NSCMA transmits an interrupt request message (IRQ) to an NSCMA operating as a master NSCMA, for example, the first NSCMA 115. At this time, the format of the IRQ is the same as Table 1 below.

TABLE 1

ADDRESS DESCRIPTION DATA 03E0H IPC TYPE 0AH 03FFH INTERRUPT REQUEST AAH

Receiving the interrupt request message as shown in Table 1, the first NSCMA 115 transmits current hardware time data stored in the memory 1 119 to the NSP 113. As the current hardware time data, the first NSCMA 115 sets the current hardware time data having a format as shown in [Table 2] on a predetermined area of the memory 1 119 by firmware. For example, the data is updated and stored every second.

TABLE 2

ADDRESS DESCRIPTION DATA 0090H COMPTY NUMBER 04H: TIME DATA REQUEST 0091H CYCLE NUMBER 00H-FFH 0092H MONTH 01-12 0093H DATE 01-31 0094H DAY 01 ~ 07 0095H HOUR 00-23 0096H MINUTE 00-59 0097H SECOND 00-59 0098H MSECOND 00-99 00AFH COMPTY NUMBER 04H

As shown in Table 2, the current hardware time data supplied to the NSP 113 is time data considering up to msec units. The NSP 113 checks the current hardware time data received from the first NSCMA 115 and checks whether the data is valid data. In this case, checking the validity of the data means checking whether the data received from the first NSCMA 115 exists in the valid data area as shown in [Table 2].

If the check result is not valid current hardware time data, the NSP 113 retransmits an IRQ to the first NSCMA 115 to retry receiving the current hardware time data.

If the check result is valid current hardware time data, the NSP 113 stores the received current hardware time data in the memory 123 and transmits the current hardware time data to the SCM 151 through the IPC. The SCM 151 stores the current hardware time data in the memory 155 and then, upon request from the OS time manager 160, that is, when the OS time manager 160 transmits an OS Primitive Call. In response to receiving a primitive call, the current hardware time data stored in the memory 155 is transmitted to the OS time manager 160. Then, the OS time management unit 160 receives the time data considered up to the minimum unit of time data, that is, msec unit, and is used as the time data of the switching system.

Therefore, the process of minimizing the error of visual data as shown in FIG. 2 transmits the updated visual data at regular intervals in an interrupt manner, and also provides visual data up to msec which is the minimum unit of the visual data.

3 is a flowchart illustrating a process of minimizing visual data error according to another embodiment of the present invention.

First, in step 311, the NSP 113 reads a predetermined number of memories included in the NES 111, for example, memories of each of four NSCMA boards, that is, memory 1 119 of the first NSCMA 115, and 2 The memory 2 121 of the NSCMA 117 and the respective memories of the two NSCMAs not shown are read, and the current hardware time data is checked, and the flow proceeds to step 313. In step 313, the NSP 113 checks whether current hardware time data of each NSCMA match. If the current hardware time data does not match, that is, the NSP 113 proceeds to step 315. In step 315, the NSP 113 checks for error factors of the mismatched NSCMA, for example, the second NSCMA 117, and proceeds to step 317. In this case, the error factor may be an access failure or a function failure. In step 317, the NSP 113 initializes the time data of the second NSCMA 117 in which the error occurs, and proceeds to step 319. In step 319, the NSP 113 reads the NSCMA operating as the master NSCMA among the normal NSCMAs excluding the second NSCMA 117, for example, the memory 1 119 of the first NSCMA 115, and displays the current hardware time. After the data is read through the TD-BUS and stored in the memory 123, the process proceeds to step 321. In step 321, the NSP 113 transmits an interrupt request message IRQ to the error-prone second NSCMA 117 in which the time data is initialized, and proceeds to step 323. In step 323, the NSP 113 transmits and returns current hardware time data stored in the memory 123 to the second NSCMA 117 through a TD-BUS. Then, the second NSCMA 117 sets the time data as the current hardware time data transmitted from the first NSCMA 115.

Therefore, the process of minimizing the visual data error as shown in FIG. 3 enables the current hardware time data to be received and set to the current time from the master network synchronizer clock management board in normal operation when an error occurs in the network synchronizer clock management board. As described above, it is possible to minimize the visual data error that may occur by setting the software visual data as in the prior art.

As described above, the embodiments of the present invention have been described with reference to the drawings, for example, but various changes and modifications can be made within the scope allowed by the matter.

As described above, the present invention firstly reads the current hardware time data using the interrupt method, thereby eliminating the scanning delay time in the case of using the conventional scanning method, and eliminates the error of the time data. When the network synchronizer clock management board that operates the data is initialized, the time data is set by the hardware time data of the master network synchronizer clock management board, not the software time data, to match the time data between the network synchronizer clock management boards. The software has the advantage of minimizing the error of visual data by extending the visual data of the visual data to the minimum unit of msec. Therefore, the reliability of the visual data operated in the exchange system is brought.

Claims (5)

Read and update a predetermined number of the Asynchronous Clock Management Board for managing each hardware time data, and the Hardware Time Data of the Asynchronous Clock Management Board at a predetermined period, and transmit the stored time data when receiving the time data request. The time of the exchange system having a system clock time management block for performing time correction and software time data provided by an operating system time management unit of an exchange system to obtain hardware time data through interfacing with the network device. In the method of minimizing data error, Receiving a hardware time data request message transmitted from the system clock time management block; Transmitting an interrupt request message to a master network synchronizer clock management board of the predetermined number of network synchronizer clock management boards in response to receiving the hardware time data request message; Receiving current hardware time data transmitted from the network synchronizer clock management board in response to receiving the interrupt request message; Checking whether the received hardware time data is valid data; And if the hardware time data is valid as a result of the inspection, transmitting the hardware time data to the system time management block. The method of claim 1, Receiving, by the operating system time management unit, a time data request message received by the system time management block storing and receiving the hardware time data; Transmitting the stored hardware time data after receiving the time data request message; And receiving the hardware time data transmitted from the system time management block by the operating system time management unit and setting the time data as valid data to msec units of the hardware time data. How to minimize visual data error of system. The method of claim 1, And retransmitting the interrupt request message to the network synchronizer clock management board when the hardware time data is valid data. The method of claim 1, The step of checking whether the received current hardware time data is valid includes checking whether a data value of the received current hardware time data exists within a data valid range within a current hardware time data format transmitted by the master network synchronizer clock management board. A method of minimizing visual data errors in an exchange system. Read and update a predetermined number of the Asynchronous Clock Management Board for managing each hardware time data, and the Hardware Time Data of the Asynchronous Clock Management Board at a predetermined period, and transmit the stored time data when receiving the time data request. In the method of minimizing the error of visual data of an exchange system having a network synchronizer processor, Inspecting hardware visual data of each of the network synchronizer clock management boards; If the hardware time data of each of the inspected clock controllers does not coincide with each other, inspecting the clocks of the controller clocks and identifying the faulty clock controller boards in error; Initializing hardware time data of the error-synchronized clock management board; Initializing the hardware time data of the faulty network synchronizer clock management board and reading the current hardware time data of the master network synchronizer clock management board in normal operation; Reading current hardware time data of the master network synchronizer clock management board and transmitting an interrupt request message to the errored network synchronizer clock management board; And writing the current hardware time data of the read master network synchronizer clock management board to the errored network synchronizer clock management board after transmitting the interrupt request message.