KR20000042299A - Device and method for segmentation and reassembly of asynchronous transmitting mode cell - Google Patents

Abstract

PURPOSE: A device for Segmentation And Reassembly(SAR) of a asynchronous transmitting mode cell, is provided to store data and control information simultaneously, by putting an input receiving the same data width of cell bus, and the same data size of SRAM as a cell bus in the outside. CONSTITUTION: A device for Segmentation And Reassembly(SAR) of a asynchronous transmitting mode cell, comprises a filter(1), a head checker(2), and a memory(20). The filter(1) detects effective data by receiving data. The head checker(2) decides error of the data detected in the filter(1) and a sort of cell. The memory(20) makes the data to a packet unit by storing the data and deciding a following step. The memory(20) has a control information area(20d), a free Queue(Q) list area(20c), a free Q area(20b), and a temp Q area(20a). The control information area(20d) has addresses which are directly mapping as a visual path/channel identifier and comprise a start address, an end address, and circulating repeat check 32 results. The free Q list area(20c) displays a free Q area currently used and a free Q area remained unused. The free Q area(20b) stores data, finished a circulating repeat check by passing the SAR in real, until a packet is completed. The temp Q area(20a) temporarily stores data being inputted to the SAR.

Description

Sar device and method of asynchronous transfer mode cell

The present invention relates to a method and a method of discarding asynchronous transmission mode cells. More particularly, the present invention relates to a method and a method of discarding asynchronous transmission mode cells suitable for preventing bottlenecks that may occur during disassembly and assembly of an asynchronous transmission mode cell. It is about.

Asynchronous transmission mode is a transmission method of broadband ISDN, and is a transmission and switching technology that is the core of broadband ISDN.

In the asynchronous transmission mode, all information is divided into fixed-length blocks called asynchronous transmission mode cells (hereinafter, referred to as ATM cells) and transmitted sequentially.

The ATM cell has 53 bytes, of which the header is 5 bytes and the information field is 48 bytes. This fixed-length data stream is the unit of multiples and exchanges.

The header contains a virtual channel identifier (VPI), a virtual path identifier (VPI) for identifying the connection to which the cell belongs, and a cell priority indicating whether the cell is discarded during congestion. Priority (CLP), cell information identification (Payload Type: PT) for distinguishing network control information, and error detection and control of header.

The feature of ATM multiplexing is that the multiplexing efficiency can be higher than time division by statistical multiplexing, and the transmission band allocated to individual communication can be freely set.

The characteristic of ATM exchange is that since routine information is stored in a header, each ATM switch can independently relay and exchange cells, and the exchange process can be realized by hardware (chip), thereby increasing the exchange speed.

An asynchronous switching network consists of two levels of networks called virtual condensation and virtual channels.

Such ATM is a technology capable of processing a variety of information at high speed by taking over the high transmission efficiency of packet switching and correcting a decrease in switching delay line usage efficiency, which is a disadvantage of circuit switching.

Such an ATM cell provides a function of disassembling user information into an ATM cell in a sub-layer of an ATM adaptation layer called SAR (Segmentation And Reassembly sublayer) and assembling the received ATM cell into user information. do.

In the conventional ATM cell processing method using such a sar, one control memory is placed in a sar (not shown) and data is used in a separate SRAM or a DRAM of a central processing unit.

However, the conventional Sar is not suitable for a structure in which a lot of data can be concentrated in one place, as in the cell bus method, because it cannot accept data in accordance with internal processing capacity. This is because, when data is concentrated in one place, data other than the capacity that can be processed internally is automatically discarded.

In addition, there was a problem in that an SRAM for storing data and an SRAM for control information were separately provided.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has an input and an external SRAM having the same data size as the cell bus. It is to provide a sar device and a sar method of an asynchronous transmission mode cell that can simultaneously store control information.

According to an aspect of the present invention for achieving the above object, a filter unit for accepting data and detecting valid data, a header check unit for determining whether the data detected by the filter unit error and the type of cells; And a memory unit configured to store the data passed through the filter unit and determine a next task and complete the packet in units of packets.

Preferably, the memory unit has an address mapped directly to a virtual path identifier / virtual channel identifier in an asynchronous transfer mode, and each of the memory addresses includes a start address Start_Addr, a last address End_Addr, and a cyclic redundancy check (CRC). 32) A control information area consisting of 32 results, a free cue list area that represents the area of the prequeue that is currently used, and the area of the prequeue that remains unused, and the data that actually passed the sar It consists of a pre-queue area that is stored until the packet is completed, and a temp queue area that temporarily stores data input to the data.

Preferably, the memory unit further includes a Line Interface Q area for distinguishing and storing a cell when the cell has the same virtual path identifier / virtual channel identifier in various places.

Further, according to another aspect of the present invention for achieving the above object, the step of disassembling the asynchronous transmission mode cell and determining the header of the cell input to the assembling apparatus and storing only valid data in the memory unit, refer to the memory unit Determining a next operation of the data of the cell, storing the data in the memory unit, and transmitting the data of the memory unit to a final terminal in packet units.

According to the present invention as described above, bottlenecks occurring in the sar can be prevented, and the configuration of the sar device can be simplified.

1 is a block diagram of a SAR for disassembling and assembling the asynchronous transmission mode cell of the present invention.

2 is an internal configuration diagram of an SRAM supporting SAR of the asynchronous transmission mode cell of the present invention.

Explanation of symbols for the main parts of the drawings

1 filter unit 2 first header check unit

3: first circular redundancy check unit 4: second header checker

5: second cyclic redundancy check unit 6: FIFO

10: SAR 20: SRAM

30: final terminal

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a sar for disassembling and assembling the asynchronous transmission mode cell of the present invention, and FIG. 2 is an internal configuration diagram of an SRAM supporting sar of the asynchronous transmission mode cell of the present invention.

As shown in FIG. 1, a block diagram of a Sar 10 for disassembling and assembling an asynchronous transmission mode cell of the present invention is shown in FIG. 1, and includes a filter unit 1 for identifying a header among cells input through a cell bus and storing only valid data therein. ), A first header check unit 2 for determining a next operation of the data passed through the filter unit 1, and a first cyclic redundancy check unit for cyclic redundancy checking of the data of the first header check unit 2 ( 3) a final terminal 30 which receives the cyclic redundancy check data and transmits it to the second header check unit 4, and a second header check unit 4 which determines the next operation of the transmitted data. And a second cyclic redundancy check unit 5 for performing cyclic redundancy check of the data for which the next operation is determined, and a FIFO (First In First Out) 6 for outputting the second cyclic redundancy check data by a first-in first-out method. It is composed.

In addition, the sar 10 may include a temp Q (Queue) area 20a, a free queue area 20b, a free cue list area 20c, and a control information area ( 20d) having an SRAM 20 (see FIG. 2).

For reference, the structure of the SRAM as shown in FIG. 2 is a configuration diagram when data width is 64 bits, VPI is 6 bits, and VCI is 9 bits.

At this time, the control information area 20d has an address mapped directly to a virtual path identifier / virtual channel identifier (hereinafter, abbreviated as VPI / VCI), each of which is a start address (Start_Addr) and a last address. (End_Addr) and cyclic redundancy check (CRC) 32 results.

At this time, the start address indicates the address of the pre-queue in which the beginning of the packet is stored, and the last address indicates the address of the pre-queue in which the end of the packet which has passed through Sar 10 is stored so far, and the cyclic redundancy check The 32 result stores the result of the cyclic redundancy check of the incoming packets.

The free cue list area 20c indicates the area of the free cue currently used and the free cue remaining unused.

The pre-queue area 20b is a place where data that has actually passed through Sar 10 and has completed cyclic redundancy check is stored until the packet is completed, where the next data is stored at the next address (Next Addr). Indicates.

The temp queue area 20a is an area in which data input to the sar 10 is temporarily stored.

In addition, a line interface queue (Line Interface Q) region 20e may be optionally formed in the SRAM 20. The line interface queue region 20e may have the same VPI / VCI in several places such as a signaling cell. When a cell comes in, it can store up to eight identical VPI / VCIs.

In the method of disassembling and assembling the asynchronous transmission mode cell of the present invention, when the data is input through the cell bus in the filter unit 1 which always receives the same speed roll data as the cell bus, only the valid data is determined. Save it.

Subsequently, valid data among the data passed through the filter unit 1 is stored in the temp queue area 20a of the SRAM 20. At this time, the data input and output of the temp queue area 20a operate in a first-in first-out (FIFO) manner.

Then, the data of the temp queue area 20a is input to the first header check unit 2 of the sar 10 to determine the next operation of the corresponding data by referring to the control information area 20d of the SRAM 20. do.

At this time, when the data of the first header checker 2 requires cyclic redundancy check, the first cyclic redundancy checker 3 moves to the first cyclic redundancy checker 3 to check the data for errors.

Data for which the cyclic redundancy check has been completed or data for which no cyclic redundancy check is required are stored in the pre-queue area 20c with reference to the information in the control information area 20d. At this time, the stored data is stored according to the type of data and the header value. The stored data are stored in an arbitrary area of the pre-queue area 20c and are connected to each other via a link.

Subsequently, the packet of the data in the prequeuing area 20c is completed, and if there is no error as a result of the cyclic redundancy check, the packet is sent to the final terminal 30. At this time, even when data is sent to the final terminal 30, it continuously moves until the packet is completely delivered in one cell unit of data movement.

At this time, the cyclic redundancy check and reassembly of the data is performed while no data comes from the outer cell bus.

According to the present invention as described above, the throughput of sar 10 is 300 Mbps at 50 MHz of the cell bus.

As described above, the Sar device and Sar method of the asynchronous transmission mode cell of the present invention have the following effects.

First, Sar can handle data at the same speed with the same data width as the cell bus, thus preventing bottlenecks in Sar.

Second, the configuration can be simplified by allowing the storage of control information and data in one SRAM.

Claims (4)

A filter unit which receives data and detects valid data; A header check unit which determines whether an error of the data detected by the filter unit and a cell type; And a memory unit configured to store the data passing through the filter unit and determine a next operation and complete the packet in units of packets. 2. The memory unit of claim 1, wherein an address is directly mapped to a virtual path identifier / virtual channel identifier of an asynchronous transfer mode, and each of the memory unit includes a start address Start_Addr, an end address End_Addr, and cyclic redundancy. CRC 32 A control information area consisting of 32 results, a free cue list area that indicates the area of the currently used free cue and an unused free cue area, and a cyclic redundancy check that actually passes through The apparatus of the asynchronous transmission mode cell, characterized in that the finished data is composed of a pre-queue area is stored until the packet is completed, and the temp queue area is stored temporarily the data input to Sar. The asynchronous memory device of claim 2, wherein the memory unit further comprises a line interface Q area for distinguishing and storing a cell when the cell has the same virtual path identifier / virtual channel identifier in various places. SAR device in transmission mode cell. Determining a header of a cell input to the assembling apparatus and disassembling the asynchronous transmission mode cell, and storing only valid data in the memory unit; Determining a next operation of data of the cell with reference to the memory unit; Storing the data in the memory unit; And transmitting the data of the memory unit in a packet unit to the final terminal.