KR20000041883A - Burst error reducing system in communication system - Google Patents

Abstract

PURPOSE: A burst error reducing system in a communication system is provided to improve an error performance by rearranging and processing a data stream before and after coding the data stream, and to reduce a delay time by progressing a configuration of an interleaver in a parallel structure. CONSTITUTION: A burst error reducing system in a communication system comprises a transmission serial/parallel part(21) divides a data stream into an even bit and an odd bit, and applies the divided even and odd bits to corresponding small-capacity interleavers(22-1,22-2), respectively. Each of the small-capacity interleavers(22-1,22-2) rearranges divided bits transferred from the transmission serial/parallel part(21), and applies the rearranged bit data to a corresponding coder(23-1/23-2). Each of the coders(23-1,23-2) channel codes the rearranged bit data from the corresponding small-capacity interleaver(22-1/22-2), and applies the coded data to a transmission parallel/serial part(24). The transmission parallel/serial part(24) converts coded data applied from each coder(23-1,23-2) into serial data, and a large-capacity interleaver(25) rearranges the serial data from the transmission parallel/serial part(24), and transfers to a channel. A large-capacity deinterleaver(26) deinterleaves the data transferred through the channel, and applies the deinterleaved data to a reception serial/parallel part(27). The reception serial/parallel part(27) divides the deinterleaved data stream into an even bit and an odd bit, and applies the divided even and odd bits to decoders(28-1,28-2). The decoders(28-1,28-2) decode the transferred even and odd bits, respectively, and small-capacity deinterleavers(29-1,29-2) deinterleave the decoded data transferred from corresponding decoders(28-1,28-2). A reception parallel/serial part(30) converts the deinterleaved data transferred from the small-capacity deinterleavers(29-1,29-2) into serial data.

Description

Aggregation Error Reduction System in Communication System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for reducing burst errors in a communication system. In particular, the present invention relates to a parallel cross interleaver having a parallel structure having a low error rate and excellent error rate even with a small memory cell size. A communication error reduction system in a communication system.

In general, in order to provide high quality information satisfactory to users in mobile communication systems and satellite communication systems, the problem of attenuation of multipath fading should be a top priority. The type of attenuation is associated with the arrival of the signal at the receiver for two or more paths with different lengths, and the effect of the attenuation is that the signal arrives with different phases and distorts the received signal. This channel characteristic causes a clustering error in the transmitted data sequence and degrades the performance of the system.

In order to reduce the aggregation error generated by the multipath fading, a block interleaver for converting the aggregation error into a random error is conventionally used.

According to the upband IS-95 standard, the block interleaver has a different size of memory cell for each channel. The size of the corresponding memory cell is based on one frame. The block interleaver used for paging channel and traffic channel is '384' memory cell size. In addition, the memory cell size of the block interleaver is related to the delay time of the system, that is, the delay time due to the device occurring during data transmission and reception is a very important problem in terms of real time communication.

Even in the case of Turbo Code and Concatenated Code, which are significantly improved in the current error performance, the use of the block interleaver is important for the sporadic error of concatenated errors due to multipath fading. This is a reason why an interleaver with a memory cell size large enough cannot be used when considering an increase in computation time.

Then, a general configuration for reducing the aggregation error in the conventional communication system, as shown in Figure 1, the encoder (Encoder) 11, the interleaver 12, the modulator (13), the channel (Channel) 14), a demodulator (15), a deinterleaver (16), and a decoder (Decoder) 17.

Here, the interleaver 12 must be used together with the encoder 11 in performing a role of converting a concatenation error into a scattering error. A communication system using the interleaver 12 is an error of the encoder 11. The larger the correction capability and the larger the memory cell size of the interleaver 12 and the less data string duplication, the better performance is in the additive white Gaussian noise and the multipath fading channel.

In addition, the interleaver 12 and the interleaver having a size of one frame used in the call channel and the call channel in the upband IS-95 standard will be described as follows with respect to the delay time due to the interleaver at the transmitter and the receiver.

First, the interleaver 12 receives the encoded symbol from the encoder 11 and replaces the applied symbols with the modulator 13 so as to be rearranged. Here, the substitution method consists of filling the columns of the M row N column arrays in order, and after the array is filled, the columns are supplied to the modulator 13 one at a time and transmitted on the channel 14. Lose.

On the contrary, the deinterleaver 16 is executed in the receiver, and the symbols are received from the demodulator 15 and deinterleaved to the decoder 17. At this time, the arrangement of the deinterleaver 16 receives the symbols in columns and rearranges them in rows.

In addition, referring to FIG. 2, an example in which the interleaver 12 has four 'M rows' and six 'N columns' will be described with reference to FIG. 2. The interleaver 12 is shown.

2 (b) shows a case in which a concatenation error smaller than 'N' adjacent channel symbol errors, i.e., five errors occur, is deinterleaver 16 divided into at least 'M' symbols at a receiving end. In the output of), all of the series errors are sporadic.

2 (c) shows a case where nine errors occur, 'bN' concatenation errors of 'b> 1' result in at least '[b]' or more symbol errors in the deinterleaver 16. Will result. Here, 'b' is a real number greater than '1' and '[b]' is a positive integer not exceeding 'b' or more.

FIG. 2 (d) shows a case in which a single error occurs at the same position of the 'N' symbol periodically. In the deinterleaver 16, a single aggregation error having a length of 'M' is generated.

Meanwhile, the delay time between the interleaver 12 and the deinterleaver 16 is approximately '2MN' symbol time. To be precise, at least M (N-1) +1 'memory cells are required to fill the array before transmission, so that the same memory cell is required at the receiving end before decoding the data strings that have passed through the demodulator 15. Therefore, the minimum delay time due to the interleaver 12 of the transmitter and the deinterleaver 16 of the receiver is '2MN-2M + 2' symbol time. Here, the delay time caused by the interleaver 12 and the deinterleaver 16 does not consider the delay time generated when the channel is propagated.

In other words, when the interleaver 12 and the deinterleaver 16 use an array of M rows and N columns, the '2MN-2M + 2' symbol time is delayed, which is an important problem in terms of real time communication and before transmitting. In order to fill the array, 'M (N-1) +1' memory cells are required, which in turn has been a constraining factor in system design.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a cross interleaver and a deinterleaver in a parallel structure which can reduce delay time and have excellent error rate characteristics even with a small memory cell size.

In addition, the present invention provides a parallel cross interleaver and an extended Hamming Code in Additive White Gaussian Noise and Rayleigh Fading Channel using a parallel interleaver in parallel. By combining the Extended Golay Code with Quadrature Phase Shift Keying (QPSK) and experimenting on the corresponding error rate characteristics, we can compare and analyze the reduction of delay time and the error rate characteristics.

1 is a block diagram showing a configuration for reducing aggregation error in a general communication system.

FIG. 2 is an exemplary diagram showing an arrangement when the interleaver operates in four rows and six columns in FIG. 1. FIG.

3 is a block diagram illustrating a concatenation error reduction system in a communication system according to an embodiment of the present invention;

4 is a block diagram illustrating a concatenation error reduction system in a communication system according to another embodiment of the present invention.

5 is a view showing the configuration of an overall transmission and reception system using the system of the present invention.

FIG. 6 is a graph of the performance curves in the additive white Gaussian noise channel of FIG. 5; FIG.

FIG. 7 is a graph showing a performance curve in a Rayleigh fading channel to which an extended Hamming code is applied in FIG. 5. FIG.

FIG. 8 is a graph illustrating performance curves in a Rayleigh fading channel when the parallel cross interleaver including the extended Hamming code and the extended Golay code and the Golay code are applied in FIG. 5.

Explanation of symbols on the main parts of the drawings

21: Transmission serial / parallel 22-1 ~ 22-N: Small capacity interleaver

23-1 to 23-N: Encoder 24: Transmit bottle / serializer

25: large capacity interleaver 26: large capacity deinterleaver

27: receiving serial / parallel 28-1 to 28-N: decoder

29-1 ~ 29-N: Small capacity deinterleaver 30: Receive bottle / serializer

The present invention is characterized in that the interleaver / deinterleaver is formed in parallel, and a parallel cross interleaver / deinterleaver for rearranging before and after channel encoding / decoding of data streams is included.

The parallel cross interleaver / deinterleaver may include a transmitting and receiving serial / parallel for separating the data sequence by a singular number of parallel structures; It characterized in that it comprises a transmit and receive parallel / serializer for serial processing the data stream separated from the transmit and receive serial / parallel.

Alternatively, the parallel cross interleaver / deinterleaver may include: a plurality of encoders for encoding interleaved data and applying the interleaved data to the transmitter / serial serializer; And a plurality of decoders for decoding each of the data separated by the receiving serial / parallel.

In addition, the parallel cross interleaver / deinterleaver includes: a plurality of small-capacity interleavers for interleaving the data separated by the transmitting serial / parallel and applying them to the respective encoders; And a plurality of small capacity deinterleavers which deinterleave the data decoded by the decoders and apply the deserialized data to the receiving serial / parallel.

Alternatively, the parallel cross interleaver / deinterleaver may include: a mass interleaver for interleaving data serially processed in the transmission bottle / serializer; And a large capacity deinterleaver for deinterleaving the interleaved data in the large capacity interleaver and applying the interleaved data to the receiving serial / parallel.

The memory cell size of the large capacity interleaver / capacity deinterleaver is related to the memory cell size of the small capacity interleaver / capacity deinterleaver and the coding rate / decoding rate of each encoder / decoder.

According to the present invention, an interleaver (i.e., a block interleaver) having a memory cell having a small sized memory cell is separated by passing data strings through a serial to parallel converter before encoding them with a channel encoder in order to reduce occurrence of concatenation errors. , Channel coding after rearranging in a convolutional interleaver, and passing each of the channel coded columns back to a parallel to serial converter in an interleaver having a large memory cell. Rearrange and send. In addition, in the present invention, the pattern of the receiving end is made to be opposite to the pattern of the corresponding transmitting end. Here, the interleaver having the large memory cell is implemented in association with the code rate of the code used and the size of the interleaver having the small memory cell.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 3 is a block diagram illustrating a concatenation error reduction system in a communication system according to an embodiment of the present invention, Figure 4 is a block diagram showing a concatenation error reduction system in a communication system according to another embodiment of the present invention, 5 is a diagram showing the configuration of an overall transmission / reception system using the system of the present invention. FIG. 6 is a graph showing a performance curve in an additive white Gaussian noise channel in FIG. 5, and FIG. 7 is expanded in FIG. 5. FIG. 8 is a graph illustrating a performance curve in a Rayleigh fading channel to which a Hamming code is applied. FIG. 8 illustrates a case where a parallel cross interleaver including an extended Hamming code and an extended Golay code is applied and only a Golay code is applied. Shows a performance curve in a Rayleigh fading channel.

In the communication system according to an embodiment of the present invention, that is, in the case where the parallel structure is two stages, the aggregation error reduction system includes a transmission serial / parallel 21 and two small interleavers 22, as shown in FIG. -1, 22-2, two encoders 23-1, 23-2, transmission bottle / serializer 24, large capacity interleaver 25, large capacity deinterleaver 26, receiving receiver / Parallel 27, two decoders 28-1 and 28-2, two small-capacity deinterleavers 29-1 and 29-2, and a receiving parallel / serializer 30, Is done. Here, the rearrangement configuration process is made up of various patterns, and the rearrangement configuration pattern is closely related to the channel characteristics, and the parallel structure reduces the computation time, thereby reducing the overall delay time of the system.

The transmitting serial / parallel 21 separates the data sequence into even bits and odd bits and applies each of the separated bits to the small capacity interleavers 22-1 and 22-2, respectively. Let it be.

The small capacity interleavers 22-1 and 22-2 have small memory cells, respectively, and rearrange the separated bits applied from the transmitting serial / parallel 21 to the encoders 23-1 and 23, respectively. To -2) respectively.

The encoders 23-1 and 23-2 can be used as both linear and non-linear codes and can be converted into a form suitable for a system according to a data rate, which is applied from each of the small capacity interleavers 22-1 and 22-2. The rearranged data is channel coded and applied to the transmitter / serializer 24, respectively.

The transmitter / serializer 24 converts the encoded signals applied from the encoders 23-1 and 23-2 into serial data and applies them to the large capacity interleaver 25.

The large capacity interleaver 25 has a large memory cell and rearranges serial data applied from the transmission bottle / serializer 24 and transmits the data to the channel.

The mass deinterleaver 26 deinterleaves data transmitted from the channel and applies the deinterleaver 27 to the receiving serial / parallel 27.

The receiving serial / parallel 27 separates the deinterleaved data sequence applied from the large-capacity deinterleaver 26 into even and odd bits, and divides each of the separated bits into the decoders 28-1 and 28-. 2) respectively.

The decoders 28-1 and 28-2 channel decode the separated bits applied from the receiving serial / parallel 27 to the small capacity deinterleavers 29-1 and 29-2, respectively. .

The small capacity deinterleavers 29-1 and 29-2 deinterleave the decoded data applied from the decoders 28-1 and 28-2, respectively, and apply them to the receiving jar / serializer 30, respectively. do.

The receiving bottle / serializer 30 converts the deinterleaved data applied from the small capacity deinterleavers 29-1 and 29-2 into serial data and outputs the serial data.

Meanwhile, the sizes of the memory cells of the first small interleaver 22-1 and the second small interleaver 22-2 are referred to as 'M ₁ ' and 'M ₂ ', respectively. When the code rates of 2) are referred to as 'R ₁ ' and 'R ₂ ', respectively, and the size of the memory cell of the large capacity interleaver 25 is referred to as 'M`, the size of the corresponding' M` is represented by the following equation. Same as 1.

M` = M ₁ / R ₁ + M ₂ / R ₂

In the case of the first small interleaver 22-1 and the second small interleaver 22-2, the symbol time is 'A (B)' when the length of the matrix is 'A × B'. -1) +1 ', and in the case of the large-capacity interleaver 25, if the length of the matrix is' C × D', the symbol time is' C (D-1) +1 ', so the minimum delay time of all the transceivers If 'Td' the 'Td' is the same as the following equation (2).

Td = 2A (B-1) + 2C (D-1) + 4

In the communication system according to another embodiment of the present invention, that is, in the case where the parallel structure is N stages, as shown in FIG. 4, the aggregation error reduction system includes a transmitting serial / parallel 21 and a plurality of small capacity interleaver 22. -1 to 22-N, a plurality of encoders 23-1 to 23-N, a transmission bottle / serializer 24, a large capacity interleaver 25, a large capacity deinterleaver 26, and a receiving module. / Parallel 27, a plurality of decoders 28-1 to 28-N, a plurality of small-capacity deinterleavers 29-1 to 29-N, and a receiving parallel / serializer 30, Is done. In this case, the transmitting serial / parallel 21 separates the data strings 'N' times in order of input so as to apply each of the separated bits to the small capacity interleavers 22-1 to 22-N, respectively. .

The operation of the aggregation error reduction system in the communication system configured as described above is as follows.

First, the input data stream is separated and applied in order from the first small interleaver 22-1 to the Nth small interleaver 22-N while passing through the transmission serial / parallel 21, for example, {1, 2,3,4,5,6,7,8,9} When the parallel structure has three stages with respect to the input data string, the data input to the first small interleaver 22-1 is {1,4,7}. And the data input to the second small interleaver 22-2 is {2,5,8} and the data input to the third small interleaver 22-3 is {3,6,9}. .

The separation function as described above may be made more random in order to more effectively configure the arrangement.

Accordingly, each of the small-capacity interleavers 22-1 to 22-N has a small memory cell and rearranges the data strings applied from the transmission serial / parallel 21, respectively. The format of receiving input data in the horizontal direction and outputting in the vertical direction is used or the format of receiving input data in the vertical direction and outputting in the horizontal direction.

The output data is input to each of the encoders 23-1 to 23-N, and each of the encoders 23-1 to 23-N is free to determine the corresponding code rate and characteristics, which is the performance of the system to be implemented. Take into consideration the parameters and take them as appropriate.

After passing through each of the encoders 23-1 to 23-N, the channel-coded data string is input from the transmitting bottle / serializer 24 to the large-capacity interleaver 25, and at this time, to the large-capacity interleaver 25. In the case where the parallel structure has two stages, if the memory cell sizes of the small interleavers 22-1 and 22-2 are the same, the inputs are divided by two times the size of the corresponding memory cell size. If the memory cell sizes of 22-1 to 22-3 are the same, the size of each memory cell is increased by three times the size of the corresponding memory cell.

Here, the memory cell size of the large capacity interleaver 25 is related to the size of each of the N small capacity interleavers 22-1 to 22-N and the code rate of each of the encoders 23-1 to 23-N. The sizes of the memory cells of the small-capacity interleavers 22-1 to 22-N are referred to as 'M ₁ ' to 'M _N ', respectively, and the code rates of the respective encoders 23-1 to 23-N are referred to as 'R'. _{When 1} 'to' R _N 'and the size of the memory cell of the large-capacity interleaver 25 are referred to as'M'', the size of the' M '' is expressed by Equation 3 below.

Here, the large-capacity interleaver 25 also receives the input in the vertical direction and outputs it in the horizontal direction or receives the input in the horizontal direction and outputs it in the vertical direction.

On the other hand, the operation of the receiving end is the reverse of the operation of the transmitting end as described above.

Alternatively, in the communication system according to an embodiment of the present invention, the overall transmission / reception system to which the concatenation error reduction system is applied may be represented as shown in FIG. 5, which uses a QPSK modulation scheme and each signal. The points are gray mapped.

Here, the following experiment applies a random bit generator as input data, which can be obtained through a Boolean equation using 32 shift registers and has a period of '2 ^32-1 '.

Further, gives to the data input to the accuracy of the experiment occurred more than 10 ⁸ times, the generator polynomial for the random bit generator is shown in Equation 4 below.

g (x) = x ³² + x ²² + x ² + x + 1

In addition, the channel applied to the experiment is an additive white Gaussian noise and Rayleigh fading channel, and constitutes a parallel cross interleaver having a structure including an extended Hamming code and an extended Golay code, and combines it with the QPSK. Configure the whole system together.

The comparison target is QPSK applying the interleaver with the same memory cell size as the interleaver with the 384 memory cell size used in the upband IS-95. At this time, the same code as the code included in the parallel cross interleaver is used. The error rate is 10 ^-3 , which enables voice communication between users.

Accordingly, when the total memory cell size and the delay time in the entire transmission / reception system of the parallel cross interleaver are calculated, they are shown in Table 1 below. Here, the unit of delay time is symbol time.

Interleaver 2 levels (4 times) 3 levels (6 times) Level 4 (8) size Delay time size Delay time size Delay time 4 × 4 96 140 144 196 192 252 6 × 4 144 208 21 304 288 392 8 × 4 192 276 288 404 384 532 6 × 6 216 328 324 460 432 604 8 × 6 288 436 432 624 8 × 8 384 594

Table 1 is a result calculated on the assumption that the code rates of the encoders are '1/2' in the experimental system and that the small interleavers have the same size. In this case, the size of the large interleaver is 2 stages, 3 In the case of stages and 4 stages, the sizes are 4, 6 and 8 times.

The memory cell size of a conventional block interleaver is 384, which is a unit of one frame, and the delay time when a single block interleaver having the same memory cell size is used is 722 symbol times. However, when compared with the delay time of Table 1, the delay time is reduced by about 54.6 (%) when the parallel cross interleaver having the size of 216 memory cells of the two-stage structure is tested, and the 288 of the two-stage structure is reduced. The delay time is reduced by about 44 (%) when using the parallel cross interleaver with the memory cell size, and the delay time is about 17.7 (% when using the parallel cross interleaver with the same memory cell size. In the case of using a parallel cross interleaver with the same memory cell size having a four-stage structure, the delay time is reduced by about 26.3 (%).

FIG. 6 is a graph showing performance curves in an additive white Gaussian noise channel. The memory cell size of the parallel cross-interleaver applied in this case varies depending on the code used, and when applied with an extended Hamming code, 216. If the memory cell size is used and the extended Golay code is used, the memory cell size is 288.

Here, as a result of experimenting with the additive white Gaussian noise, a QPSK error rate characteristic curve using a Hamming code extended at an error rate of ^10-3 and a parallel cross interleaver with a size of 216 memory cells ((c) curve shown in FIG. 6) Shows an improvement of about 3 (dB) over the uncoded QPSK error rate characteristic curve ((a) curve shown in FIG. 6), and the QPSK error rate with an extended Golay code and parallel cross interleaver of 288 memory cell sizes The characteristic curve (curve (d) shown in FIG. 6) shows a performance improvement of about 4 (dB) over the uncoded QPSK error rate characteristic curve. And, the curve (b) shown in FIG. 6 shows a QPSK error rate characteristic curve to which only a Golay code is applied.

In addition, the experimental results show that the QPSK error rate curve using the extended Hamming code, the extended Golay code, and the single block interleaver with the size of 384 memory cells shows the same performance as that of the parallel cross interleaver.

FIG. 7 is a graph showing performance curves according to memory cell sizes when an extended Hamming code is applied in a Rayleigh fading channel, and 216 memory cells from the curves of (b), (c) and (d) shown in FIG. It can be seen that the parallel parallel interleaver of the size outperforms the single block interleaver of 384 memory cell size.

Here, the experimental performance analysis results show that the QPSK error rate characteristic curve ((d) curve shown in FIG. 7) with the Hamming code extended at the error rate 10 ^-3 and the parallel cross interleaver of 216 memory cell size is a single 384 memory cell size. It shows about 2 (dB) improvement over the QPSK error rate characteristic curve with block interleaver ((c) curve shown in Fig. 7), and the QPSK error rate characteristic with parallel cross interleaver with extended Hamming code and 384 memory cell size The curve (curve (e) shown in Figure 7) shows a performance improvement of about 3 (dB) over the QPSK error rate characteristic curve with a single block interleaver of 384 memory cell size. In addition, the curve (a) shown in FIG. 7 represents an uncoded QPSK error rate characteristic curve, and the curve of (b) shown in FIG. 7 represents an extended Hamming code and a parallel cross interleaver having a size of 196 memory cells. The applied QPSK error rate characteristic curve is shown.

FIG. 8 is a graph illustrating a QPSK performance curve when a parallel cross interleaver including an extended Hamming code and an extended Golay code is applied to Rayleigh fading channel and only an extended Golay code is applied.

Here, the experimental performance analysis results show that the QPSK error rate characteristic curve ((c) curve shown in FIG. 8) with an extended Hamming code at error rate 10 ^-3 and a parallel cross interleaver with 216 memory cell size is shown as an extended Hamming code and 384. A performance improvement of about 2 (dB) over the QPSK error rate characteristic curve (curve (b) shown in FIG. 8) applying a single block interleaver of memory cell size, and the uncoded QPSK error rate characteristic curve (a shown in FIG. 8) (Q curve) characteristic curve ((f) curve shown in FIG. 8) with an extended Golay code and a parallel cross interleaver of 288 memory cells. A performance improvement of about 2 (dB) over the QPSK error rate characteristic curve ((e) curve shown in FIG. 8) with a Golay code and a single block interleaver of 384 memory cell size, and about 12 (12%) over the uncoded QPSK error rate characteristic curve. (dB) performance improvement It looks.

And, the curve of (d) shown in FIG. 8 shows a QPSK error rate characteristic curve to which only the extended Golay code is applied.

As described above, according to the present invention, the structure of the interleaver (for example, the block interleaver, the convolutional interleaver, etc.) can be advanced in a parallel structure to reduce the delay time, and the data sequence is rearranged and processed before and after the data channel encoding. Therefore, it can have excellent error rate characteristics.

Claims (4)

And a parallel cross interleaver / deinterleaver for forming interleaver / deinterleaver in parallel and rearranging before and after channel encoding / decoding of data streams. The method of claim 1, The parallel cross interleaver / deinterleaver includes: a transmitting and receiving serial / parallel for separating the data sequence by the singular number of the parallel structure; A transmit and receive parallel / serializer for serially processing data streams separated from the transmit and receive serial / parallel; A plurality of encoders for encoding interleaved data and applying the encoded interleaved data to the transmitter / serial serializer; And a plurality of decoders for decoding the data separated by the receiving serial / parallel, respectively. The method of claim 2, The parallel cross interleaver / deinterleaver includes: a plurality of small-capacity interleavers for interleaving data separated by the transmitting serial / parallel and applying them to the encoders; A plurality of small capacity deinterleavers which deinterleave the data decoded by the decoders and apply the deserialized data to the receiving serial / parallel; A large interleaver for interleaving data serially processed in the transmission bottle / serializer; And a large capacity deinterleaver for deinterleaving the interleaved data in the large capacity interleaver and applying the interleaved data to the receiving serial / parallel. The method according to claim 2 or 3, The memory cell size of the large interleaver / capacity deinterleaver is related to the memory cell size of the small interleaver / capacity deinterleaver and the coding rate / decoding rate of each encoder / decoder. .