KR20000038606A - Decoder for compensating automatically movement of direct current reference line in high-speed ethernet - Google Patents

Abstract

PURPOSE: A decoder for compensating automatically a movement of a direct current reference line in a high-speed ethernet is provided to compensate automatically a movement of a direct current reference line. CONSTITUTION: A decoder for compensating automatically a movement of a direct current reference line in a high-speed ethernet relates to a data transmission and reception portion of a 100Base-TX physical layer in a high-speed ethernet. Particularly, the decoder is to compensate automatically a movement of a direct current reference line generated when performing the data transmission and reception adapted to IEEE802.3. The decoder comprises a high pass filter(100), a current classification portion(200), an input comparison portion(300), a feedback voltage/current converter(400), a low pass filter(500), a voltage/current converter(600), and an output comparison portion(700).

Description

Fast Ethernet DC Baseline Shift Automatic Compensation Decoder

The present invention relates to a data transceiver of a Fast Ethernet 100Base-TX physical layer. In particular, the present invention relates to the movement of a DC reference line generated when there is no data transition in transmitting and receiving data in accordance with the Institute of Electrical and Electronic Engineers (IEEE) 802.3 communication protocol. It relates to a decoder that automatically corrects.

The IEEE 802.3 protocol in the Ethernet communication method is also known as carrier sense multiple access with collision detection (CSMA / CD).

In the CSMA / CD scheme, when a frame transmitted by terminals collides by sharing a transmission medium, a function of detecting a collision with a carrier and a function of retransmitting are implemented in a physical layer and a data link layer.

Next, a data transmission / reception system of a general Fast Ethernet physical layer will be described with reference to FIG. 1.

1 is a block diagram of a data transceiver of a general Fast Ethernet physical layer.

Referring to FIG. 1, in the transmission path, when a digital signal passing through a 4B / 5B encoder is transmitted through a scrambler in the form of a multi-level transmission 3 (MLT3) code, the transmitter passes through a transmission line through a transformer. After that, a signal comes in to the receiver of the other LAN (Local Area Network) card. The signal is compensated for the frequency attenuated on the transmission line as it passes through an equalizer, and the decoder converts the MLT3 code into a Non Return to Zero Inverted (NRZI) code and then receives a receive phase locked loop. In the loop, a clock of a certain period is sent out, and a data of the other party is transmitted to a medium access control (MAC) unit through a 5B / 4B decoder through a descrambler.

A receiver decoder in a conventional data transceiver system of a fast Ethernet physical layer is described below with reference to FIG. 2.

2 is a block diagram of a receiver decoder block in a data transceiver system of a conventional fast Ethernet physical layer.

As shown in FIG. 2, the conventional data receiver decoder includes a bias generator 15, a current classifier 25, and a comparator 35.

The bias generator 15 generates a reference voltage and a reference current, the current classifier 25 moves the direct current level to be comparable in the comparator with the intermediate level of the signal to eliminate noise generated in the line, and the comparator 35 Compares the reference voltage of the bias generator 15 with the direct current level moved by the current classifier 25.

On the other hand, the 10MHz Ethernet transmission transmits data in the form of Manchester code, so that the clock information is included in the bit string, so it is easy to recover data from the receive path and extract the receive clock.

On the other hand, 100MHz Ethernet transmissions transmit data in MLT3 code rather than Manchester code and do not include clock information in the bitstream. In addition, since the transmission is not only severely attenuated in the transmission line because of the high speed transmission, the DC reference line is moved by OCL (Open Circuit Inductance), which is an inherent property of the transformer.

The data after the movement of the DC reference line has a certain margin for noise when using the conventional decoder at the time of restoration, but it cannot compensate for the movement of the DC reference line that occurs when there is no data transition. Not only is this unstable jitter worsening, there is a problem that data loss may occur.

The present invention is to solve such a problem, even if the data transition does not occur for a long time, even if the DC reference line movement occurs using a current classifier and comparator and a simple current mode first-order high-pass filter and low-pass filter to compensate for the DC reference line movement, These values are compared to facilitate the extraction of data in the form of low noise NRZI codes.

1 is a block diagram of a data transceiver of a Fast Ethernet physical layer.

2 is a block diagram of a receiver decoder block in a data transceiver system of a conventional fast Ethernet physical layer.

3 is a block diagram of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer proposed in the present invention.

4 is an internal circuit diagram of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer proposed in the present invention.

FIG. 5 is an input / output waveform diagram at each stage of the DC reference line moving automatic compensation decoder in the data transceiver system of the fast Ethernet physical layer proposed by the present invention.

In order to achieve this problem, the data transmission / reception system of the fast Ethernet physical layer proposed by the present invention is a 4B / 5B encoder, a link monitor, a far end fault generator, a scrambler selector, and a transmitter. A base and equalizer unit, a decoder unit, a phase locked loop unit, a descrambler selector unit, a far end fault detector unit, and a 5B / 4B decoder unit are included.

The 4B / 5B encoder section consists of a 4B / 5B encoder and a transmission shift register. The 4B / 5B encoder section receives the input data, converts the 4-bit data into 5 bits, and codes the non-return to zero inverted (NRZI) format. This parallel data is converted into serial data via a transmission shift register.

The link monitor receives the on / off state of the signal from the link layer and transmits the link state to the transceiver.

The far-end failure generation unit transmits the output data of the 4B / 5B encoder unit to the scrambler selection unit according to the on / off state signal of the link monitor unit.

The scrambler selector consists of an NRZI converter and a scrambler, selects one of the NRZI converter and a scrambler according to the type of transmission line, receives the NRZ type data from the far-end failure generator, and converts the NRZI type data It is output to the cable transmission line or encoded and transmitted to the transmitter.

The transmitter unit is composed of a transmitter and a transmission phase synchronization loop, receives data from a scrambler selector, outputs a transmission line through a transformer in the form of a multi-level transmission 3 (MLT3) code, and 25Mhz in a transmission phase synchronization loop. The clock of the crystal oscillator is applied and divided to supply the clock to the upper layer.

The equalizer part is composed of a pre-amp and an equalizer. The data received through the transmission line is amplified by being applied to the preamplifier through the transformer and according to the frequency attenuated in the transmission line through the equalizer. The level is rewarded.

The decoder receives MLT3 code data from the equalizer and converts the data into an NRZI code.

The reception phase lock loop unit receives the transmission clock from the decoder unit and divides the transmission clock to supply the reception clock.

The descrambler selector consists of an NRZ converter and a descrambler, and selects one of the NRZ converter and the descrambler according to the type of the transmission line, and receives the NRZI type data from the optical cable transmission line and converts it into NRZ type data. After outputting to the far-end failure detection unit or receiving the NRZI type data from the decoder unit and receiving the clock from the receiving phase lock loop unit, the inverse transform is performed on the signal modulated by the scrambler of the transmission path.

The far-end failure detection unit receives the received data from the NRZ converter and the descrambler and checks whether the link with the other terminal is disconnected and outputs the result to the link monitor unit.

The 5B / 4B decoder consists of a 5B / 4B decoder and a receive shift register. The receive shift register receives serial received data from a descrambler and converts the received data into parallel data, and then groups the received shift register into 5 bits through the 5B / 4B decoder. The parallel data is converted into 4 bits and output to the MAC (Medium Access Control) of the link layer.

An embodiment of the data transceiver of the fast Ethernet physical layer of the present invention configured as described above will be described with reference to FIG. 1.

1 is a block diagram of a data transceiver of a general Fast Ethernet physical layer.

First, in the transmission path, the 4B / 5B encoder unit 10 receives input data from a link layer that is higher than the physical layer, divides four data into one group in the 4B / 5B encoder 11, and converts the data into 5 bits. It is coded in the Non Return to Zero Inverted (NRZI) code format. Here, the NRZI code format is a form in which polarity is inverted only when data is high, and a NRZ (Non Return to) is used for mapping a high and low digital binary code to the positive and negative sides of a modulated wave. Zero) Unlike the code format, it is advantageous for the magnetic recording of the differential detection type. The transmission shift register 12 receives parallel data from the 4B / 5B encoder 11 and converts the serial data into serial data.

The link monitor 20 receives an on / off state of a signal from the link layer, that is, whether a transmission line is shorted, and transmits a link state to the transceiver 50.

The far-end failure generator 30 checks whether the link with the counterpart terminal is disconnected according to the on / off status signal of the link monitor 20, and transmits the result to the counterpart terminal. The output data of the data is transmitted to the scrambler selector 40.

The scrambler selector 40 is composed of an NRZI converter 41 and a scrambler 42. If one of the NRZI converter 41 and the scrambler 42 is selected according to the type of transmission line, the scrambler selector 40 ) Is selected, the NRZ type data is received from the far-end failure generation unit 30 and converted into NRZI type data and then output to the optical cable transmission line, and when the scrambler 42 is selected, the amplitude of the data and the The jitter (Jitter) having an unstable phase is suppressed, and the signal is transmitted to the transmitter unit 50 by maintaining and transmitting a uniform transmission characteristic.

The transmitter unit 50 is composed of a transmitter 51 and a transmission phase lock loop 52. The transmitter unit 50 receives data from the scrambler selector 40 and generates a transformer in the form of a multi-level transmission 3 (MLT3) code. The output signal is transmitted to the transmission line, and the clock of the 25Mhz crystal oscillator is applied in the transmission phase synchronization loop 52, and divided to supply the clock to the upper layer. Here, the MLT3 code form is a method of shape-converting the data of the NRZI code into three levels. The MLT3 code form is high when the NRZI code is initially high, low when the low code is low, and high again. high, -1, and low again.

Next, in the reception path, the equalizer unit 60 amplifies the data received through the transmission line through the transformer to the preamplifier 61 and compensates for the deformation due to the propagation time deviation through the equalizer 62. The level according to the attenuated frequency in the transmission line is compensated.

The decoder 70 receives current mode data in the form of MLT3 code compensated for attenuation by the equalizer 60, and converts the DC reference line movement generated when there is no data transition into a compensated NRZI code form.

The reception phase lock loop unit 80 uses a phase lock loop to adapt to minute changes caused by temperature and voltage fluctuations of the transmission clock. The reception phase lock loop 80 receives and extracts the transmission clock included in the data from the decoder 70 and then divides it. Supply the receive clock.

The descrambler selector selects one of the descrambler 86 and the NRZ converter 87 according to the type of transmission line, and if the descrambler 86 is selected, the NRZI type data from the decoder unit 70 is selected. When the NRZ converter 87 is selected, the inverse conversion is performed by applying the same shape to the signal modulated by the scrambler 42 of the transmission path by receiving the reception clock from the reception phase lock loop unit 80. After receiving the NRZI data from the optical cable transmission line, the NRZ data is converted into NRZ data and output to the far-end failure detection unit 90.

The far-end failure detection unit 90 receives the data received from the descrambler 86 and the NRZ converter 87 and receives a signal for checking whether a link is disconnected with the counterpart terminal, and transmits the result to the link monitor unit 20. Output

The 5B / 4B decoder unit 95 receives serial reception data from the descrambler 86 in the reception shift register 96 and converts the serial reception data into parallel data, and then receives the reception shift register 96 through the 5B / 4B decoder 97. Converts parallel data grouped into 5 bits into 4 bits and outputs it to the medium access control (MAC) of the link layer. Here, the MAC is a link layer element that performs CSMA / CD operation according to carrier and collision information reported in the physical layer.

Next, a decoder unit of a data transceiver unit of a fast Ethernet physical layer according to the present invention will be described.

The receiver decoder of the data transceiver system of the fast Ethernet physical layer proposed by the present invention includes a high pass filter, a current classifier, an input comparator, a feedback voltage / current converter, a low pass filter, a voltage / current converter, and an output comparator. .

The high pass filter receives a current mode data input in the form of MLT3 code compensated for attenuation from the equalizer section and passes only the high range portion of the frequency.

The current classifier receives a signal passing through the high pass filter and moves the intermediate level and the DC level so that the input comparator can be compared.

The input comparison unit receives the data moved by the current classifying unit, stores the previous value, and compares the levels.

The feedback voltage / current converter feeds back the output of the input comparator to maintain the accuracy and characteristics of the processing result.

The low pass filter passes only the low pass portion of the current mode data converted by the feedback voltage / current conversion unit, and adds the output of the high pass filter to the current classifying unit.

The voltage / current converter receives the voltage output of the input comparator and converts the current mode data.

The output comparator receives the non-inverted output and the inverted output of the current mode data converted by the voltage / current converter, compares the current levels of the two signals and outputs them in the form of NRZI codes.

An embodiment of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer configured as described above will now be described with reference to FIG. 3.

3 is a block diagram of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer proposed in the present invention.

The high pass filter 100 is a primary current mode filter having a frequency of 2 MHz and a gain of 0.5, that is, -3 dB (decibel) point, and is applied with a current mode data input in the form of an MLT3 code to remove unnecessary frequency components and Pass only the highs.

The current classifying unit 200 receives the signal passing through the high pass filter 100, and removes the noise generated from the transmission line. Move it so that it can be compared.

The input comparator 300 receives the data moved by the current classifier 200, and when the input having a little noise in the same amount as the reference level is input, the output repeats high and low. To prevent this, remember the previous value and compare the levels.

The feedback voltage / current converter 400 feeds back the output of the input comparator 300 to correct the movement of the DC reference line caused by the inherent characteristics of the transformer when no data transition occurs for a long time. Convert data in voltage mode to current mode.

The low pass filter 500 removes unnecessary frequency components of the current mode data converted by the feedback voltage / current converting unit 400 and passes only the low pass portion of the required frequency, and adds the current classifying unit to the output of the high pass filter 100. Enter (200).

The voltage / current converter 600 receives the voltage output of the input comparator 300 and converts the current / mode data into a current mode data in order to prevent a problem caused by the frequency characteristic of the OP AMP in the high frequency band.

The output comparator 700 receives the non-inverted output and the inverted output of the current mode data converted by the voltage / current converter 600, compares the current levels of the two signals, and outputs the NRZI codes.

Next, an internal configuration of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer according to the present invention will be described in detail with reference to FIG. 4.

4 is an internal circuit diagram of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer proposed in the present invention.

The current mode data inputs Inp and Inn in the form of MLT3 codes are applied to the input of the high pass filter 100 in the form of V1 and V2, respectively, and are output in the form of V3 and V4, respectively.

The current classifying unit 200 receives current mode data inputs Inp and Inn from the high pass filter 100 in the form of V5 and V6, respectively, to form current power supplies Iop2, Iop3, Ion2, and Ion3.

The input comparator 300 includes resistors R1, R2, R3, and R4, current power supplies IR1 and IR2, and comparators COMP1 and COMP2. The power supply voltage VDD is applied in parallel to the resistors R1 and R2, and the current power source IR1 is connected to the other side of the resistor R1, and the contact thereof is connected to the current power source Iop2 of the current classifying unit 200. The current power source Ion2 of the current classifying unit 200 is connected to the other side of the resistor R2. The contact of the resistor R1 and the current power supply IR1 is applied in the form of Inp1 to the (+) input terminal of the comparator COMP1, and the other side of the resistor R2 is applied in the form of Inn1 to the (-) input terminal. .

In addition, the power supply voltage VDD is applied in parallel to the resistors R3 and R4, and the current power source IR2 is connected to the other side of the resistor R3, and the contact thereof is the current power source Iop3 of the current classifying unit 200. ) And a current power source Ion3 of the current classifying unit 200 is connected to the other side of the resistor R4. The contact of the resistor R3 and the current power supply IR2 is applied to the (+) input terminal of the comparator COMP2 in the form of Inp2, and the other side of the resistor R4 is applied to the (-) input terminal in the form of Inn2. .

The feedback voltage / current converter 400 includes comparators COMP3 and COMP4 and current power supplies I11 and I12, and the comparator COMP1 of the input comparator 300 is connected to the positive input terminal of the comparator COMP3. The output of is applied, and the inverted output of the comparator COMP1 of the input comparator 300 is applied to the negative input terminal. In addition, the output of the comparator COMP2 of the input comparator 300 is applied to the (+) input terminal of the comparator COMP4, and the inverted output of the comparator COMP2 of the input comparator 300 is applied to the (-) input terminal. Is applied. The output of the comparator COMP3 and the inverting output of the comparator COMP4 are summed and output to the current power supply I12, and the inverting output of the comparator COMP3 and the output of the comparator COMP4 are summed and output to the current power source I11. .

The low pass filter 500 receives the output currents I11 and I12 from the feedback voltage / current converter 400 and is output in the form of V13 and 414 to respectively output V3 and V4 of the high pass filter 100. The sum is applied to the inputs V5 and V6 of the current classifying unit 200.

The voltage / current converter 600 is composed of comparators COMP5 and COMP6, and the output of the comparator COMP1 of the input comparator 300 is applied to the positive input terminal t1 of the comparator COMP5. The inverting output of the comparator COMP1 of the input comparator 300 is applied to the negative input terminal t2. In addition, the output of the comparator COMP2 of the input comparator 300 is applied to the (+) input terminal t3 of the comparator COMP6, and the comparator of the input comparator 300 is applied to the (−) input terminal t4. The inverting output of (COMP2) is applied.

The output comparator 700 includes resistors R5 and R6, current power source IR3 and comparator COMP7. The power supply voltage VDD is applied in parallel to the resistors R5 and R6, and the other side of the resistor R5 is connected to the sum of the inverting output Ion1 of the comparator COMP5 and the output Iop2 of the comparator COMP6. The other side of the resistor R6 is connected to the sum of the output Iop1 of the comparator COMP5 and the inverting output Ion2 of the comparator COMP6. In addition, the current power source IR3 is connected to the other side of the resistor R6, and the positive input terminal of the comparator COMP7 has an output Iop1 and a comparator of the comparator COMP5 of the voltage / current converter 600. The sum of the inverted output Ion2 and the current power supply IR3 of COMP6 is applied, and the sum of the inverted output Ion1 of the comparator COMP5 and the output Iop2 of the comparator COMP6 is applied to the negative input terminal. Finally, the output NRZI is output.

Next, an operation of the DC reference line moving automatic compensation decoder in the data transceiver system of the fast Ethernet physical layer according to the present invention will be described in detail with reference to FIGS. 4 and 5.

4 is an internal circuit diagram of a DC reference line moving automatic compensation decoder in a data transceiver system of a fast Ethernet physical layer proposed in the present invention.

FIG. 5 is an input / output waveform diagram at each stage of the DC reference line moving automatic compensation decoder in the data transceiver system of the fast Ethernet physical layer proposed by the present invention.

As shown in FIG. 5A, when the input currents In and Inn are applied to the high pass filter 100, the output waveform is as shown in FIG. 5B, and the corrected input current is shown in FIG. 5C. It is applied to the current classifying unit 200 in the form of.

The input voltages VInn1 and VInp1 applied to the (+) input terminal and the (-) input terminal of the comparator COMP1 of the input comparator 300 are the same as in Equations 1 and 2, and the waveform of FIG. same as d).

VInn1 = VDD- (R2 * (IO + Inp))

VInp1 = VDD- (R1 * (IO + Inn + IR1))

Here, IO is a basic bias current generated by the current classifying unit 200.

First, the output Vt1 of the comparator COMP1 of the input comparator 300 is high in a section (1) in which the input current Inp is greater than the sum of the input current Inn and the spare current ir. ), And the inverting output Vt2 becomes low.

In addition, the input voltages VInn2 and VInp2 applied to the (+) input terminal and the (−) input terminal of the comparator COMP2 of the input comparator 300 are the same as in Equations 3 and 4, and the waveform is shown in FIG. 5. Is the same as (e).

VInn2 = VDD- (R4 * (IO + Inn))

VInp2 = VDD- (R3 * (IO + Inn + IR2))

Here, IO is a basic bias current generated by the current classifying unit 200.

The output Vt3 of the comparator COMP2 of the input comparator 300 becomes low and the inverted output Vt4 becomes high.

In addition, the feedback voltage / current converter 400 has an output Vt7 of the comparator COMP3 high and an inverted output Vt8 is low, and an output Vt9 of the comparator COMP4. ) Becomes low and the inverting output Vt10 becomes high.

Accordingly, the waveforms of the power supply voltages I11 and I12 applied to the low pass filter 500 are as shown in FIG. 5 (f), and the waveforms passing through the low pass filter 500 are as shown in FIG. 5 (g).

Meanwhile, the waveform (b) passing through the high pass filter 100 and the waveform (g) passing through the low pass filter 500 are combined and applied to the current classifying unit 200 in the form of FIG. 5C. do.

Similarly, the output Vt1 of the comparator COMP1 of the input comparator 300 is high to the (+) input terminal of the comparator COMP5 of the voltage / current converter 600 via the input comparator 300. Is applied and the output of the comparator COMP5 of the voltage / current converter 600 is applied when a low that is an output Vt2 of the comparator COMP1 of the input comparator 300 is applied to the negative input terminal. Iop1 becomes high and inverted output Ion1 becomes low.

In addition, a low, which is an output Vt3 of the comparator COMP2 of the input comparator 300, is applied to the (+) input terminal of the comparator COMP6 of the voltage / current converter 600. When a high, which is an output Vt4 of the comparator COMP2 of the input comparator 300, is applied to the input terminal, the output Iop2 of the comparator COMP6 of the voltage / current converter 600 is low. ), And the inversion output Ion2 becomes high.

Accordingly, the voltage Vt5 applied to the (+) input terminal of the comparator COMP7 of the output comparator 700 and the voltage Vt6 applied to the (−) input terminal are the same as Equations 5 and 6, , Waveforms are the same as in FIG.

Vt5 = VDD-R6 * (IR3 + Inp1 + Ion2)

Vt6 = VDD-R5 * (Ion1 + Iop2)

Therefore, the final output NRZI in the section (1) in which the input current Inp of the decoder section is larger than the sum of the input current Inn and the spare current ir becomes high.

Next, in the section (2) where the input current Inp is greater than the difference between the input current Inn and the reserve current ir, and less than the sum of the input current Inn and the reserve current ir, the input comparison unit The output Vt1 of the comparator COMP1 of 300 becomes low, and the inverting output Vt2 becomes high.

In addition, waveforms of the input voltages VInn2 and VInp2 applied to the (+) input terminal and the (−) input terminal of the comparator COMP2 of the input comparator 300 are as shown in FIG. 5E.

The output Vt3 of the comparator COMP2 of the input comparator 300 becomes low and the inverted output Vt4 becomes high.

In addition, the feedback voltage / current converter 400 has an output Vt7 of the comparator COMP3 low, an inverted output Vt8 is high, and an output Vt9 of the comparator COMP4. ) Becomes low and the inverting output Vt10 becomes high.

Accordingly, the waveforms of the power supply voltages I11 and I12 applied to the low pass filter 500 are as shown in FIG. 5 (f), and the waveforms passing through the low pass filter 500 are as shown in FIG. 5 (g).

Meanwhile, the waveform (b) passing through the high pass filter 100 and the waveform (g) passing through the low pass filter 500 are combined and applied to the current classifying unit 200 in the form of FIG. 5C. do.

Similarly, the output Vt1 of the comparator COMP1 of the input comparator 300 is low at the (+) input terminal of the comparator COMP5 of the voltage / current converter 600 through the input comparator 300. Is applied, and when a high, which is an output Vt2 of the comparator COMP1 of the input comparator 300, is applied to the negative input terminal, the output of the comparator COMP5 of the voltage / current converter 600 is applied. (Iop1) goes low, and the inverted output (Ion1) goes high.

In addition, a low, which is an output Vt3 of the comparator COMP2 of the input comparator 300, is applied to the (+) input terminal of the comparator COMP6 of the voltage / current converter 600. When a high, which is an output Vt4 of the comparator COMP2 of the input comparator 300, is applied to the input terminal, the output Iop2 of the comparator COMP6 of the voltage / current converter 600 is low. ), And the inversion output Ion2 becomes high.

Accordingly, the waveforms of the voltage Vt5 applied to the (+) input terminal of the comparator COMP7 of the output comparator 700 and the voltage Vt6 applied to the (−) input terminal are the same as in FIG. .

Therefore, the input current Inp of the decoder section is larger than the difference between the input current Inn and the marginal current ir, and is the last in the section (2) smaller than the sum of the input current Inn and the marginal current ir. The output NRZI goes low.

Next, the output Vt1 of the comparator COMP1 of the input comparator 300 is low in a section (3) where the input current Inn is greater than the sum of the input current Inp and the spare current ir. low, and the inverting output Vt2 becomes high.

In addition, waveforms of the input voltages VInn2 and VInp2 applied to the (+) input terminal and the (−) input terminal of the comparator COMP2 of the input comparator 300 are as shown in FIG. 5E.

The output Vt3 of the comparator COMP2 of the input comparator 300 becomes high and the inverted output Vt4 becomes low.

In addition, the feedback voltage / current converter 400 has an output Vt7 of the comparator COMP3 low, an inverted output Vt8 is high, and an output Vt9 of the comparator COMP4. ) Becomes low and the inverting output Vt10 becomes high.

Accordingly, the waveforms of the power supply voltages I11 and I12 applied to the low pass filter 500 are as shown in FIG. 5 (f), and the waveforms passing through the low pass filter 500 are as shown in FIG. 5 (g).

Meanwhile, the waveform (b) passing through the high pass filter 100 and the waveform (g) passing through the low pass filter 500 are combined and applied to the current classifying unit 200 in the form of FIG. 5C. do.

Similarly, the output Vt1 of the comparator COMP1 of the input comparator 300 is low at the (+) input terminal of the comparator COMP5 of the voltage / current converter 600 through the input comparator 300. Is applied, and when a high, which is an output Vt2 of the comparator COMP1 of the input comparator 300, is applied to the negative input terminal, the output of the comparator COMP5 of the voltage / current converter 600 is applied. (Iop1) goes low, and the inverted output (Ion1) goes high.

In addition, a high, which is an output Vt3 of the comparator COMP2 of the input comparator 300, is applied to the (+) input terminal of the comparator COMP6 of the voltage / current converter 600, and (−) When a low, which is an output Vt4 of the comparator COMP2 of the input comparator 300, is applied to the input terminal, the output Iop2 of the comparator COMP6 of the voltage / current converter 600 is high. ), And the inverting output Ion2 becomes low.

Accordingly, the waveforms of the voltage Vt5 applied to the (+) input terminal of the comparator COMP7 of the output comparator 700 and the voltage Vt6 applied to the (−) input terminal are the same as in FIG. .

Therefore, the final output NRZI in the section (3) in which the input current Inn of the decoder section is larger than the sum of the input current Inp and the spare current ir becomes high.

As described above, the data transceiver system of the fast Ethernet physical layer according to the present invention is a high-speed transmission, so not only attenuation in the transmission line is severe but also a direct current due to the inherent property of the transformer if the state of the transmitted data remains unchanged. Since the movement of the baseline causes the DC baseline to not be compensated for when restoring data, jitter becomes unstable in amplitude and phase, and data loss may occur. To solve it.

Claims (3)

In the data transceiver system of the fast Ethernet physical layer, A high pass filter 100 receiving a current mode data input in the form of an MLT3 code to remove unnecessary frequency components and passing only a high range portion of a required frequency; The current classifying unit which receives the signal passing through the high pass filter 100 and moves the DC level to be compared with the intermediate level of the signal passing through the high pass filter 100 in order to eliminate noise generated in the transmission line ( 200); When the input data having a little noise in the same amount as the reference level is received by receiving the data moved by the current classifying unit 200, the previous value is changed to prevent the output from repeating high and low. An input comparison unit 300 for storing and comparing levels; A feedback voltage / current converter 400 for feeding back the output of the input comparator 300 to convert data of a voltage mode into a current mode; Unnecessary frequency components of the current mode data converted by the feedback voltage / current converter 400 are removed, and only a low-pass portion of the required frequency is passed, and the current classifier 200 is summed with the output of the high-pass filter 100. A low pass filter 500 to be inputted into; A voltage / current converter 600 which receives the voltage output of the input comparison unit 300 and converts the voltage output into current mode data; And an output comparator 700 which receives the non-inverted output and the inverted output of the current mode data converted by the voltage / current converter 600, compares the current levels of the two signals, and outputs the result. Fast Ethernet DC Baseline Shift Automatic Compensation Decoder. In claim 1, The high pass filter 100 is Current mode data first and second inputs Inp and Inn in the form of MLT3 codes are applied to an input side, and first and second outputs V3 and V4 are output to an output side; The current classifying unit 200 is Receiving current mode data third and fourth inputs V5 and V6 from the high pass filter 100 to form first to fourth current power supplies Iop2, Iop3, Ion2, and Ion3; The input comparison unit 300 is A first resistor R1 connected to a second current power source Iop2 of the current classifying unit 200 on one side of the power supply voltage VDD; A second resistor R2 connected to a third current power source Ion2 of the current classifying unit 200 on one side of the power supply voltage VDD; A fifth current power source IR1 connected to the contact point of the first resistor R1 and the second current power source Iop2 of the current divider 200; A contact of the first resistor R1 and the fifth current power source IR1 is applied to a positive input terminal as a first input Inp1, and the other side of the second resistor R2 is connected to a negative input terminal. A first comparator COMP1 applied to the second input Inn1, A third resistor R3 connected to the third current power source Iop3 of the current classifying unit 200 on one side of the power supply voltage VDD and the other side; A fourth resistor R4 connected to a fourth current power source Ion3 of the current classifying unit 200 on the other side of the power supply voltage VDD; A sixth current power source IR2 connected to the contact point of the third resistor R3 and the third current power source Iop3 of the current divider 200; A contact of the third resistor R3 and the sixth current power source IR2 is applied to a positive input terminal as a third input Inp2, and the other side of the fourth resistor R4 is connected to a negative input terminal. A second comparator COMP2 applied to the second input Inn2; The feedback voltage / current converter 400 An output of the first comparator COMP1 of the input comparator 300 is applied to a positive input terminal, and an inverted output of the first comparator COMP1 of the input comparator 300 is applied to a negative input terminal. An applied third comparator COMP3; An output of the second comparator COMP2 of the input comparator 300 is applied to a positive input terminal, and an inverted output of the second comparator COMP2 of the input comparator 300 is applied to a negative input terminal. An applied fourth comparator COMP4, A seventh current power source I12 to which the output of the third comparator COMP3 and the inverted output of the fourth comparator COMP4 are applied together; An eighth current power source I11 to which the inverted output of the third comparator COMP3 and the output of the fourth comparator COMP4 are applied together; The low pass filter 500 is The seventh and eighth output voltages V13 and V14 are output by receiving the seventh and eighth current power supplies I11 and I12 from the feedback voltage / current converting unit 400 to respectively output the high pass filter 100. Is combined with the first and second output voltages V3 and V4 and applied to the third and fourth inputs V5 and V6 of the current divider 200. Fast Ethernet DC Baseline Shift Automatic Compensation Decoder. In claim 1, The voltage / current converter 600 The output of the first comparator COMP1 of the input comparator 300 is applied to the (+) input terminal t1, and the first comparator of the input comparator 300 is applied to the (−) input terminal t2. A third comparator COMP5 to which the inverting output of COMP1) is applied; The output of the second comparator COMP2 of the input comparator 300 is applied to the (+) input terminal t3, and the second comparator of the input comparator 300 is applied to the (−) input terminal t4. A fourth comparator COMP6 to which the inverting output of COMP2) is applied; The output comparison unit 700 is The power supply voltage VDD is applied to one side and the sum of the inverted output Ion1 of the third comparator COMP5 of the voltage / current converter 600 and the output Iop2 of the fourth comparator COMP6 are connected to the other side. The first resistor R5, A power supply voltage VDD is applied to one side and a sum of the output Iop1 of the third comparator COMP5 of the voltage / current converter 600 and the inverted output Ion2 of the fourth comparator COMP6 is connected to the other side. The second resistor R6, A first current power source IR3 connected to a contact point of the second resistor R6 and the output Iop1 of the third comparator COMP5 of the voltage / current converter 600; The sum of the output Iop1 of the third comparator COMP5 of the voltage / current converter 600 and the inverted output Ion2 of the fourth comparator COMP6 is applied to a positive input terminal t5, A fifth comparator to which the sum of the inverted output Ion1 of the third comparator COMP5 of the voltage / current converter 600 and the output Iop2 of the fourth comparator COMP6 is applied to the input terminal t6. Containing (COMP7) Fast Ethernet DC Baseline Shift Automatic Compensation Decoder.