KR20000038391A - Method for verifying multiple fpgas using fpga emulator - Google Patents

Abstract

PURPOSE: A method for verifying multiple FPGAs is provided to reduce the number of test pins and a verification time by verifying multiple FPGAs with the use of a host and an FPGA emulator. CONSTITUTION: Circuit blocks logically designed with FPGA chips from a host are mapped(ST1). The FPGA chips(T-FPGA) to be verified out of the FPGA chips are selected(ST2). All paths are searched from test pins of an interface socket to the T-FPGA(ST3). Only the T-FPGA is placed to the FPGA board from the host if the step ST3 is completed(ST4). Other FPGA chips included in the paths reaching the T-FPGA are designed again to be placed(ST5). Logic design blocks except for a circuit block corresponding to the T-FPGA is mounted to the host after placed on the FPGA board(ST6).

Description

Multi-FJA verification method using F-PJA emulator

The present invention relates to a method for verifying a multifuse amplification using a fpuA emulator, and more particularly, to test design blocks placed on FPGA chips constituting a field programmable gate array (FPGA) emulator. The present invention relates to a multi-FPGA verification method using an FFP emulator that forms a virtual path and verifies an FPGA to be verified using the formed virtual path without a test socket.

Field Programmable Gate Array (FPGA), the basis of logic emulators for verifying designed circuits, can emulate complex logic designs at clock rates four to six times faster than high-speed software simulators. An FPGA-based emulator is a heterogeneous network of purpose-built processors, with each FPGA processor individually designed to run jointly with a partition of the entire simulated circuit. Such FPGA logic emulation systems have been developed for complex designs ranging from thousands to tens of thousands of gates. Indeed, the software for the system is considered the most complex component. Emulation systems have been developed to interconnect FPGAs in two-dimensional mesh and partial crossbar topologies. In addition, a structured approach for the connection has been developed. In addition to the above structural approach, another approach uses a combination of the nearest element and crossbar connection. The logical partition is actually wired to the FPGAs according to the partition placement.

A conventional FPGA logic emulation system 5 is shown in FIG. The FPGA logic emulation system 5 can be achieved by interconnecting an array of FPGAs according to a logic design. This array is wired directly to the host 2 capable of downloading the designed circuit and the destination system 8 for logic design. Memory element 6 may be connected to array 10 of FPGAs. The host can be a PC or a workstation.

An example of a detailed placement of an FPGA logic emulation system having the above configuration is shown in FIG. In FIG. 2, reference numeral 20 denotes a host, reference numeral 30 denotes an FPGA board, and reference numeral 35 denotes an interface socket. The FPGA board 30 is composed of a plurality of FPGA chips (A, B, C, D, E, F). Each FPGA chip is placed according to the logic design downloaded from the host 20. The FPGA chips and the host 20 are interconnected by an interface socket 35. The interface socket 35 is connected to the host 20 to transmit n data bits simultaneously. When the placement is completed, the interface socket 35 and the FPGA chips are interconnected as shown in FIG. In this case, the connection lines may be classified into two types. The first category includes lines I, II, III, and IV directly connected between the interface socket 35 and the FPGA chips, and the second category includes lines r, connected between the FPGA chips. s, t, u, v, w). Since the connection lines I, II, III, and IV corresponding to the first category are directly connected to the interface socket 35, the connection lines I, II, III, and IV may be directly verified by the host 20.

However, to verify the connection lines (r, s, t, u, v, w) corresponding to the second category, the interface socket (35) from the pin of the FPGA chip not directly connected to the interface socket (35). There is a method of verifying through a logic analyzer by forming a separate verification line connected to the verification pin of the test circuit or by installing a test socket around the FPGA chip to be verified. The above method is performed with the FPGA emulator placed and mapped to each logical block, and does not take advantage of the features of the FPGA emulator, but uses the test pins to fix the test socket in the case of a complex FPGA emulator having a large number of FPGA blocks to be verified. However, an increase in the number of test pins causes overhead.

Accordingly, the present invention has been invented to solve the above problems, the first object of the present invention is to provide a multi-FPGA verification method using an FPGA emulator that can reduce the number of test pins.

A second object of the present invention is to provide a multi-FPGA verification method using an FPGA emulator that can shorten the verification time using a host and an FPGA emulator.

In order to achieve the above object, the multi-FPGA verification method using the FPGA emulator according to the present invention includes a placement step (ST1) for mapping the circuit blocks designed from the host to the FPGA chip of the FPGA board; A target FPGA selection step (ST2) of selecting an FPGA (T-FPGA) to be verified among the placed FPGA chips; A path search step (ST3) of searching all paths from the test pin of the interface socket to the T-FPGA; A re-placement step (ST4) of placing only the T-FPGA from the host to the FPGA board when the path search step (ST3) is completed; A virtual circuit placement step (ST5) of redesigning and placing other FPGAs included in paths leading to the T-FPGA; Installing logic design blocks on the host except for a circuit block corresponding to the T-FPGA after the T-FPGA and the virtual circuits are placed on the FPGA board (ST6); When the steps ST4, ST5, and ST6 are completed, simulating an FPGA emulation system including the host and the FPGA board in a test pattern written according to a designer's design (ST7); A data simulation step (ST8) of inputting and simulating data to be used on an actual logic circuit when the simulation of the test pattern is completed; Determining whether the verification of the selected T-FPGA chip is completed by checking whether there is no error in the data simulation step (ST8) (ST9); A redesign step (ST11) of redesigning logical blocks by a designer, if there is an error in the T-FPGA verification completion determination step (ST9); If there is no error in the T-FPGA verification completion determination step (ST9), the FPGA board verification completion determination step (ST10) to determine whether the verification of the selected FPGA is completed and to verify all the FPGA; And if the verification of all the FPGAs on the FPGA board is not completed, selecting another T-FPGA (ST12).

1 is a block diagram of a conventional logic emulation system,

2 is a block diagram illustrating an FPGA emulation system including a conventionally placed FPGA board,

3 is a diagram illustrating an example of virtual path formation for verifying multiple FPGAs using an FPGA emulator according to the present invention; and

4 is a flowchart illustrating a multi-FPGA verification method using an FPGA emulator according to the present invention.

<Explanation of symbols for main parts of drawing>

300: FPGA board 350: test socket

A 'to F': FPGA chip a to c: Routing path

t1, t2: test pin , , : Virtual Path

Hereinafter, a multi-FPGA verification method using the FPGA emulator of the present invention will be described in detail with reference to FIGS. 3 and 4. 3 is a diagram illustrating an example of forming a virtual path for verifying a multi-FPGA using an FPGA emulator according to the present invention, and FIG. 4 is a flowchart illustrating a multi-FPGA verification method using the FPGA emulator according to the present invention.

An example of virtual path formation for verifying multiple FPGAs using an FPGA emulator is shown in FIG. 3. In FIG. 3, reference numeral 300 denotes an FPGA board, and reference numeral 250 denotes an interface socket. The FPGA board 300 is composed of a plurality of FPGA chips A ', B', C ', D', E ', and F'. Each FPGA chip is interconnected by paths (a, b, c, etc.) shown in solid lines in FIG. 3 when the placement operation is completed. The FPGA chips A ', B', C ', D', E ', and F' are intended for the FPGA chip C 'rather than the FPGA chips A' and D 'directly connected to the interface socket 350. In the case of determining an FPGA (T-FPGA), the second test pin is passed from the first test pin t1 of the interface socket 350 to the T-FPGA C ′ through the paths formed by the placement operation. A virtual path shown by dotted lines is formed on the figure to form a path to (t2). Pins formed on each of the FPGA chips may be connected by reprogramming the corresponding FPGA. However, virtual paths between FPGA chips must be connected via wires. In order to verify the T-FPGA, a closed path from the first test pin t1 to the second test pin t2 must be formed. That is, a connection path starting from the first test pin t1 to the FPGA chip A ', an unused pin L of the FPGA chip C' from an unused pin M of the FPGA chip A '. Wired to) , Connection line c, virtual path connected inside FPGA chip (B ') , Connection line b, virtual path connected inside FPGA chip (D ') , A connecting path a and a closed path to the second test pin t2 are formed. All the FPGA chips belonging to the closed path may be verified using the first and second test pins t1 and t2.

A method for verifying FPGA chips via a virtual path as shown in FIG. 3 will be described by the flow chart shown in FIG. First, a placement step ST1 of mapping logic blocks designed from the host (not shown) to the FPGA chips A ', B', C ', D', E ', and F' of the FPGA board 300 is performed. do. When the placement step ST1 is completed, a target FPGA selection step ST2 for selecting an FPGA (T-FPGA) to be verified among the mapped FPGA chips is performed. When the target FPGA selection step ST2 is performed, a path search step ST3 for searching all paths from the test pins t1 and t2 of the interface socket 350 to the T-FPGA is performed. . When the path search step ST3 is completed, a replacement step ST4 for performing placement of the T-FPGA from the host to the FPGA board 300 is performed. When the replacement step ST4 is completed, a virtual circuit placement step ST5 for redesigning and placing other FPGAs included in the paths to the T-FPGA is performed. When the steps ST4 and ST5 where the T-FPGA and the virtual circuits are placed on the FPGA board 300 are completed, logic design blocks excluding circuit blocks corresponding to the T-FPGA are installed on the host. Step ST6 is performed. When the step ST6 is completed, a step ST7 of simulating an FPGA emulation system including the host and the FPGA board 300 using a test pattern created according to a designer's design is performed. When the simulation of the test pattern is completed, a data simulation step ST8 is performed to input and simulate data to be used on an actual logic circuit. When the data simulation step ST8 is completed, the step ST9 is performed to determine whether verification of the selected T-FPGA chip is completed by checking whether there is no error in the ST8 step. If there is an error in the T-FPGA verification completion determination step ST9, a redesign step ST11 of redesigning the logic blocks is performed by a designer, while an error is performed in the T-FPGA verification completion determination step ST9. If not, the FPGA board verification completion determination step (ST10) to determine whether the verification of the selected FPGA is completed and to verify all the FPGA is performed. If the verification of all FPGAs on the FPGA board is not completed, a step ST12 of selecting another T-FPGA is performed, and the process proceeds to step ST3.

Accordingly, according to the multi-FPGA verification method using the FPGA emulator of the present invention as described above, the following effects can be obtained.

First, the number of test pins can be reduced by validating multiple FPGAs using the host and the FPGA emulator.

Second, the verification time is reduced by verifying multiple FPGAs using the host and the FPGA emulator.

As mentioned above, although this invention was demonstrated concretely by the above-mentioned Example, this invention is not limited to this, The deformation | transformation and improvement are possible within the range of common knowledge of a person skilled in the art.

Claims (1)

A placement step (ST1) of mapping logically designed circuit blocks from a host to FPGA chips of a Field Programmable Gate Array (FPGA) board; A target FPGA selection step (ST2) of selecting an FPGA (T-FPGA) to be verified among the placed FPGA chips; A path search step (ST3) of searching all paths from the test pin of the interface socket to the T-FPGA; A re-placement step (ST4) of placing only the T-FPGA from the host to the FPGA board when the path search step (ST3) is completed; A virtual circuit placement step (ST5) of redesigning and placing other FPGAs included in paths leading to the T-FPGA; Installing logic design blocks on the host except for a circuit block corresponding to the T-FPGA after the T-FPGA and the virtual circuits are placed on the FPGA board (ST6); When the steps ST4, ST5, and ST6 are completed, simulating an FPGA emulation system including the host and the FPGA board in a test pattern written according to a designer's design (ST7); A data simulation step (ST8) of inputting and simulating data to be used on an actual logic circuit when the simulation of the test pattern is completed; Determining whether the verification of the selected T-FPGA chip is completed by checking whether there is no error in the data simulation step (ST8) (ST9); A redesign step (ST11) of redesigning logical blocks by a designer, if there is an error in the T-FPGA verification completion determination step (ST9); If there is no error in the T-FPGA verification completion determination step (ST9), the FPGA board verification completion determination step (ST10) to determine whether the verification of the selected FPGA is completed and to verify all the FPGA; And if the verification of all the FPGAs on the FPGA board is not completed, perform a step of selecting another T-FPGA (ST12) and proceed to the step ST3. This verification method in the mouse.