KR20000033914A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR20000033914A KR20000033914A KR1019980050980A KR19980050980A KR20000033914A KR 20000033914 A KR20000033914 A KR 20000033914A KR 1019980050980 A KR1019980050980 A KR 1019980050980A KR 19980050980 A KR19980050980 A KR 19980050980A KR 20000033914 A KR20000033914 A KR 20000033914A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- semiconductor device
- drain
- forming
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- 239000007772 electrode material Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract 2
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 반도체소자의 채널길이가 짧아짐에 따라 발생되는 문제점들을 완화시키기 위하여 채택된 엘디디(lightly doped drain : LDD) 구조를 측벽을 사용하지 않고 제작하여 특성을 향상시킬 수 있도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to fabricate a lightly doped drain (LDD) structure adopted to alleviate the problems caused by shortening the channel length of a highly integrated semiconductor device without using sidewalls. The present invention relates to a method for manufacturing a semiconductor device capable of improving characteristics.
종래 측벽을 이용한 엘디디 구조의 반도체소자 제조방법을 도1a 내지 도1c의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a semiconductor device having an LED structure using a conventional sidewall will now be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1C.
먼저, 도1a에 도시한 바와같이 엔형 반도체기판(1) 상에 피형 웰(2) 및 분리영역(3)을 통상적인 이온주입후 열처리 및 필드 산화공정을 통해 형성한 후, 그 피형 웰(2)의 상부 액티브영역에 산화공정을 수행하여 게이트산화막(4)을 형성하고, 그 게이트산화막(4)의 상부에 폴리실리콘을 증착 및 패터닝하여 게이트전극(5)을 형성한다.First, as shown in FIG. 1A, the well type 2 and the isolation region 3 are formed on the N-type semiconductor substrate 1 through conventional ion implantation, followed by heat treatment and field oxidation, and then the type well 2 The gate oxide film 4 is formed by performing an oxidation process on the upper active region of the C), and the polysilicon is deposited and patterned on the gate oxide film 4 to form the gate electrode 5.
그리고, 도1b에 도시한 바와같이 상기 게이트전극(5)이 형성된 반도체기판(1) 상의 상부전면에 산화막과 같은 절연막(6)을 증착한다.As shown in FIG. 1B, an insulating film 6 such as an oxide film is deposited on the upper surface of the semiconductor substrate 1 on which the gate electrode 5 is formed.
그리고, 도1c에 도시한 바와같이 상기 절연막(6)을 선택적으로 건식식각하여 상기 게이트전극(5)의 측면에 측벽(7)을 형성하고, 그 게이트전극(5)과 측벽(7)을 마스크로, 노출된 게이트산화막(4)을 버퍼로 하여 고농도의 엔형 불순물이온(N+)을 주입한 후 열처리함으로써, 저농도 불순물영역(8)과 고농도 불순물영역(9)의 소스/드레인을 동시에 형성한다.As shown in FIG. 1C, the insulating layer 6 is selectively dry-etched to form sidewalls 7 on the side surfaces of the gate electrode 5, and the gate electrodes 5 and sidewalls 7 are masked. In this case, the exposed gate oxide film 4 is used as a buffer to inject high concentrations of N-type impurity ions (N + ) and then heat-treat them to simultaneously form the source / drain of the low concentration impurity region 8 and the high concentration impurity region 9. .
그러나, 상기한 바와같은 종래 반도체소자 제조방법은 게이트의 측면에 측벽을 형성하기 위해 추가되는 절연막의 증착 및 선택적 건식식각공정의 제어가 어려워 반도체기판의 손상 또는 식각이 유발됨에 따라 누설전류가 증가하는 등의 동작특성이 저하되는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, it is difficult to control the deposition and additional dry etching process of the insulating film added to form sidewalls on the side of the gate, so that leakage current increases due to damage or etching of the semiconductor substrate. There was a problem that the operating characteristics such as deterioration.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 측벽을 형성하지 않고 엘디디구조를 형성할 수 있는 고집적의 반도체소자 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a highly integrated semiconductor device manufacturing method capable of forming an LED structure without forming sidewalls.
도1은 종래 측벽을 이용한 엘디디 구조의 반도체소자 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a method of manufacturing a semiconductor device of an LED structure using a conventional sidewall.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:엔형 반도체기판 12:피형 웰11: N-type semiconductor substrate 12: Blood well
13:분리영역 14:게이트산화막13: separation region 14: gate oxide film
15:게이트전극 16:저농도 불순물영역15: gate electrode 16: low concentration impurity region
17:고농도 불순물영역17: high concentration impurity region
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 반도체기판의 상부에 순차적으로 게이트산화막과 게이트전극물질을 증착한 후, 그 게이트전극물질을 패터닝하여 게이트전극을 형성하는 공정과; 상기 게이트전극 및 저농도 드레인이 형성될 영역의 상부에 감광막 패턴을 형성한 후, 고농도의 불순물이온을 주입하여 소스 및 엘디디구조의 드레인을 동시에 형성하는 공정을 구비하여 이루어짐을 특징으로 한다.A preferred embodiment of the method of manufacturing a semiconductor device for achieving the object of the present invention as described above is to sequentially deposit a gate oxide film and a gate electrode material on top of the semiconductor substrate, and then pattern the gate electrode material to form a gate electrode. Forming step; And forming a photoresist pattern on the region where the gate electrode and the low concentration drain are to be formed, and then simultaneously implanting a high concentration of impurity ions to form a drain of the source and the LED structure.
상기한 바와같은 본 발명에 의한 반도체소자 제조방법의 바람직한 일 실시예를 도2a 내지 도2c의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2C.
먼저, 도2a에 도시한 바와같이 엔형 반도체기판(11) 상에 피형 웰(12) 및 분리영역(13)을 형성한 후, 그 피형 웰(12)의 상부에 산화공정을 수행하여 게이트산화막(14)을 형성하고, 그 게이트산화막(14)의 상부에 폴리실리콘을 증착 및 패터닝하여 게이트전극(15)을 형성한다.First, as shown in FIG. 2A, the wells 12 and isolation regions 13 are formed on the N-type semiconductor substrate 11, and then an oxidation process is performed on the wells 12 to form a gate oxide film ( 14) and polysilicon is deposited and patterned on the gate oxide film 14 to form the gate electrode 15.
그리고, 도2b에 도시한 바와같이 상기 게이트전극(15)이 형성된 반도체기판(11)의 상부에 감광막을 도포한 후, 노광 및 현상하여 게이트전극(15) 및 저농도 드레인이 형성될 영역의 상부에 감광막 패턴(PR11)을 형성한다. 이때, 감광막 패턴(PR11)을 형성하기 위한 마스크는 상기 게이트전극(15)의 패터닝시에 적용된 마스크에 대한 데이터를 시프트(shift)시켜 사용함으로써, 감광막 패턴(PR11)을 형성하기 위한 마스크를 용이하게 제작하는 것도 고려될 수 있다.As shown in FIG. 2B, a photosensitive film is coated on the semiconductor substrate 11 on which the gate electrode 15 is formed, and then exposed and developed to cover the gate electrode 15 and the region where the low concentration drain is to be formed. The photoresist pattern PR11 is formed. In this case, the mask for forming the photoresist pattern PR11 may be used by shifting data on the mask applied when the gate electrode 15 is patterned, thereby easily forming the mask for forming the photoresist pattern PR11. Fabrication may also be considered.
그리고, 도2c에 도시한 바와같이 상기 감광막 패턴(PR11)을 적용하고, 노출된 게이트산화막(14)을 버퍼로 하여 고농도의 엔형 불순물이온(N+)을 주입한 후 열처리함으로써, 저농도 불순물영역(16)과 고농도 불순물영역(17)의 소스/드레인을 동시에 형성한다.As shown in FIG. 2C, the photoresist pattern PR11 is applied, and a high concentration of N-type impurity ions (N + ) is implanted using the exposed gate oxide layer 14 as a buffer, followed by heat treatment, thereby providing a low concentration impurity region ( 16) and the source / drain of the high concentration impurity region 17 are formed at the same time.
한편, 상기 본 발명의 일 실시예는 피형 웰(12)이 형성된 엔형 반도체기판(11) 상에 엘디디구조의 엔모스 트랜지스터를 제조하는 경우로 한정하여 설명하였지만, 엔형 반도체기판(11) 상에 피모스 트랜지스터를 제조하는 경우에도 동일하게 적용할 수 있으며, 엔모스 및 피모스 트랜지스터를 동시에 제조하는 씨모스(CMOS) 트랜지스터의 경우에도 엔모스 및 피모스 트랜지스터 모두에 적용하거나 또는 선택적으로 하나의 트랜지스터에 적용할 수 있다.On the other hand, the embodiment of the present invention has been described to be limited to the case of manufacturing the NMOS transistor of the LED structure on the n-type semiconductor substrate 11, the formed well 12, on the n-type semiconductor substrate 11 The same applies to the manufacture of PMOS transistors, and in the case of CMOS transistors producing NMOS and PMOS transistors simultaneously, the transistors may be applied to both NMOS and PMOS transistors or, optionally, to one transistor. Applicable to
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 측벽을 사용하지 않고 엘디디구조의 모스 트랜지스터를 제조함으로써, 종래에 절연막의 선택적 건식식각으로 인해 문제시되던 반도체소자의 동작특성을 향상시킬 수 있는 효과와 아울러 씨모스 트랜지스터의 제조시 엔모스 및 피모스 트랜지스터에 대해 선택적으로 적용할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, by manufacturing a MOS transistor having an LED structure without using sidewalls, it is possible to improve the operation characteristics of the semiconductor device, which is conventionally a problem due to selective dry etching of an insulating film. In addition to the effects there is an effect that can be selectively applied to the NMOS and PMOS transistors in the manufacturing of the CMOS transistors.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980050980A KR20000033914A (en) | 1998-11-26 | 1998-11-26 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980050980A KR20000033914A (en) | 1998-11-26 | 1998-11-26 | Method for fabricating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000033914A true KR20000033914A (en) | 2000-06-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980050980A KR20000033914A (en) | 1998-11-26 | 1998-11-26 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000033914A (en) |
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1998
- 1998-11-26 KR KR1019980050980A patent/KR20000033914A/en not_active Application Discontinuation
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