KR20000031481A - Delay looked loop with varying clock delay and semiconductor memory device using delay looked loop - Google Patents

Abstract

PURPOSE: A delay locked loop with varying clock delay is provided wide active frequency range. And a memory device is provided by using the delay locked loop. CONSTITUTION: A phase detector(311) receives Reference Clock signal(RCLK) and Feedback Clock Signal(FDCLK) from delay complementary circuit(341). The phase detector(311) compares the phase of two signals and generate up or down signal. A charge pump(321) produces direct current voltage(VCON) based on the signals of pause detector(311). If the up signal is generated, the VCON is higher than reference level. If the down signal is produced, the VCON is lower than reference level. A variable delay circuit(331) receives and delays PCLK under controlling of VCON from the charge pump(321), power up signal(PVCCH), and synchronous signal(DLLST). The variable delay circuit(331) has many delay units. After passing the variable delay circuit(321), the RCLK is changed advanced clock signal(ADCLKN) with variant delay time. The delay time is depend on the number of operating delay units. The phase detector(311) compares the phase of RCLK and ADCLKN(or FDCLK) and adjusts the number of delay units in the variable delay circuit(331) to reduce phase difference of the two signals. Using the delay locked loop(301) in semiconductor memory device, the memory device is managed to active frequency range without altering inner circuit.

Description

Delayed synchronous loop for varying delay of clock signal and semiconductor memory device employing same

The present invention relates to an electrical circuit, and more particularly, to a delay lock loop and a semiconductor memory device employing the same.

The delay lock loop is used to provide a clock signal having a shift of a certain time with respect to the reference clock signal. Although the clock signal provided by the delay lock loop circuit is delayed with respect to the reference clock, it is often phased ahead of the reference clock. Thus, in this specification, for convenience of description, the signal generated by the delay lock loop is called an advanced clock signal.

In general, situations that require an advanced clock signal are relatively common, such as Merged Memory with Logic (MML), Rambus DRAM (RDRAM), and Double Data Rate Synchronous DRAM (DDR). It occurs in an integrated circuit (IC) circuit having a high degree of integration. The reference clock signal is input to one pin and distributed throughout the device. The reference clock signal arriving at a portion relatively far from the input pin can be significantly delayed relative to the reference clock signal at the portion immediately adjacent to the input pin. This delay makes it difficult to maintain synchronization between parts of the IC.

To compensate for this problem, a delay locked loop circuit may be included on the IC. The delay lock loop circuit is typically located close to the input pin that inputs the reference clock signal. This delay lock loop circuit receives a reference clock signal and generates a preceding clock signal. This leading clock signal is generally similar to the reference clock signal. However, the phase advances by approximately the same amount of time required for the preceding clock signal to reach far from parts of the integrated circuit where the clock is relatively close to the reference clock input pin. The reference clock signal continues to be used near the input pin of the reference clock signal, while the preceding reference clock signal is sent farther away in the IC mentioned above in alignment with the original reference clock signal. In this way, a synchronized clock signal is received at every part of the IC, which operates the synchronized operation of the IC even at very high speeds.

1 is a block diagram of a conventional delay lock loop. The conventional delay lock loop circuit 101 is configured as a phase detector 111, a charge pump 121, a variable delay circuit 131 and a delay compensation circuit 141, as shown in FIG. The delay lock loop circuit 101 typically adjusts the delay time by the variable delay circuit 131 when the phase of the feedback clock signal 143 advances or falls behind the phase of the reference clock signal RCLK. The phase of the signal 143 matches the phase of the reference clock signal RCLK.

However, the variable delay circuit 131 constituting the conventional delay lock loop 101 has a certain number of delays D1 to Dn, as shown in FIG. As described above, when the number of delayers D1 to Dn is constant, the variable delay range is limited, so that an operating frequency range exists. That is, when a frequency smaller than the operating frequency range is input, the delay of the variable delay circuit 131 is no longer increased, and jitter is generated in a direction in which the feedback signal 143 precedes the external input signal. do. On the contrary, when a frequency larger than the operating frequency range is input, the delay of the variable delay circuit 131 is no longer reduced, and thus jitter occurs in a direction in which the feedback signal 143 is later than the external input signal. Therefore, a problem arises that the operating frequency of the input signal is limited in the semiconductor memory device (not shown) that ultimately uses the delay lock loop 101.

The technical problem to be achieved by the present invention is to provide a delay lock loop to widen the operating frequency range.

Another object of the present invention is to provide a semiconductor memory device having the delay synchronization loop to widen an operating frequency range.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional delay lock loop.

FIG. 2 is a detailed block diagram of the variable delay circuit shown in FIG.

3 is a block diagram of a delay lock loop in accordance with a preferred embodiment of the present invention.

FIG. 4 is a diagram illustrating a change in power-up of an external power supply voltage VCC of the power-up signal shown in FIG. 3.

5 is a circuit diagram of the variable delay circuit shown in FIG.

6 is a schematic block diagram of a semiconductor memory device according to the present invention.

The delay synchronization loop of the present invention for achieving the above technical problem is a delay synchronization loop for inputting a reference clock signal, by feeding back the signal output from the delay synchronization loop to the phase of the feedback clock signal and the phase of the reference clock signal In the matched delay lock loop, a phase detector for comparing a phase of the reference clock signal and a phase of the fed back clock signal and outputting a difference, and a charge pump for outputting a voltage that is increased or decreased in response to an output of the phase detector. And a control register for generating a plurality of control signals, and a plurality of delayers, the delay of the reference clock signal in response to the input of the reference clock signal and output from the charge pump and the plurality of control signals. It is characterized by varying the time.

Preferably, the delay lock loop further comprises a delay compensation circuit for compensating the phase of the fed back clock signal, the voltage level of the control signals output from the control register can be arbitrarily changed externally.

Preferably, further comprising a switching circuit between the variable delay circuit and the control register, the switching circuit is connected to a plurality of delays of a plurality of delays included in the variable delay circuit, the control register The operation of the plurality of delayers is controlled in response to control signals output from the controller and a control signal input from the outside, and a control signal input to the switching circuit from the outside is powered by a power supply voltage applied to the delay synchronization loop. When up and above a predetermined level, the enabled power-up signal and the variable delay circuit are enabled when operating.

The semiconductor memory device of the present invention for achieving the above another technical problem,

The voltage level of the internal clock signal output from the delayed synchronization loop, the clock buffer for generating an internal clock signal by converting the voltage level of the external clock signal input from the outside, the phase of the internal clock signal is stabilized, And an output buffer for converting, wherein the delay lock loop compares a phase of the internal clock signal with a phase of a signal fed back from the delay lock loop and outputs a difference, and increases and decreases in response to an output of the phase detector. A charge pump for outputting a voltage, and a plurality of delayers, and varying a delay time of the internal clock signal in response to a voltage input from the charge pump and a control signal input from the outside. A variable delay circuit is provided.

Preferably, the voltage level of the internal clock signal output from the clock buffer is a complementary metal oxide semiconductor (CMOS) level.

The operating frequency range of the semiconductor memory device including the delay lock loop and the delay lock loop of the present invention as described above is widened.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In each drawing, the same reference numerals denote the same members.

3 is a block diagram of a delay lock loop according to a preferred embodiment of the present invention. Referring to FIG. 3, a delay lock loop 301 according to a preferred embodiment of the present invention includes a phase detector 311, a charge pump 321, a variable delay circuit 331, and a delay compensation circuit 341.

The phase detector 311 compares the phase of the reference clock signal RCLK with the phase of the signal FDCLK output from the delay compensation circuit 341, and according to the result, an up signal UP or a down signal DOWN. Occurs. That is, the phase detector 311 generates the up signal UP when the phase of the reference clock signal RCLK is earlier than the phase of the signal FDCLK output from the delay compensation circuit 341 and the phase of the reference clock signal RCLK. When the signal FDCLK is out of phase, a down signal DOWN is generated.

The charge pump 321 outputs a DC voltage VCON in response to an up signal UP or a down signal DOWN. When the up signal UP is generated from the phase detector 311, the DC voltage VCON is higher than the predetermined level. When the down signal DOWN is generated from the phase detector 311, the DC voltage VCON is lower than the measure level.

The variable delay circuit 331 inputs the reference clock signal RCLK and is controlled by the DC voltage VCON output from the charge pump 321, the power-up signal PVCCH and the synchronization signal DLLST input from the outside. The reference clock signal RCLK is delayed for a predetermined time. The variable delay circuit 331 includes a plurality of delayers (D1 to Dni in FIG. 5). The delay time of the reference clock signal ADCLKN passing through the variable delay circuit 331 varies depending on whether the parts Dn to Dni of the plurality of delayers D1 to Dni of FIG. 5 are operated. Therefore, the reference clock signal ADCLKN passed through the variable delay circuit 331 is fed back to the phase detector 311 and compared with the phase of the reference clock signal RCLK input to the phase detector 311. At this time, if the phase of the reference clock signal RCLK input to the phase detector 311 is ahead of the reference clock signal ADCLKN passing through the variable delay circuit 331, some delayers included in the variable delay circuit 331 are included. (Dn to Dni in FIG. 5 is operated a lot to delay the reference clock signal ADCLKN which has passed through the variable delay circuit 331 a lot, and the phase of the reference clock signal RCLK input to the phase detector 311 is variable. When it is behind the reference clock signal ADCLKN which has passed through the delay circuit 331, some of the delayers included in the variable delay circuit 331 (Dn to Dni of FIG. 5) are operated less and pass through the variable delay circuit 331. Delay one reference clock signal ADCLKN less. In this way, the phase of the reference clock signal RCLK input to the phase detector 311 and the phase of the reference clock signal ADCLKN passed through the variable delay circuit 331 are matched. The reference clock signal ADCLK passing through the variable delay circuit 331 is directly fed back to the phase detector 311 as described above, but is also phased as a delay-compensated signal FDCLK through the delay compensation circuit 341. It may be fed back to the detector 311. Whichever of the above two methods is used, the phase detector 311 compares the phases of the input signals RCLK, ADCLKN or FDCLK, and thus the delay lock loop 301 shows the same result.

The phase difference of the feedback signal FDCLK with respect to the reference clock signal RCLK is determined by adjusting the number of some delayers Dn to Dni included in the variable delay circuit 331 as described above. Enter within the range of. Since the variable delay circuit 331 is specifically illustrated in FIG. 5, the variable delay circuit 331 will be described in detail with reference to FIG. 5.

The delay compensation circuit 301 compensates the phase of the reference clock signal RCLK output from the variable delay circuit 331 and transfers the phase to the phase detector 311. If a delay compensation circuit 341 is not included in the delay lock loop 301 of the present invention, an error equal to a transmission delay time occurs between a point near and a point far from an output terminal of the variable delay circuit 331. However, even if the delay lock loop 301 of the present invention does not use the delay compensation circuit 341, the effect of the present invention is achieved.

FIG. 4 is a diagram illustrating a change in power-up of the external power supply voltage VCC of the power-up signal PVCCH illustrated in FIG. 3. When the external power supply voltage VCC is lower than the predetermined voltage VT, the power-up signal PVCCH maintains a low level voltage, that is, a ground voltage VSS level. When the external power supply voltage VCC is higher than the predetermined voltage VT, the power-up signal PVCCH is maintained at a high voltage level, that is, at the same voltage level as the external power supply voltage VCC.

FIG. 5 is a circuit diagram of the variable delay circuit 331 shown in FIG. Referring to FIG. 5, the variable delay circuit 331 includes a plurality of delay units D1 to Dni, switching circuits 521 and 525, and a control register 511.

The retarders D1 to Dn-1 are controlled by the DC voltage VCON and the power supply voltage VCC, respectively. That is, the delayers D1 to Dn-1 are activated when the DC voltage VCON is higher than the predetermined level while the power supply voltage VCC is applied, and is deactivated when the DC voltage VCON is lower than the predetermined level. The reference clock signal RCLK sequentially passes through the delayers D1 to Dn-1 and is input to the delayer Dn.

The delay unit Dn inputs the reference clock signal RCLK delayed by the delay unit Dn-1 through the transmission gate 571 and outputs through the transmission gate 572. The retarder Dn is controlled by the DC voltage VCON and the control signal P1. That is, the retarder Dn is activated and operated when the DC voltage VCON is higher than the predetermined level and the control signal P1 is high, and the DC voltage VCON is lower than the predetermined level or the control signal P1 is lowered. It does not work at the low level. When the control signal P1 is at a high level, the transfer gates 571 and 572 are turned on. Accordingly, the delay unit Dn is activated, and receives the reference clock signal RCLK output from the delay unit Dn-1, delays it for a predetermined time, and outputs it through the transmission gate 572. If the control signal P1 is at the low level, the delay device Dn is inactivated and the transfer gate 573 is turned on at the same time. Therefore, the reference clock signal RCLK output from the delay unit Dn-1 is transmitted directly to the later delay unit without passing through the delay unit Dn.

The delay unit Dni is controlled by the control signal Pn and the DC voltage VCON to delay the reference clock signal RCLK output from the delay unit of the previous stage. Since the operation of the retarder Dni is the same as that of the retarder Dn, redundant description will be omitted.

The control register 511 generates a plurality of control signals P1 to Pn. The control signals P1 to Pn output from the control register 511 can be arbitrarily changed externally.

The switching circuit 521 inputs the control signal P1, the power-up signal PVCCH, and the synchronization signal DLLST output from the control register 511, and outputs the control signal P1. The switching circuit 521 includes a NAND gate 531, PMOS transistors 533 and 535, NMOS transistors 537 and 539, and inverters 541 and 543. If any one of the power-up signal PVCCH and the synchronization signal DLLST is logic low, the output of the NAND gate 531 is logic high. Then, the NMOS transistor 537 is turned on. When both the power-up signal PVCCH and the synchronization signal DLLST are logic high, the output of the NAND gate 531 is logic low, and the PMOS transistor 533 is turned on. The power-up signal PVCCH is maintained at a low level but becomes high when the power supply voltage VCC is above a predetermined level. The synchronization signal DLLST is maintained at a low level when the variable delay circuit 331 of FIG. 3 is inactivated and rises to a high level when the variable delay circuit 331 of FIG. 3 is activated.

When the variable delay circuit 331 of FIG. 3 is inactivated, the NMOS transistor 537 is turned on because the synchronization signal DLLST is at a low level. Inverter 543 then outputs a low level signal. Since the power-up signal PVCCH is at the low level when the power supply voltage VCC is not powered up, the NMOS transistor 537 is turned on so that the inverter 543 outputs a low-level signal. When the synchronization signal DLLST and the power-up signal PVCCH are both at high level, the output of the NAND gate 531 is at low level, so the NMOS transistor 537 is turned off and the PMOS transistor 531 is turned on. In this state, when the control signal CR1 output from the control register 511 is logic low, the PMOS transistor 535 is turned on, thereby causing the control signal P1 output from the inverter 543 to be logic high.

Since all the switching circuits connected to the control register 511 including the switching circuit 525 have the same structure and operation as the switching circuit 521, the redundant description is omitted.

Although only one of each of the plurality of delayers Dn to Dni and the plurality of switching circuits 521 to 525 shown in FIG. 5 exists, the delayed synchronization loop 301 of FIG. It will be apparent to those skilled in the art that A can be achieved.

6 is a schematic block diagram of a semiconductor memory device according to the present invention. Referring to FIG. 6, the semiconductor memory device 601 includes a clock buffer 611, a delay lock loop 621, an output buffer 631, and an internal circuit 641.

The clock buffer 611 converts the voltage level of the external clock signal CLK input from the outside to generate the internal clock signal PCLK. In the semiconductor memory device 601, the internal circuit 641 is mostly composed of CMOS transistors. Accordingly, the clock buffer 611 may have a high voltage level of the internal clock signal PCLK such that the internal clock signal PCLK matches the CMOS transistors regardless of the voltage level of the external clock signal clk input from the outside. Is converted to a CMOS voltage level, for example 3.3 volts.

The delay lock loop 621 stabilizes and outputs the phase of the internal clock signal PCLK within a predetermined range. Since the delay sync loop 621 has the same configuration and operation as that shown in FIG. 3, redundant description will be omitted.

The output buffer 631 outputs data Di, which is input from the internal circuit 641, to the outside in synchronization with the clock signal CLKDQ output from the delay synchronization loop 621.

As shown in FIG. 6, the operating frequency range can be adjusted by employing the delay synchronization loop 621 shown in FIG. 3 in the semiconductor memory device 601. In other words, when the operating frequency region determined as a design target and the operating frequency region are different after the semiconductor memory device 601 is manufactured, a desired value is written in the control register 511 of FIG. 5 to target the operating frequency region. You can adjust it to the value you set. As such, the operating frequency range may be adjusted as desired by the user without modifying the internal circuit of the semiconductor memory device 601. Therefore, the semiconductor memory device can be used for high frequency operation and low frequency operation, thereby increasing the application range.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the operating frequency range can be widened by the delay lock loop 301 according to the present invention. In addition, the delay synchronization loop 301 is employed in the semiconductor memory device 601 to write down a target value in the control register 511 even after the semiconductor memory device 601 is manufactured, thereby operating frequency of the semiconductor memory device 601. Since the region can be adjusted to a desired value, the application range regarding the operating frequency of the semiconductor memory device is widened.

Claims (7)

A delayed synchronization loop for inputting a reference clock signal, the delayed synchronization loop for feeding back the signal output from the delayed synchronization loop to match the phase of the feedback clock signal with the phase of the reference clock signal, A phase detector for comparing a phase of the reference clock signal with a phase of the fed back clock signal and outputting a difference; A charge pump for outputting a voltage that is increased or decreased in response to the output of the phase detector; A control register for generating a plurality of control signals; And And a variable delay circuit for inputting the reference clock signal and varying a delay time of the reference clock signal in response to a voltage output from the charge pump and the plurality of control signals. Delayed synchronization loop. The method of claim 1, wherein the delay lock loop And a delay compensation circuit for compensating for the phase of the fed back clock signal. 2. The apparatus of claim 1, further comprising a switching circuit between the variable delay circuit and the control register, wherein the switching circuit is connected to a plurality of delayers of a plurality of delayers included in the variable delay circuit. And controlling the operations of the plurality of delayers in response to control signals output from a register and control signals input from the outside. 4. The variable delay circuit of claim 3, wherein the control signal input to the switching circuit from the outside is enabled when the power supply voltage applied to the delay lock loop is powered up and higher than a predetermined level. And a delay enabled loop. The delay lock loop as recited in claim 1, wherein a voltage level of control signals output from the control register is arbitrarily changed externally. In a semiconductor memory device, A clock buffer converting a voltage level of an external clock signal input from the outside to generate an internal clock signal; A delay lock loop for stabilizing a phase of the internal clock signal; And An output buffer operated in synchronization with an internal clock signal output from the delay lock loop, The delay lock loop may include a phase detector for comparing a phase of the internal clock signal with a phase of a signal fed back from the delay lock loop and outputting a difference; A charge pump for outputting a voltage that is increased or decreased in response to the output of the phase detector; And And a variable delay circuit for inputting the internal clock signal and varying a delay time of the internal clock signal in response to a voltage output from the charge pump and a control signal input from the outside. A semiconductor memory device. The semiconductor memory device of claim 6, wherein a voltage level of the internal clock signal output from the clock buffer is a CMOS level.