KR20000027682A - Semiconductor device capable of dispersing current paths by electrostatic discharge - Google Patents

Semiconductor device capable of dispersing current paths by electrostatic discharge Download PDF

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Publication number
KR20000027682A
KR20000027682A KR1019980045673A KR19980045673A KR20000027682A KR 20000027682 A KR20000027682 A KR 20000027682A KR 1019980045673 A KR1019980045673 A KR 1019980045673A KR 19980045673 A KR19980045673 A KR 19980045673A KR 20000027682 A KR20000027682 A KR 20000027682A
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South Korea
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power supply
semiconductor device
well
node
pins
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KR1019980045673A
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Korean (ko)
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이남영
남종완
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김영환
현대전자산업 주식회사
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Priority to KR1019980045673A priority Critical patent/KR20000027682A/en
Publication of KR20000027682A publication Critical patent/KR20000027682A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

PURPOSE: A device is provided to prevent a deterioration of a device by dispersing current due to an electrostatic discharge stress in a semiconductor device having separated electric power supplies. CONSTITUTION: A first well of a first conductive-type is formed on a semiconductor substrate and between adjacent electric power pins(Vccddq, Vccin, Vcc peri). A node isolation regions(ISO) isolates plural nodes formed on the surface of the first well, having a second conductive-type, and connected to adjacent electric power supply pins(Vccdq, Vccin, Vcc peri), and adjacent nodes. A parasitic bipolar transistor is connected to adjacent electric power supply pins(Vccdq, Vccin, Vcc peri) with an application of an electrostatic discharge through the pins(Vccdq, Vccin, Vcc peri).

Description

정전방전에 의한 전류의 경로를 분산할 수 있는 반도체 소자Semiconductor device capable of distributing current paths by electrostatic discharge

본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 전원(power)이 회로 블록(block)별로 분리되는 반도체 소자의 ESD(electrostatic discharge) 스트레스를 효과적으로 분산시킬 수 있는, 정전방전에 의한 전류의 경로를 분산할 수 있는 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and in particular, to distribute the path of current due to electrostatic discharge, which can effectively distribute the electrostatic discharge (ESD) stress of semiconductor devices in which power is separated by circuit blocks. It is related with the semiconductor element which can be performed.

도1은 전원이 분리되지 않은 종래 반도체 메모리 소자의 출력버퍼와 입력버퍼의 구성을 도시한 회로도이다. 출력 패드(p)에서 데이터를 출력할 때, 출력버퍼(output buffer)에서 과도한 전류를 끌어내기 때문에 Vccdq에서 큰 잡음이 발생한다. 이러한 잡음은 입력버퍼(input buffer) 혹은 주변 지역의 회로를 오동작시키는 문제점이 있다.1 is a circuit diagram showing the configuration of an output buffer and an input buffer of a conventional semiconductor memory device in which power is not separated. When outputting data from the output pad p, a large noise occurs at V ccdq because it draws excessive current from the output buffer. This noise has a problem of malfunctioning the input buffer or the circuit of the surrounding area.

따라서, 주변회로 블록과의 잡음(noise) 간섭을 줄이기 위해 출력버퍼, 입력버퍼 및 주변회로영역 또는 셀영역의 전원을 각각 Vccdq, Vccin, Vccperi로 분리하여 3개의 전원 공급 핀을 갖는 구조의 반도체 소자가 제시되었다.Thus, the structure having a noise (noise) in order to reduce interference output buffer, the power of the input buffer and the peripheral circuit region or a cell area, each V ccdq, separated by V ccin, V ccperi 3 of the power supply pin of the peripheral circuit block The semiconductor device of was presented.

도2는 전원이 분리된 종래 반도체 소자의 개략적인 단면도로서, 출력버퍼, 입력버퍼, 주변회로영역과 셀영역의 전원이 각각 Vccdq, Vccin, Vccperi로 분리된 것을 보이고 있다. 도2에서 미설명 도면 부호 n+는 각각 웰-픽업(well-pick up)을 나타낸다.Figure 2 shows that the power is separated conventionally a schematic sectional view of a semiconductor device, the output buffer, input buffer, the power supply of the peripheral circuit region and the cell region, respectively, separated by V ccdq, ccin V, V ccperi. In FIG. 2, unexplained reference numerals n + denote well-pick-ups, respectively.

한편, 도1에 도시한 반도체 소자와 같이 전원이 분리되기 전에는 ESD 스트레스가 가해지는 ESD 재핑(zapping)시 전류 경로(path)가 출력버퍼, 입력버퍼 그리고 모든 주변회로의 CMOS를 통하여 분산되어 ESD 스트레스를 효과적으로 완화시킬 수 있었다. 그러나, 도2의 단면 구조를 갖는 반도체 소자에서는 전원 공급 핀이 다수로 분리되어 특정 핀에 연결된 풀-다운 트랜지스터에만 전력이 집중되므로 하나의 핀에 대한 임피던스(impedance)가 증가하여 ESD 스트레스를 효과적으로 감소시킬 수 없는 문제점이 발생한다.On the other hand, before the power is disconnected, as in the semiconductor device shown in FIG. 1, the current path is distributed through the CMOS of the output buffer, the input buffer and all peripheral circuits during ESD zapping during which ESD stress is applied. Could be effectively alleviated. However, in the semiconductor device having the cross-sectional structure of FIG. 2, since the power supply pins are separated into a plurality, and the power is concentrated only on the pull-down transistors connected to the specific pins, the impedance on one pin increases, effectively reducing the ESD stress. A problem that cannot be made occurs.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 전원이 회로 블록별로 분리되는 반도체 소자에서 ESD 스트레스를 효과적으로 분산시킬 수 있는 반도체 소자를 제공하는데 그 목적이 있다.An object of the present invention is to provide a semiconductor device that can effectively distribute the ESD stress in the semiconductor device in which the power source is separated for each circuit block.

도1은 전원이 분리되지 않은 종래 반도체 메모리 소자의 출력버퍼와 입력버퍼의 구성을 도시한 회로도,1 is a circuit diagram showing the configuration of an output buffer and an input buffer of a conventional semiconductor memory device in which power is not separated;

도2는 전원이 분리된 종래 반도체 소자의 개략적인 단면도,2 is a schematic cross-sectional view of a conventional semiconductor device with the power source separated;

도3은 본 발명의 일실시예에 따른 반도체 소자의 개략적인 단면도.3 is a schematic cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings

Vccdq,: 출력버퍼의 Vcc전원 Vccin,: 입력버퍼의 Vcc전원V ccdq,: V cc power supply for output buffer V ccin,: V cc power supply for input buffer

Vccperi: 주변회로영역 또는 셀영역의 Vcc전원V ccperi : V cc power supply in peripheral circuit area or cell area

n+: 웰-픽업 ISO: 노드분리막n + : Well-pickup ISO: node separator

상기와 같은 목적을 달성하기 위한 본 발명은 다수의 전원 공급 핀(pin)을 갖는 반도체 소자에 있어서, 이웃하는 전원 공급 핀 사이의 반도체 기판에 형성된 제1 도전형의 웰, 상기 웰 표면에 형성되고 제2 도전형을 가지며 이웃하는 전원 공급 핀과 연결되는 다수의 노드(node) 및 이웃하는 상기 노드를 분리하는 노드분리영역으로 이루어져, 소자의 정상 동작시에는 작동하지 않으며 상기 전원 공급 핀을 통하여 ESD(electrostatic discharge)가 가해질 때에 동작하여 이웃하는 전원 공급 핀을 연결하는 기생 쌍극성 트랜지스터(parasitic bipolar transistor)를 포함하는 반도체 소자를 제공한다.The present invention for achieving the above object is a semiconductor device having a plurality of power supply pin (pin), the first conductivity type formed in the semiconductor substrate between the adjacent power supply pin, formed on the well surface It has a second conductivity type and consists of a plurality of nodes connected to neighboring power supply pins and a node isolation region separating the neighboring nodes, which do not operate during normal operation of the device and are ESD through the power supply pins. A semiconductor device including a parasitic bipolar transistor that operates when an electrostatic discharge is applied to connect neighboring power supply pins.

본 발명은 ESD 스트레스가 가해질 때 분리된 전원 공급 핀들을 기생 쌍극성 트랜지스터(parasitic bipolar junction transistor)로써 연결하여 ESD 스트레스를 효과적으로 분산시킬 수 있는 반도체 소자를 제공하는데 그 특징이 있다. 즉, 본 발명은 다수의 전원 공급 핀을 갖는 반도체 소자에서, 이웃하는 전원 공급 핀 사이에 제1 도전형의 웰 및 웰 표면에 형성된 노드분리영역을 사이에 두고 이웃하며 각각이 이웃하는 전원 공급 핀의 웰 픽업과 연결되는 다수 개의 제2 도전형 노드로 이루어져 정상적인 회로 동작에서는 동작하지 않고 ESD 스트레스가 가해질 때만 동작하는 기생 쌍극성 트랜지스터를 형성하여, ESD 스트레스가 가해질 때 전원 공급 핀들을 상호 연결함으로써 ESD 스트레스를 분산시킬 수 있는 반도체 소자를 제공한다.The present invention provides a semiconductor device capable of effectively distributing ESD stress by connecting separated power supply pins as parasitic bipolar transistor transistors when an ESD stress is applied. That is, according to the present invention, in a semiconductor device having a plurality of power supply pins, neighboring power supply pins are adjacent to each other with a first conductivity type well and a node isolation region formed on the surface of the well, and adjacent power supply pins. It consists of a plurality of second conductive nodes connected to the well pickup of the circuit, forming a parasitic bipolar transistor that does not work in normal circuit operation but operates only when ESD stress is applied, thereby interconnecting the power supply pins when ESD stress is applied. Provided is a semiconductor device capable of dispersing stress.

이하, 본 발명의 일실시예에 따른 반도체 소자의 단면도인 도3을 참조하여 본 발명의 일실시예에 따른 반도체 소자를 상세히 설명한다.Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIG. 3, which is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

도3에 도시한 바와 같이 출력버퍼를 이루는 제1 n웰, 입력버퍼를 이루는 제2 n웰 및 주변회로영역 또는 셀영역을 이루는 제3 n웰을 구비하는 반도체 소자에 있어서, 제1 n웰과 제2 n웰 사이에 제1 기생 쌍극성 트랜지스터를 이룰 제4 n웰 및 제4 n웰 표면에 노드분리막(ISO)을 사이에 두고 이웃하는 두 p+ 노드(node)를 형성한다. 또한, 제2 n웰과 제3 n웰 사이에 제2 기생 쌍극성 트랜지스터를 이룰 제5 n웰 및 제5 n웰 표면에 노드분리막(ISO)을 사이에 두고 이웃하는 두 p+ 노드를 형성한다. 도3에서 미설명 도면 부호 Vccdq, Vccin, Vccperi은 출력버퍼, 입력버퍼 및 주변회로영역 또는 셀영역 각각의 Vcc전원 핀을 각각 나타내며, n+는 각각의 웰-픽업(well-pick up)을 나타낸다. 한편, 상기 제4 n웰과 제5 n웰에는 공통으로 전압이 인가될 수도 있다.As shown in FIG. 3, a semiconductor device having a first n well constituting an output buffer, a second n well constituting an input buffer, and a third n well constituting a peripheral circuit region or a cell region, comprising: a first n well; Two neighboring p + nodes are formed on the surface of the fourth n well and the fourth n well to form the first parasitic bipolar transistor between the second n wells with the node isolation layer ISO interposed therebetween. In addition, two neighboring p + nodes are formed between the second n well and the third n well with the node isolation layer ISO interposed therebetween on the surfaces of the fifth n well and the fifth n well to form a second parasitic bipolar transistor. In Figure 3, reference numeral V ccdq, V ccin, V ccperi the output buffer, input buffer, and each of the peripheral circuit region or cell region V cc supply pin indicates the respective, n + are each well-pick-up (well-pick up). Meanwhile, a voltage may be applied to the fourth n well and the fifth n well in common.

도3과 같이 이웃하는 Vcc전원 사이에 기생 쌍극성 트랜지스터를 형성하면, 정상적인 회로 동작에서는 절연막인 노드분리막(ISO)에 의해 각각의 Vcc전원은 분리된다. 그러나, 예를 들어 Vccdq전원 핀과 연결된 패드(pad)를 통하여 ESD 스트레스가 가해지면, 접합 항복(junction break down)과 스냅-백 항복(snap-back breakdown)에 의해, 제4 n웰 및 제4 n웰 표면의 두 p+ 노드로 이루어지는 제1 기생 쌍극성 트랜지스터가 동작하여 Vccdq전원과 분리되었던 Vccin, Vccperi전원이 연결된다. 이와 같은 방법으로 ESD 스트레스가 가해질 때 ESD 전류 경로가 출력버퍼뿐만 아니라 입력버퍼 및 주변회로로 분산될 수 있다. 따라서, ESD 스트레스를 효과적으로 분산시킬 수 있다.If parasitic bipolar transistors are formed between neighboring V cc power supplies as shown in Fig. 3, in normal circuit operation, each V cc power supply is separated by the node isolation film ISO, which is an insulating film. However, if ESD stress is applied through, for example, a pad connected to the V ccdq power pin, the fourth n well and the first by the junction break down and the snap-back breakdown. n 4 is connected to the first parasitic bipolar transistor operates in a V ccdq ccin V, V ccperi power that was separated from the power source consisting of two p + node of the well surface. In this way, when ESD stress is applied, the ESD current path can be distributed to the input buffer and peripheral circuit as well as the output buffer. Therefore, the ESD stress can be effectively distributed.

전술한 본 발명의 일실시예는 제4 n웰 또는 제5 n웰 표면의 두 p+ 노드가 노드분리막(ISO)에 의해 분리되는 경우를 설명하였지만, 노드분리막을 대신하여 게이트 전극을 형성해서 트랜지스터 구조를 이용하여 이웃하는 노드를 분리할 수도 있다. 또한, 본 발명은 Vss전원에도 적용할 수 있으며, 이때 각 웰의 전도형은 도3의 전도형과 반대가 된다. 또한, 본 발명의 일실시예에서는 PNP 기생 쌍극성 트랜지스터의 형성을 예로서 설명하였지만, 제4 n웰 및 제5 n웰을 각각 p웰로 형성하고 각각의 p웰 표면에 n형 노드를 형성하여, NPN 기생 쌍극성 트랜지스터를 형성할 수 있다. 그러나, NPN 기생 쌍극성 트랜지스터의 경우에는 소자의 정상적인 동작에서 p웰이 접지(ground)되어 웰 전압은 낮고, 노드 전압은 높아서 콘택 누설(contact leakage) 및 접합 누설(junction leakage)이 증가하는 것을 고려하여야 한다.Although the above-described embodiment of the present invention has described a case in which two p + nodes on the surface of the fourth n well or the fifth n well are separated by the node isolation layer ISO, a gate electrode is formed in place of the node isolation layer to form a transistor structure. Neighboring nodes can also be separated using. In addition, the present invention can be applied to a V ss power supply, where the conductivity type of each well is opposite to that of FIG. In addition, in the embodiment of the present invention, the formation of the PNP parasitic bipolar transistor has been described as an example, but the fourth n well and the fifth n well are formed as p wells, and n-type nodes are formed on the surface of each p well, NPN parasitic bipolar transistors can be formed. However, in the case of NPN parasitic bipolar transistors, the p well is grounded in the normal operation of the device, so that the well voltage is low and the node voltage is high, so that contact leakage and junction leakage are increased. shall.

상기와 같이 이루어지는 본 발명은 잡음에 대한 내성을 향상시킬 수 있도록 설계된, 전원이 분리된 반도체 소자에서 ESD 스트레스에 의한 전류를 분산시켜 소자의 특성 저하를 방지할 수 있다.The present invention made as described above is designed to improve the resistance to noise, it is possible to prevent the deterioration of the characteristics of the device by distributing the current by the ESD stress in the semiconductor device is separated power.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

Claims (5)

다수의 전원 공급 핀(pin)을 갖는 반도체 소자에 있어서,In a semiconductor device having a plurality of power supply pins, 이웃하는 전원 공급 핀 사이의 반도체 기판에 형성된 제1 도전형의 제1 웰,A first well of a first conductivity type formed in a semiconductor substrate between neighboring power supply pins, 상기 제1 웰 표면에 형성되고 제2 도전형을 가지며 이웃하는 전원 공급 핀과 연결되는 다수의 노드(node) 및A plurality of nodes formed on the surface of the first well and having a second conductivity type and connected to neighboring power supply pins; 이웃하는 상기 노드를 분리하는 노드분리영역으로 이루어져,Node separation area for separating the neighboring node, 소자의 정상 동작시에는 작동하지 않으며 상기 전원 공급 핀을 통하여 ESD(electrostatic discharge)가 가해질 때에 동작하여 이웃하는 전원 공급 핀을 연결하는 기생 쌍극성 트랜지스터(parasitic bipolar transistor)Parasitic bipolar transistors that do not operate during normal operation of the device and operate when an electrostatic discharge (ESD) is applied through the power supply pins to connect neighboring power supply pins. 를 포함하는 반도체 소자.Semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 노드분리영역은,The node isolation region, 절연막으로 이루어지는 것을 특징으로 하는 반도체 소자.A semiconductor device comprising an insulating film. 제 1 항에 있어서,The method of claim 1, 상기 노드분리영역은,The node isolation region, 상기 이웃하는 노드; 및The neighboring node; And 상기 노드 사이에 형성된 게이트 전극을 포함하는 트랜지스터로 이루어지는 것을 특징으로 하는 반도체 소자.And a transistor including a gate electrode formed between the nodes. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 전원 공급 핀은,The power supply pin is 출력버퍼, 입력버퍼, 주변회로 또는 셀영역의 전원 공급 핀인 것을 특징으로 하는 반도체 소자.A semiconductor device, comprising: an output buffer, an input buffer, a peripheral circuit, or a power supply pin of a cell region. 제 4 항에 있어서,The method of claim 4, wherein 상기 전원 공급 핀과 상기 노드는,The power supply pin and the node, 상기 전원 공급 핀과 연결되는 제2 웰 표면에 형성된 도핑 영역을 경유하여 연결되는 것을 특징으로 하는 반도체 소자.And a doped region formed on a surface of a second well connected to the power supply pin.
KR1019980045673A 1998-10-29 1998-10-29 Semiconductor device capable of dispersing current paths by electrostatic discharge KR20000027682A (en)

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