KR20000027277A - Edge test pattern for measuring a junction line capacitance of a semiconductor device and a method therefor - Google Patents

Abstract

PURPOSE: A pattern is provided to reduce a device size and to enable an exact line capacitance to be measured by separating contact hole-formed active regions and contact hole-free active regions. CONSTITUTION: A first gate group has plural gates(22) formed on a semiconductor substrate and isolated to each other. A second gate group are isolated from each other, formed on the substrate, composed of plural gates, and opposite to the first gate group. Plural device isolation layers(20) are formed on the substrate of a lower portion of each gate of the first and second gate groups and isolated from each other. Junction regions are formed between the first and second gate groups and between the gates(22) and gates. Plural contact holes(25) are formed on the contact regions, and a gate connection body(22B).

Description

Edge Test Pattern for Measuring Junction Line Capacitance of Semiconductor Device and Formation Method thereof

The present invention relates to an edge test pattern for measuring a junction line of a semiconductor device and a method of forming the same. In particular, by forming an edge test pattern in consideration of the topology of a junction line in an actual cell region, source line margins are secured and the size of the device is secured. The present invention relates to an edge test pattern for measuring a junction line of a semiconductor device and a method of forming the same.

In memory devices requiring high speed operation, the capacitance of the source and drain lines is a very important variable to be considered when designing a memory device. In particular, a source line formed through a self alignment source (SAS) etching process in an actual cell region has a narrow junction width and has a high topology. However, since the junction area of the conventional edge test pattern is formed flat and the shape of the junction area of the cell area is different from that of the cell area, accurate junction capacitance cannot be measured.

1 is a layout diagram illustrating a method of forming an edge test pattern for measuring junction line capacitance of a conventional semiconductor device.

As shown in the drawing, the conventional edge test pattern has a horizontal shape and is formed flat on the active region 11 divided by the device isolation region 10, and has 100 lines having a width of 2 μm and a length of 200 μm. Dogs have size formed. This edge test pattern is separated from each source line and connected to metal lines through a contact 12.

As described above, the conventional edge test pattern has a width of 2 μm, which is excessively large compared to the width of an actual source line having a width of 0.3 to 0.4 μm. This is the result of setting a junction width of at least 1.5 μm to give sufficient margin with the junction contact gate. In addition, since the conventional edge test pattern forms a junction using only the active region 11, a junction region having a flat shape is formed. However, the junction region formed in the actual cell region has a severe topology, and thus the junction region of the test pattern and the junction region of the cell region have different shapes. Accordingly, there is a problem in that the junction line capacitance of the cell region and the junction line capacitance of the edge test pattern have different values, so that accurate junction line capacitance cannot be measured.

Accordingly, the present invention forms an edge test pattern for measuring the junction line capacitance in consideration of the topology of the junction line in the actual cell region, thereby reducing the size of the device while ensuring margins of the source and drain lines, and operating speed of the device. It is an object of the present invention to provide an edge test pattern and a method for forming the junction line capacitance of a semiconductor device capable of measuring the junction line capacitance and improving the accuracy thereof.

The edge test pattern for measuring the junction line capacitance of the semiconductor device according to the present invention for achieving the above object is formed on the substrate spaced apart from each other and a first gate group consisting of a plurality of gates, and spaced apart from each other on the substrate A second gate group formed of a plurality of gates to face the first gate group, a plurality of device isolation layers formed on the substrate under each gate of the first and second gate groups, and spaced apart from each other; A junction region formed between the first gate group and the second gate group and between the gate and the gate, a plurality of contact holes formed on the junction region between the first gate group and the second gate group, and the first region And a gate connector surrounding the second gate group and connected to the gate. And that is characterized.

In addition, the edge test pattern forming method for measuring the junction line capacitance of the semiconductor device according to the present invention for achieving the above object is to perform a device isolation process on the silicon substrate to define the device isolation region and the active region, the overall structure Forming a plurality of gate groups and gate connectors surrounding the gate groups and connected to each gate, performing an etching process using a self-aligned source etching mask, and performing an ion implantation process Forming a junction region, forming an interlayer insulating film over the entire structure, and forming a contact hole in the junction region between the gate groups.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a layout diagram illustrating a method for forming an edge test pattern for measuring junction line capacitance of a conventional semiconductor device.

2 (a) to 2 (d) are layout views illustrating edge test patterns for measuring capacitance of a junction line in a semiconductor device according to a first embodiment of the present invention.

3 (a) to 3 (c) are cross-sectional views of the parts of FIG. 2 (d) taken away;

4 is a layout diagram illustrating an edge test pattern for measuring capacitance of a junction line of a semiconductor device according to a second exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 20, 30: device isolation region 11, 21A, 21B: active region

22, 31: gate

23: overlapping portion of the gate and active region

24: Self-aligned source etching mask

25: contact hall

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) to 2 (d) are layout views illustrating edge test patterns for measuring capacitance of a junction line of a semiconductor device according to a first embodiment of the present invention, and FIG. 3 is a diagram illustrating FIGS. 3 (c) is a sectional view of the state in which the respective portions of FIG. 2 (d) are cut out.

As shown in FIG. 2A, the device isolation process is performed to define the device isolation region 20 and the active regions 21A and 21B on the silicon substrate (1 of FIG. 3). In this case, in order to solve the problem that the width of the junction line formed in the edge test pattern is wider than the source line of the cell region, the contact hole is formed only in the specific active region 21B. The width of the active region 21A where no contact holes are formed is set to 0.2 to 0.5 µm, and the width of the active region 21B where the contact holes are formed is set to 1 µm. In addition, the active regions 21A and 21B having such widths include four lines of the active region 21A in which contact holes are not formed, one line in the active region 21B in which the contact holes are to be formed, and an active region in which the contact holes are not formed. 21A) Repeatedly formed in the order of 8 lines, the size of the entire active area 21A, 21B is 200 ~ 200㎛. The interval between the active regions 21A and 21B is 0.5 to 0.55 탆.

As shown in FIG. 2 (b), a gate 22 including a finger gate 22A group and a gate connector 22B surrounding and connecting the finger gate 22A group is formed on the entire structure. Form. At this time, the finger gate 22A is perpendicular to the junction region 21A, and the gate 22 is not formed on the junction region 21B where the contact hole is to be formed. Here, the gate 22 has an oxide / tungsten silicide / oxide structure, and must act as a protective film in a subsequent self align source etch (SAS etch), so the gate 22 must be formed at a portion that will not form a junction. ) Should be formed. In order to prevent the edge portion of the gate connector 22B from being rounded, the side portions of the active regions 21A and 21B are overlapped with the gate 22 by about 0.1 to 0.2 탆 (23 portions).

As shown in FIG. 2C, an etching process using the SAS etching mask 24 is performed. The region to which the SAS etching process is applied has an inner portion of the gate connector 22B about 0.2 μm. By the SAS etching process, the oxide film and the device isolation film 20 on the tungsten silicide layer forming the gate 22 are removed. That is, the portion where the gate 22 is not formed (between the finger-type gates) is divided into a plurality of active regions 21A and field regions 20. When the SAS etching process is performed, the gate 22 is covered. Since the device isolation film 20 of the portion that is not secured is removed and the silicon substrate is exposed, the same topology as that of the junction region of the actual cell region can be obtained. Thereafter, an ion implantation process is performed to form a finger junction line.

As shown in FIG. 2 (d), after forming an interlayer insulating film (not shown) on the entire structure, a plurality of contact holes 25 are formed on the active region 21B. (A) is sectional drawing of the state which cut | disconnected XX 'part of FIG. 2 (d), FIG. 3 (b) is sectional drawing of the state which cut | disconnected YY' part of FIG. ) Is a cross-sectional view of the ZZ 'portion of FIG. 2 (d) taken away. In the portion covered by the gate 22, that is, the portion in which the junction is not formed, the device isolation film 20 remains as it is, but the device isolation film between the finger gates 22A is removed by a SAS etching process so that the actual cell region is removed. It has the same topology as the topology of the junction line (part 21C).

The edge test pattern formed as described above is perpendicular to the junction line 21B on which the contact hole 25 is formed and the junction line 21A on which the contact hole is not formed, and all of the junction lines in the test pattern are connected. do.

4 is a layout diagram illustrating an edge test pattern for measuring capacitance of a junction line of a semiconductor device according to a second exemplary embodiment of the present invention.

After defining the field region 30 and the active region on the substrate, the gate 32 is formed. The gate 32 used herein uses a finger gate that is perpendicular to the active region. In particular, a gate having a shape in which upper and lower fingers are crossed with each other is used. Thereafter, an ion implantation process is performed to form the junction region 31 and to form the contact hole 33 in the selected portion of the junction region 31. This edge test pattern has the same topology as the cell region, and can be used to check whether the junction is bridged between the junctions.

As described above, according to the present invention, the size of the device can be reduced by forming the active region in which the contact hole is formed and the active region in which the contact hole is not formed. In addition, by forming a junction region using a gate having a finger perpendicular to the junction region, it is possible to have the same topology as that generated in the cell region, thereby making it possible to accurately measure the junction line capacitance. In the case where the gate fingers are used to cross test patterns, it is possible to check whether the junctions are bridged between the junctions.

Claims (5)

A first gate group formed on the substrate and spaced apart from each other, the first gate group comprising a plurality of gates, A second gate group formed on the substrate to be spaced apart from each other and formed of a plurality of gates to face the first gate group; A plurality of device isolation layers formed on the substrate under each gate of the first and second gate groups to be spaced apart from each other; A junction region formed between the first gate group and the second gate group and between the gate and the gate; A plurality of contact holes formed on the junction region between the first gate group and the second gate group; Edge test pattern for measuring the junction line capacitance of a semiconductor device, characterized in that it comprises a gate connector surrounding the first and second gate group and connected to the gate. The method of claim 1, An edge test pattern for measuring capacitance of a junction line of a semiconductor device, wherein the junction region between the gate and the gate is formed in an uneven shape. Performing a device isolation process on the silicon substrate to define device isolation regions and active regions; Forming a plurality of gate groups and gate connectors surrounding the gate groups and connected to the respective gates on the entire structure; Performing an etching process using a self-aligned source etching mask, Performing an ion implantation process to form a junction region, Forming an interlayer insulating film over the entire structure; And forming a contact hole in the junction region between the gate groups. The method of claim 3, wherein The active region is formed of a plurality of active lines formed at intervals of 0.5 to 0.55㎛, a plurality of active lines having a width of 0.2 to 0.5㎛, an active line having a width of 1㎛ and having a width of 0.2 to 0.5㎛ An edge test pattern for measuring capacitance of a junction line of a semiconductor device, characterized in that a plurality of active lines are sequentially formed. The method of claim 3, wherein An edge test pattern for measuring capacitance of a junction line of a semiconductor device, wherein the junction region between the gate and the gate is formed in an uneven shape.