KR20000025609A - Cash structure having changeable line size - Google Patents

Abstract

PURPOSE: A cash structure with the changeable line size is provided to effectively obtain maximum hit ratio under any program by changing the line size according to the space or the time characteristic of the program. CONSTITUTION: A cash structure comprises a line size controlling part(100), a tag register(101, 102), a comparing part(103, 108), a register(104), a shift register(105, 106), a subtracting and adding part(107), a n and gate(NAND1), and an and gate(AND1). The tag register(101, 102) memorizes and shifts the cash address which is sequentially accessed from the tag memory(30). the comparing part(103) compares the tag stored at the tag register(102, 101). The register(104) stores the number of cash which synchronizes with the latch enable signal. The shift register(105, 106) stores the cash miss signal occurring at the cash controller. After passing through the NAND gate(104) and adding part, the information stored in the register(104) is compared at the comparing part. The comparing part outputs line size signal to cash controller.

Description

Cache structure with variable line size

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache structure having a variable line size. In particular, the present invention relates to a variable line size for determining an effective line size according to a time or a characteristic of an executed application. The branch is about the cache structure.

The conventional cache structure consists of a tag memory, a cache memory, and a cache controller. Here, tag memory is used to see if CPI is sending an address to read main memory, and the contents of main memory are copied to the cache at the same time, and the next time the same address is called, the corresponding cache is read and the same address is referenced. Memory for storing the address value to know.

The cache controller also fetches the contents of the memory location in the case of cache misses and logic for comparing the tag field (tag_field) of the requested memory address with the tag value output from the tag memory. To store it in the cache memory, and the cache memory uses RAM that is relatively faster than the memory used as the main memory, and stores the command processed by CPI there and reads the command again. Speed up processing by reading cache rather than main memory.

On the other hand, when the data is read from the memory at the time of cache miss, the line size reads not only the data requested by CPI but also a fixed size memory block including the data. Spatial locality (hereinafter, referred to as spatial characteristics) exhibits a high hit ratio for large data accesses.

In addition, in case of data access having a large temporal locality (temporal locality), as the cache size increases, there is a high possibility that a cache miss frequently occurs at the same line size. set associative) cache structure.

On the other hand, when the cache size is constant, a large line size indicates a high hit rate in a data access having a large spatial characteristic, and a small line size shows a high hit rate in a data access having a large temporal characteristic.

Therefore, when designing a cache structure, the general data access pattern of the system is observed in advance to determine the optimal line size. However, the data access pattern of the running application is different for each application, so the determined line size may not be optimal for all applications.

As described above, in the conventional technology, the cache line size is fixed, and the cache rate of the cache is changed according to the characteristics of the application. In particular, an application having a large spatial characteristic causes frequent cache misses. there was.

Therefore, the present invention was created to solve the above-mentioned conventional problems. The line size is changed according to the temporal and spatial characteristics of the application program to be executed so that the optimal bit rate can be obtained by executing any program. The purpose is to provide a cache structure having a variable line size.

1 is a schematic block diagram showing a cache structure having a variable line size according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

100: line size control unit 101,102: tag register

103: comparison unit 104: register

105,106: shift register 107: addition / subtraction part

108: comparison unit XOR1: exclusive ora gate

AND1: AND gate NAND1: NAND gate

The configuration of the present invention for achieving the above object, in the cache structure consisting of a cache controller, a cache memory and a tag memory, further comprises a line size control unit for determining whether a continuous cache miss occurs to change the line size of the cache It is achieved by the configuration including, when described in detail with reference to the accompanying drawings an embodiment according to the present invention.

1 is a schematic block diagram showing a cache structure having a variable line size according to the present invention. As shown in FIG. 1, a cache structure including a cache controller 10, a cache memory 20, and a tag memory 30 is illustrated. It further comprises a line size control unit 100 for determining a continuous cache miss occurs to change the line size of the cache.

Here, the line size control unit (100) includes a tag register (101, 102) for storing and shifting a tag of a cache address continuously accessed from the tag memory (30); A comparison unit (103) and an exclusive OR gate (XOR1) for comparing the tags stored in the tag registers (101, 102) with each other; An AND gate AND1 for outputting the latch enable signal LE by AND combining the output of the comparison unit 103 and the exclusive OR gate XOR1; A register (104) for storing the number of consecutive cache misses in synchronization with the latch enable signal; Shift registers 105 and 106 for storing a cache miss signal MISS generated in the cache controller 10; A NAND gate NAND1 for NAND combining the shift registers 105 and 106 to output an add / subtract signal A / S; An addition / subtraction unit 107 for adding or subtracting 1 to the value of the register 104 according to the addition / subtraction signal A / S output from the NAND gate NAND1; A comparator for outputting a line size signal LS to the cache controller 10 by comparing the contents stored in the register 104 to an arbitrary upper threshold value (UT: Upper Threshold) and a lower threshold value (LT: Lower Threshold). The operation and operation of the present invention configured as described above, which is constituted by 108, will be described.

Once the CAPI 40 requests the cache controller 10 for the address of the memory to be processed, the cache controller 10 accesses the cache memory 20 and the corresponding tag memory 30 by this request. The address is loaded onto the address bus.

Accordingly, the tag memory 30 outputs the address requested by the cache controller 10 to the tag bus, and the cache controller 10 displays the contents of the tag bus and the tag field of the memory address requested by the CPI 40. In comparison, the hit / miss of the cache is determined, and when the cache is missed, the cache miss signal MISS is output.

In addition, tags output from the tag memory 30 are sequentially latched and shifted in the tag registers 101 and 102 to store tags for memory blocks continuously accessed.

Accordingly, the comparison unit 103 compares the contents except the least significant bits of the tag registers 101 and 102 and outputs 1 when they are the same. In contrast, the exclusive OR gate XOR1 compares only the least significant bits of the tag registers 101 and 102. If they are different from each other, a 1 is output. In the AND gate AND1, the tag address portion of the memory block address consecutively accessed by AND combining the outputs becomes 1 when the upper bits are the same but the least significant bits are different, and the latch enable signal LE ) Will be printed.

Meanwhile, the shift registers 105 and 106 receive a cache miss signal MISS from the cache controller 10 and latch and shift the shift registers 105 and 106 to store consecutive cache miss histories. When the contents are all '1', that is, a continuous cache miss occurs, the output of the NAND gate NAND1 becomes an addition signal to 0 and adds '1' to the input.

However, when the contents of the shift registers 105 and 106 are all '0', that is, a non-consecutive cache miss occurs, the output of the NAND gate becomes a subtraction signal of 1, and the result of subtracting '1' from the input is output. Done.

Accordingly, the output of the add / subtract unit 107 is stored in the register 104 at the point where the latch enable signal LE is output.

That is, the contents of register 104 are incremented by one for successive cache misses and decremented by one when memory access is made to adjacent memory blocks.

Therefore, the comparing unit 108 compares whether the value of the register 104 is outside the range of any upper reference value UT and lower reference value LT, and when the value is larger than the upper reference value, the line size signal of '1' ( LS) outputs a line size signal LS of '0' when the reference value is smaller than the lower reference value, and the cache controller 10 receiving the line size signal LS operates in a different line size in each case. In other cases, it keeps the past line size.

That is, when a cache miss occurs, the cache controller 10 loads the miss memory block from the main memory (not shown), and this transmission unit becomes one cache line so that the line size signal LS If 0, the cache controller 10 loads only one cache line from the memory in a conventional manner. If the line size signal LS is 1, the cache controller 10 reads the next memory block continuously with the corresponding cached cache line. And save it.

Therefore, the size of the block loaded from the memory is doubled without changing the structure of the cache itself, resulting in an increase in the line size of the cache.

As described above, the cache structure having the variable line size according to the present invention has the effect of changing the line size according to the temporal and spatial characteristics of the application program to be executed to obtain an optimal hit rate even when executing any program.

Claims (2)

In the cache structure consisting of a cache controller, a cache memory and a tag memory, the variable line size further comprises a line size control unit 100 for determining whether a continuous cache miss occurs and changing the line size of the cache. Cache structure with 2. The apparatus of claim 1, wherein the line size control unit comprises: a tag register (101, 102) for storing and shifting a tag of a cache address continuously accessed from a tag memory; A comparison unit (103) and an exclusive ora gate for comparing tags stored in the tag register with each other; An AND gate outputting a latch enable signal LE by AND combining the output of the exclusive OR gate with the comparator 103; A register (104) for storing the number of consecutive cache misses in synchronization with the latch enable signal; Shift registers 105 and 106 for storing a cache miss signal MISS generated at the cache controller; A NAND gate outputting an addition / subtraction signal A / S by NAND combining the shift registers; An addition / subtraction unit for adding or subtracting 1 to the value of the register 104 according to the addition / subtraction signal A / S output from the NAND gate; A cache having a variable line size, comprising: a comparator 108 for outputting a line size signal LS to a cache controller by comparing the contents stored in the register 104 with an arbitrary upper reference value and a lower reference value rescue.