KR20000025598A - Method for testing switch in asynchronous transfer mode exchange - Google Patents

Abstract

PURPOSE: A method for testing a switch in an asynchronous transfer mode exchange is provided to test a function in a biggest capacity which an ATM cell test board assembly when testing a path within a switch. CONSTITUTION: A method for testing a switch in an asynchronous transfer mode exchange includes a first through third steps. The first step is to test a unit path according to a path test port for testing a switch in an asynchronous transfer mode exchange by linking an arc processing block, a subscriber/trunk line access block for an asynchronous transfer mode exchange. The second step is to test a local path. The third step is to test a global path.

Description

METHOD FOR TESTING SWITCH IN ASYNCHRONOUS TRANSFER MODE SWITCH

The present invention relates to a switch test method in an asynchronous transfer mode (ATM) exchange, and in particular, the basic path test, the local path test, the global path test according to the location of the path test target port in the out of service state. A switch test method in an asynchronous transfer mode (ATM) exchange in conjunction with a processing block, a subscriber / relay line matching block, and a test device.

In general, the association setup for cell path testing of ATM switching systems is largely set between switches and subscribers, between switches and switches, processors and switches, and ATM cells in each ATM Local Switching Subsystem (ALS). A test cell is generated through the test board.

The ATM cell test apparatus analyzes the returned test cell and informs the operator. The path test cell is generated by a test device in each ATM local switching subsystem (ALS), which analyzes the test cell returned via the path. do.

Functional Path Test (Functional Path Test) is possible to the Connection Test (Connection Test) and Performance Test (Performance Test), the Connection Test (Connection Test) can be confirmed through one cell test (One cell test), The performance test can be confirmed through a bandwidth cell test at a constant bit rate (CBR).

1 is a system configuration diagram showing the structure of an ATM switching system. In the ATM switch architecture, the testable path and the location of each device and switch are indicated.

The structure of the ATM switching system includes a central switch (CSW) 210 and an operating and maintenance processor (OMP) 220 within an ATM Central Switching Subsystem (ACS) 200. ATM Local Switching Subsystem (ALS) 300 includes: an access switch (ASW) 311, interface modules 312 and 313, and call connection control. It consists of a processor (CCP) and a call cell connection board assembly (ACTA) 319.

The operator terminal 100 is connected to the ATM Central Switching Subsystem (ACS) 200 equipped with an ATM card and having a switch structure of 64x64 or 256x256 with an Ethernet cable. ACS) 200 is comprised of a plurality of said ATM local switching subsystems (ALS) 300.

When the ATM central switching subsystem (ACS) 200 has a 64x64 switch structure, up to eight ATM local switching subsystems (ALS) 310 of a 32x32 switch structure may be connected, and the ATM central switching subsystem ( If the ACS) 200 has a 256x256 switch structure, up to 32 ATM local switching subsystems (ALS) 310 of 32x32 switch structure can be connected and a user-network interface (UNI) and a connection between the exchange and the exchange. Used in conjunction with the Network-Network Interface (NNI).

The path test execution configuration shown in FIG. 2 illustrates the interaction between the upper software and the ATM cell test board (ACTA) 319 firmware for operating the same in the structure shown in FIG. Display.

In the path test, the band allocation is performed by the ATM Central Switching System (ACS), the Interface Test (IM), the Global Test (IM), and the Interface Module (IM) Band Assignment. And a local test that performs a return function, an ATM Central Switching Subsystem (ACS), and a unit test that performs interface module (IM) band allocation and return.

Performance measurements on current switch paths or ports using a test cell for all paths through which a user cell can flow in an asynchronous transfer mode (ATM) exchange have not been available. Since performance was measured in the In Service state, link band allocation for each interface module type (IM type), which is a subscriber board, was large, and a criterion for performance determination was unclear because user cells flowed together.

The cell path test can only test limited capacity in the maximum band of each link, but since the actual link through which the test cell flows is looped back at the interface module level, which is the subscriber board, the link type It is not necessary to be affected by the type, and only the switch path test within the switch should be performed at the maximum capacity that an ATM Cell Test Board Assembly (ACTA) PBA can generate. Because it is a path test for the ATM local switching subsystem (ALS), the constraints that are affected by the interface module should be minimized.

However, depending on the Interface Module Type, only the limited capacity (2M / 45M / 155M: DS1E / DS3 / STM-1) in the maximum bandwidth of each link can be tested and the user cell in service If this flows, there is a problem that it is difficult to accurately measure the test cell.

The present invention has been proposed to solve the above problems, and an object of the present invention is to test only a limited capacity in the maximum band of each link, but the link through which the test cell flows is interface module level (Interface). At the module level, the switch test method is used in an asynchronous transfer mode (ATM) exchange to perform performance tests with the maximum capacity that an ATM cell test board assembly (ACTA) can generate if only a path test is performed within the switch. to provide.

In order to achieve the above object, the present invention provides a switch test in an asynchronous transfer mode (ATM) exchange, the asynchronous transfer mode (ATM) exchange in conjunction with the call processing block, subscriber / relay line matching block, the test apparatus A basic path test step according to a location of a path test target port; Local path testing step; And it provides a switch test method in the asynchronous transmission mode switch, characterized in that it comprises a global path test step.

1 is a system configuration diagram showing the structure of an ATM switching system;

2 is a path test execution block diagram;

3 is a block diagram of a path test function assignment according to the present invention;

4 is a block diagram illustrating a path test to an interface module IM associated with USER_PORT in a single ATM local switching subsystem ALS;

FIG. 5 is a block diagram illustrating a cell path test to a central switch (CSW) in an ATM central switching subsystem (ACS) connected to an ACS_PORT in a single ATM local switching subsystem (ALS).

6 is a block diagram illustrating an IPC cell path test in an ATM local switching subsystem (ALS).

7 is a block diagram illustrating inter-IMS cell path tests within the same ATM local switching subsystem (ALS).

8 is a block diagram of a cell path test between a call connection control processor (CCCP) and an interface module (IM) in another ATM local switching subsystem (ALS).

9 is a block diagram illustrating cell path tests between interface modules IM in different ATM local switching subsystems (ALS).

* Description of the symbols for the main parts of the drawings *

100: operator terminal

200: ATM Central Switching Subsystem (ACS)

210: central switch (CSW)

220: Operating and Maintenance Processor (OMP)

221: Switch Path Test Management Block (SPMF)

300: ATM Local Switching Subsystem (ALS)

311, 361: access switch (ASW)

312, 313: Interface Module

314: Call and Connection Control Processor (CCCP)

315: Switch Path Test Handling Block (SPTF)

316: library on maintenance in ALS (LIBMLF)

317: Subscriber Interface Module (SIM) / Trunk

Trunk Interface Module (TIM)

318: Interface Module Controller (IMC)

319: ATM Cell Test Board Assembly (ACTA)

390: UNI Link Resource Handling Function (ULRHF) / NNI Link Resource Handling Function (NLRHF) / Switch Link Resource Handling Function (SLRHF)

321, 331, 360: Interface Module

330: Cell Mux / Demux board Assembly (CMDA)

UNI: User Network Interface

NNI: Network Network Interface

LSIH: 1.544 Mbps (DS-1) low speed subscriber interface hardware block

(Low-rate Subscriber Interface Hardware Block)

LSIM: 1.544 Mbps (DS-1) Low Speed Subscriber Interface Module

Low-rate Subscriber Interface Module

MSIH: 44.736 Mbps (DS-3) medium speed subscriber interface hardware block

(Medium-rate Subscriber Interface Hardware Block)

MSI: 44.736 Mbps (DS-3) medium speed subscriber interface module

(Medium-rate Subscriber Interface Module)

BSIM: 155 Mbps (STM-1) Base Rate Subscriber Interface Module

(Basic-rate Subscriber Interface Module)

BSIH: 155 Mbps (STM-1) native rate subscriber interface hardware block

(Basic-rate Subscriber Interface Hardware Block)

BTIM: 155 Mbps (STM-1) native speed trunk interface module

(Basic-rate Trunk Interface Module)

BTIH: 155 Mbps (STM-1) native speed trunk interface hardware block

(Basic-rate Trunk Interface Hardware Block)

HTIM: 622Mbps (STM-4) High Speed Trunk Interface Module

(High-speed Trunk Interface Module)

HTIH: 622Mbps (STM-4) High Speed Trunk Interface Hardware Block

(High-speed Trunk Interface Hardware Block)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Functional Path Test (Functional Path Test) can be a connection test (Connection Test) and Performance Test (Performance Test), the performance test is divided into INS (In service) / OOS (Out of service) to subdivide the function.

The Out of Service (OOS) performance test, which is not provided with the service, is a newly added performance test, and is an ATM cell test board assembly (ACTA) 319 regardless of the interface module type (IM type: 2M, 45M, 155M). Test is possible with the maximum bandwidth that can occur.It is mainly used when testing the performance of interface module because the service error rate is high when the board is replaced due to a failure during expansion.

The INS (In Service) performance test is a test corresponding to a conventional cell path test, which should not affect the serviced port, and can only test depending on the interface type (IM type). If the port is in service, only the remaining bands can be tested and used to check the operation of a particular interface module (IM) or port during service.

The connection test is a test regardless of in service / out of service (INS / OOS) and is measured through a one cell test. Since only one cell is used, this can be done at any time without significant loss of bandwidth.

3 is a block diagram of the path test function assignment according to the present invention.

The path test function performs switch path tests of ATM switching systems in conjunction with call processing blocks, subscriber / relay line matching blocks, and test equipment. Path tests can be divided into connection and performance test, path test history output, and path test stop.

The path test such as basic path test, local path test and global path test in an asynchronous transfer mode (ATM) exchange is performed by dividing the switch path of the ATM switching system as follows.

<Basic Path Test>

O Test path to interface module (IM) connected to USER_PORT in a single ATM local switching subsystem (ALS)

O Test path to the central switch (CSW) connected to ACS_PORT in a single ATM local switching subsystem (ALS).

O Tests the path to the call connection control processor (CCCP) associated with IPC_PORT within a single ATM local switching subsystem (ALS).

<Local path test>

O Path test between interface module (IM) and interface module (IM) in a single ATM local switching subsystem (ALS)

<Global Path Test>

O A path test between a call connection control processor (CCCP) in any ATM local switching subsystem (ALS) and an interface module (IM) in another ATM local switching subsystem (ALS).

O A path test between an interface module (IM) in any ATM local switching subsystem (ALS) and an interface module (IM) in another ATM local switching subsystem (ALS).

Referring to FIG. 3, a switch path test handling block (SPMF) in the operator terminal 100 may be a unit path test or a local path test according to a test path. ), Enter the Man-Machine Command (MMC) commands (TEST-UNIT-PATH, TEST-LOCA-PATH, and TEST-GLOB-PATH) of the Global Path Test.

The switch path test handling block (SPMF) 221 receives the Man Machine Command (MMC) command and switches a switch path test management block (SPTF) in a call connection control processor (CCCP) 314 (315). ), A signal (I_MmcGlobPathTestReq) requesting to perform a global path test corresponding to each path test, a signal (I_MmcLocaPathTestReq) requiring a local path test, and a signal (I_MmcUnitPathTestReq) requiring a basic path test are transmitted.

The UNI Link / NNI Link / Switch Link Resource Control Function (ULRHF / NLRHF / SLRHF) is received from the switch path test control block (SPTF) 315 by receiving the path test request signal into the call connection control processor (CCCP) 314. 317 calls the UNI link resource control function block (ULRHF), the NNI link resource control function block (NLRHF), and the library for allocating and releasing bands for the switch port.

The library calls the library L_SPC_ResoAlloc requesting band allocation and the library L_SPC_ResoDealloc requesting release of the allocated band to the UNI link resource control function block ULRHF, and the NNI link resource control function block NLRHF. Call library (L_PathTestRQ) that requires band allocation and library (L_PathTestDel) that requires release of allocated bands, and call library (L_TestPathSel) that requires band allocation for switch ports, and L_TestPathRel) is called.

Allocating and releasing bands in the UNI Link / NNI Link / Switch Link Resource Conditioning Function (ULRHF / NLRHF / SLRHF) 317 and then allocating and releasing bands of the library to the Switch Path Test Control Block (SPTF) 315. Gives the result (OK / NOK).

The switch path test control block (SPTF) 315 is an interface module controller (IM Controller) 318 in the interface module (IM) 320 to virtually loopback at the start of the path test in accordance with the start / end of the path. Virtual channel identifier (VPI / VCI), routing tag information (I_TestCellLoopBackInfo) and the virtual path identifier / virtual channel identifier (VPI / VCI), routing tag (Routing Tag) to terminate loopback at the end of a path test A signal (I_TestCellLoopBackEnd) for transmitting the information of the interface module controller 318 is transmitted.

The interface module controller 318 is a switch path test control block (SPTF) 315 to the virtual path identifier / virtual channel identifier (VPI / VCI), routing tag (Routing Tag) information to loop back at the start of the path test A response signal (N_LoopBackInfoAck) of (I_TestCellLoopBackInfo) and a response signal (N_LoopBackEndAck) of information of the virtual path identifier / virtual channel identifier (VPI / VCI) and routing tag (Routing Tag) are provided to end the loopback when the path test ends.

The ATM cell test board assembly (ACTA) in a Library on Maintenance in ALS (LIBMLF) in an ATM Local Switching Subsystem (ALS), which is a library that receives the response signal to signal the beginning and end of a path test and receives a result upon termination In step 319, a path test start notification signal I_PathTestStart and a signal I_PathTestStopReq requesting to stop the path test under test are transmitted according to the path start / stop.

Response signal (N_PathTestAck) and path test for a path test start notification according to a path start / stop from the ATM cell test board assembly (ACTA) 319 to the maintenance library board LIBMLF in the ATM local switching subsystem ALS. A response signal (N_PathTestStopAck) for the stop request is transmitted, and a signal (N_PathTestRslt) for the result value tested at the end of the path test is transmitted.

A signal (N_MmcGlobPathTestRslt) for transmitting a result value of performing a global path test according to a test path from the switch path test management block (SPTF) 315 to the switch path test handling block (SPMF) 221, and a local path test. It transmits a signal (N_MmcLocaPathTestRslt) that transmits the result value, and a signal (N_MmcUnitPathTestRslt) that transmits the result value of the basic path test.

In addition, the path test at each exchange may be stopped during the test, and the content of the path test currently being performed may be output as shown in Table 1.

First, the term definitions shown in Table 1 are briefly described.

The Low-rate Subscriber Interface Hardware Block (LSIH) is the remaining subscriber board hardware that does not include an Interface Module Controller (IM Controller). The Low-rate Subscriber Interface Module (LSIM) is 1.544. Subscriber interface interface module including Mbit / s (DS1 grade) interface module controller (IM Controller).

The Switch Path Test Management Block (SPTF) and Switch Path Test Handling Block (SPMF) are described in Table 1.

The medium-rate subscriber interface module (MSIM) is a subscriber interface module of 44.736 Mbit / s (DS3 grade) including an interface module controller (IM Controller).

Basic-rate Subscriber Interface Hardware Block (BSIH) is a 155 Mbit / s (STM-1) subscriber hardware board that does not include an Interface Module Controller (IM Controller). Basic Rate Subscriber Interface Module (BSIM) is a subscriber hardware module of 155 Mbit / s (STM-1) including an Interface Module Controller.

Basic-rate Trunk Interface Hardware Block (BTIH) is 155 Mbit / s (STM-1) trunk board hardware without the Interface Module Controller (IM Controller). Basic-rate trunk interface module (BTIM) is a trunk interface module of 155 Mbit / s (STM-1 level) including an interface module controller (IM Controller).

High-speed Trunk Interface Hardware Block (HTIH) is 622 Mbit / s (STM-4 class) trunk board hardware without the Interface Module Controller (IM Controller). The module (HTIM: High-speed Trunk Interface Module) is a 622 Mbit / s (STM-4 class) trunk interface module including an interface module controller (IM Controller).

The UNI Link Resource Handling Function (ULRHF) is a local-band related band library, that is, a basic speed (155 Mbps: STM-1) subscriber interface module (BSIM) or a medium speed (44.736 Mbps: DS-3) subscriber. The interface module (MSIM) and the low speed (1.544 Mbps: DS-1) subscriber interface module (LSIM) call this library to perform band management during path tests.

A Call and Connection Control Processor (CCCP) is a processor that is mounted in an ATM local switching subsystem (ALS) in an ATM switch and performs call connection control.

Subscriber Interface Module (SIM) refers to all subscriber boards in its entirety, and Trunk Interface Module (TIM) refers to all trunk boards.

The NNI Link Resource Handling Function (NLRHF) calls the library when the path is tested with the relay call-related band management library, that is, the 155 Mbps basic speed trunk interface module (BTIM) or 622 Mbps high speed trunk interface module (HTIM). Band Link Management is performed, and the Switch Link Resource Handling Function (SLRHF) calls this library when testing the global path during the ACS_PORT test of the ACS switch port band management library. Band management is performed, and ATM Cell Test Board Assembly (ACTA) is a board that generates test cells and analyzes the returned test cells.

Function Block Name location detail of fuction LSIH LSIM It is located in LSIM and performs loopback by modifying test cell that enters LSIM according to routing information sent by SPTF. MSIM Located in MSIM, it performs loopback by modifying test cell that enters MSIM according to routing information sent by SPTF. BSIH BSIM It is located in BSIM and performs loopback by modifying test cell coming into BSIM according to routing information sent by SPTF. BTIH BTIM Located in BTIM, it performs loopback by modifying test cell that enters BTIM according to routing information sent by SPTF. HTIH HTIM Located in HTIM, it performs loopback by modifying test cell that enters HTIM according to routing information sent by SPTF. ULRHF CCCP One of the libraries that performs the call control function, located in CCCP, performs the function of allocating / releasing the bidirectional band for the port connected to the SIM among the path test targets. NLPHF CCCP One of the libraries that perform call control function, located in CCCP, performs the function of allocating / releasing the bidirectional band for the port connected to the TIM among the path test targets. SLRHF CCCP It is located in CCCP as one of the libraries that perform call control and performs the function of deallocating the bidirectional band for the port connected to CSW among the path test targets. ACTA Generates a path test cell and analyzes the test cells that have passed through the test path, and measures the number of test cells received, the number of received cells, the number of error cells, the number of lost cells, the number of duplicated cells, and the cell transmission delay time. SPMF OMP Located in OMP, it receives the path test MMC command input from the operator, requests the path test processing to the SPTF, and outputs the path test result sent from the SPTF to the operator. SPTF CCCP Located in CCCP, the bandwidth required for the path test is allocated to the call processing block according to the path test requirements required by the SPMF, the IM controller notifies the routing information, and the routing information of the test cell, the number of test cells, and the test to the test device. It performs the function of processing the actual test progress by notifying the information necessary for the test such as the progress time

The path test target is divided into basic path test, local path test, and global path test according to the location of the target port, and the current path test can be stopped and the current progress can be output by performing the path test history output function. .

4 is a schematic diagram illustrating a path test to an interface module IM associated with USER_PORT in a single ATM local switching subsystem (ALS).

Routing tag attached to the test device Routing tag attached by IM Routing_tag_1: bittype (port number associated with IM) Routing_tag_1: bittype (port number connected with test device) Routing_tag_2: bittype (0) Routing_tag_2: bittype (0) Routing_tag_3: bittype (0) Routing_tag_3: bittype (0)

The operator requires a path test to the interface module (IM) associated with the USER_PORT in a single ATM local switching subsystem (ALS) 310, so that the path test function in the call connection control processor (CCCP) can be routed to the call processing block. Requires allocation in both directions with the required bandwidth.

When the band is allocated, the interface module controller (IM Controller) receives routing information and notifies routing information so that a test cell can be looped back, and a path test function in the call connection control processor (CCCP) is a test device (ATM cell test board). Test cell generation (Assembly: ACTA: 319).

The test apparatus generates a test cell and transmits the cell to a corresponding routing via a cell mux / demux board assembly (CMDA) 330 and a matching switch (ASW: 311). It transmits to the interface module (IM) 321, analyzes the test cell looped back from the interface module (IM) 321, and notifies the test result to the path test function in the call connection control processor (CCCP).

The cell mux / demux board assembly (CMDA) 330 multiplexes / demultiplexes the cells, adds an IPC message when establishing a call connection, and adds a routing tag to a test cell when performing a path test. IPC message is sent to the call connection control processor (CCCP: 314) by transmitting to the switch (ASW: 311) and receiving the loopback test cell from the matching switch (ASW: 311). Is transmitted to the test device 319, which is an ATM cell test board assembly (ACTA).

When the path test is completed, band conversion is performed to the call processing block, the end of the test is notified to the interface module controller (IM Controller), and the path test result is notified to the operator terminal 100.

FIG. 5 is a schematic diagram illustrating a cell path test to a central switch (CSW) in an ATM central switching subsystem (ACS) connected to an ACS_PORT in a single ATM local switching subsystem (ALS).

Routing tag attached to the test device Routing_tag_1: bittype (ASW port number) Routing_tag_2: bittype (CSW port number) Routing_tag_3: bittype (port number to which test device is connected)

If an operator requests a path test to a central switch (CSW) 210 connected to an ACS_PORT in a match switch (ASW) 311, the path test function in the call connection control processor (CCCP) 314 returns to the call processing block. Requires bandwidth allocation in both directions for path testing.

The path test function in the call connection control processor (CCCP) 314 requires test cell generation to the test device 319, which is an ATM cell test board assembly, so that the test device 319 generates a test cell to generate a central switch. (CSW) 210, and analyzes the test cell looped back from the central switch (CSW) 210 and notifies the test result to the path test function in the call connection control processor (CCCP).

When the path test is completed, the band for the call processing block is converted and the path test result is output to the operator terminal 100.

6 is a block diagram illustrating an IPC cell path test in an ATM local switching subsystem (ALS). That is, FIG. 6 illustrates a path test up to IPC_PORT with an ATM local switching subsystem (ALS) 310 coupled with the call connection control processor (CCCP) 314.

Routing tag attached to the test device Routing_tag_1: bittype (port number to which test device is connected) Routing_tag_2: bittype (0) Routing_tag_3: bittype (0)

If an operator requests a path test to IPC_PORT of a matched switch (ASW) 311 connected to the call connection control processor (CCCP) 314, the path test function in the call connection control processor (CCCP) 314 is an ATM. Test cell generation is required with the test device 319, a cell test board assembly.

The test device 319 generates the test cell and transmits the test cell to the matching switch (ASW) 311, and analyzes the test cell looped back from the matching switch (ASW) 311 to control a test result of the call connection control. Notifies the path test function in the processor (CCCP) 314. When the path test is completed, output the path test result to the operator terminal (100).

On the other hand, the suspension of the basic path test in a single ATM local switching subsystem (ALS) 310 is either a path test to the interface module (IM) associated with the USER_PORT in the single match switch (ASW) 311 currently in progress or a single match switch ( Path test to the central switch (CSW) 210 connected to ACS_PORT in ASW) 311 or path test to the call connection control processor (CCCP) 314 connected to IPC_PORT in single match switch (ASW) 311. Stop it. When a basic path test stop command in a single ATM local switching subsystem (ALS) 310 is input, the test device 319 is requested to stop the test and the test result up to the stop time is notified and output to the operator terminal 100. do.

7 is a block diagram illustrating inter-IMS cell path tests within the same ATM local switching subsystem (ALS).

The function of the local path test means a path test between the interface module (IM) and the interface module (IM) in a single ATM local switching subsystem (ALS).

Routing tag attached to the test device Routing tag attached to the start IM Routing tag attached to the end IM Routing_tag_1: bittype (port number to which starting IM is connected) Routing_tag_1: bittype (port number to which the terminating IM is connected) Routing_tag_1: bittype (port number to which test device is connected) Routing_tag_2: bittype (0) Routing_tag_2: bittype (0) Routing_tag_2: bittype (0) Routing_tag_3: bittype (0) Routing_tag_3: bittype (0) Routing_tag_3: bittype (0)

If an operator requires a path test between an interface module (IM) and an interface module (IM) in a single ATM local switching subsystem (ALS), the path test function in the call connection control processor (CCCP) 314 is transferred to a call processing block. For each of the start_IM 321 and the end_IM 331, the bandwidth allocation required for the path test is bidirectionally requested.

Once the details of the port connecting the two interface modules (IM) are assigned, for each of the start_IM 321 and end_IM 331, the interface module controller (IM Controller) can receive and loop back the test cell. Notifying of routing information and a path test function within the call connection control processor (CCCP) 314 requires the test device 319 to generate the test cell.

The test device 319 generates the test cell and transmits the test cell to the start_IM 321, and the start_IM 321 changes the routing information so that the path test cell is transmitted to the end_IM 331.

The end_IM 331 changes routing information so that the received test cell can go to the test device 319, so that the test device 319 loops back the test cell from the end_IM 331. Analyzes and reports the test results to the path test function in the call connection control processor (CCCP) 314.

When the path test is completed, the band is converted to the call processing block, the end of the test is notified to the interface module controller (IM Controller), and the path test result is output to the operator.

Suspension of the path test between two interface modules IM in the single ATM local switching subsystem (ALS) if an operator requests a path test stop command between two interface modules (IM) in the single ATM local switching subsystem (ALS). In addition, the test apparatus is requested to stop the test and the test result until the stop is notified and outputted to the operator.

8 is a block diagram of a cell path test between an interface module (IM) between a call connection control processor (CCCP) and another ATM local switching subsystem (ALS).

The global path test function will be described with reference to FIGS. 8 and 9.

Configured and attached to the test apparatus as shown in FIG. 8 for path testing between the Call Connection Control Processor (CCCP) in any ATM Local Switching Subsystem (ALS) and the Interface Module (IM) in another ATM Local Switching Subsystem (ALS). Experiment with the routing tag attached to the routing tag and the termination interface module (IM) as shown in Table 6.

Routing tag attached to the test device Routing tag attached at the end IM Routing_tag_1: bittype (port number where starting ASW is connected to CSW) Routing_tag_1: bittype (port number where the ending ASW is connected to the CSW) Routing_tag_2: bittype (port number connected to ASW terminated by CSW) Routing_tag_2: bittype (port number from CSW to starting ASW) Routing_tag_3: bittype (port number connected to the IM of the ending ASW) Routing_tag_3: bittype (port number to which test device is connected)

An operator requires a path test between the call connection control processor (CCCP) in any ATM local switching subsystem (ALS) and the interface module (IM) in another ATM local switching subsystem (ALS).

The path test function in the call connection control processor (CCCP) 314 is a port for connecting a start match switch (ASW) 311 and a central switch (CSW) 210 as a call processing block, and an end match switch (ASW) ( 361) requests bandwidth allocation in both directions for the port connecting the central switch (CSW) 210 and the port connecting the interface module IM of the termination_ASW 361. Once the band is allocated, the interface module controller notifies the end_IM 360 of the routing information to receive and loop back the test cell. If the process is successful, the path test function in the call connection control processor (CCCP) 314 requires the test cell generation to the test device 319, which is an ATM cell test assembly (ACTA) 319.

The test apparatus 319 generates and transmits a test cell to the end_IM 360, and the end_IM 360 changes routing information so that the received test cell can go to the test apparatus 319. .

The test device 319 analyzes the test cell looped back from the end_IM 360 and notifies the test result to the path test function in the call connection control processor (CCCP) 314 and informs the operator of the path test result. Output

9 is a block diagram illustrating cell path tests between interface modules IM in different ATM local switching subsystems (ALS).

Routing configured and attached to the test apparatus as shown in FIG. 9 to perform a path test between the interface module IM in any ATM local switching subsystem (ALS) and the interface module IM in another ATM local switching subsystem (ALS). The path test is performed by setting the tag, the routing tag attached by the start interface module (IM) and the routing tag attached by the end interface module (IM) as shown in Table 7.

Routing tag attached to the test device Routing tag attached to the start IM Routing tag attached to the end IM Routing_tag_1: bittype (port number to which starting IM is connected) Routing_tag_1: bittype (connection port number of start_ASW and CSW) Routing_tag_1: bittype (exit_port number of ASW and CSW) Routing_tag_2: bittype (0) Routing_tag_2: bittype (connection port number of CSW and exit_ASW) Routing_tag_2: bittype (connection port number of CSW and start_ASW) Routing_tag_3: bittype (0) Routing_tag_3: bittype (port number of exit_IM) Routing_tag_3: bittype (port number to which test device is connected)

The operator requires a path test between an interface module IM in any ATM local switching subsystem (ALS) and an interface module IM in another ATM local switching subsystem (ALS).

The path test function in the call connection control processor (CCCP) 318 is a port for connecting the interface module (IM) of the start_ASW 311 to the call processing block, the start_ASW 311 and the central switch (CSW) ( A path for connecting the port 210, a port connecting the end_ASW 361 and the central switch (CSW) 210, a port connecting the interface module (IM) 321 of the end_ASW 361, and the like. Requires bidirectional bandwidth allocation for testing. Once the band is allocated, the interface module controller (IM Controller) informs the start_IM 321 and the end_IM360 of the routing information to receive and loop back the test cell. If the procedure is successful, the path test function in the call connection control processor (CCCP) 318 requires test cell generation to the test device 319, which is an ATM cell test board assembly (ACTA).

The test device 319 generates a test cell and transmits it to the start_IM 321, and the start_IM 321 changes the routing information so that the received test cell can go to the end_IM 360. The start_ASW 311, the central switch (CSW) 210 and the end_ASW 361 in the ATM Central Switching Subsystem (ACS) are routed to the End_IM 360 to receive the test cell ( Change routing information to go to 319).

The test device 319 analyzes the test cell looped back from the end_IM 360 and notifies the test result to the path test function in the call connection control processor (CCCP) 318.

When the path test is completed, the band is returned to the call processing block, the end of the test is notified to the interface module controller (IM Controller), and the warning test result is notified to the operator terminal 100.

On the other hand, the path test halting between different ATM local switching subsystems (ALSs) is an interface module (IM) between the call connection control processor (CCCP) in another ATM local switching subsystem (ALS) and another ATM local switching subsystem (ALS). Stop the path test between the interface module (IM) in any ATM local switching subsystem (ALS) and the interface module (IM) in another ATM local switching subsystem (ALS).

When the operator requests a path test stop command between different ATM local switching subsystems (ALS), the test apparatus requests the test stop and the test result up to the stop point is notified and output to the operator.

In addition, the path test command entered by the basic operator is stored in the history, and the contents of the path test currently in progress are displayed.

Depending on the type of basic path test, local path test and global path test, the output of the path test is output as follows.

If the path test type is a basic path test, the ASW number, port number, path test period, path test bandwidth, and traffic mode are output.

If the path test type is a local path test, the ASW number, port number, end port number, path test period, path test bandwidth, and traffic mode are output.

If the path test type is Global Path Test, the start match switch (ASW) number, the start user (USER) port number, or the port number to which the call connection control processor (CCCP) is connected, the start ATM central switching subsystem (ACS) port number, and the end match. Output switch (ASW) number, terminating ATM central switching subsystem (ACS) port number, terminating user (USER) port number, path test period, path test bandwidth, traffic mode.

As described above, the switch test method in the asynchronous transfer mode (ATM) switch according to the present invention is a basic path test, a local test according to the location of the path test target port in connection with the call processing block, subscriber / relay line matching block, the test apparatus And by performing the global test, it is possible to check the path performance when the exchange error is high when the exchange is initially installed, when the board is replaced, and when the board is replaced due to a failure.

Claims (4)

In an asynchronous transfer mode (ATM) exchange, depending on the location of a path test target port for switch testing in an asynchronous transfer mode (ATM) exchange in conjunction with a call processing block, a subscriber / relay line matching block, and a testing device. A unit path test step; Local Path Test step; And A switch test method in an asynchronous delivery mode switch comprising the step of a global path test. The method of claim 1, wherein the basic path testing step (a) a path testing step to an interface module (IM) associated with USER_PORT in a single ATM Local Switching Subsystem (ALS); (b) a path testing step to a central switch (CSW) in an ATM central switching subsystem (ACS) connected to an ACS_PORT in the single ATM local switching subsystem (ALS); (c) a path test step up to IPC_PORT of the ATM local switching subsystem (ALS) coupled with a call connection control processor (CCCP) in the ATM local switching subsystem (ALS); And (d) stopping a basic path test in the single ATM local switching subsystem (ALS). The method of claim 1, wherein said local path testing step comprises: (e) a path testing step between the start interface module IM and the end interface module IM in a single ATM local switching subsystem ALS; And (f) A method for testing a switch in an asynchronous delivery mode switch comprising the step of suspending a path test between two interface modules (IM) in a single ATM local switching subsystem (ALS). The method of claim 1, wherein the global path testing step (g) a path test step between a call connection control processor (CCCP) in any ATM local switching subsystem (ALS) and an interface module (IM) in another ATM local switching subsystem (ALS); (h) a path testing step between an interface module IM in any ATM local switching subsystem ALS and an interface module IM in another ATM local switching subsystem ALS; And (i) stopping the path test between different ATM local switching subsystems (ALS).