KR20000023077A - Field emission element and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A method of manufacturing a field emission device is provided to increase the electric field at an emitter end CONSTITUTION: A method of manufacturing a field emission device comprises the steps of: forming a surface layer including a conductive gate layer on a substrate; eliminating a part of the surface layer to form a hole penetrating the surface layer; forming a side- space forming part composed of a first sacrificial layer on the side wall of the hole; forming a second sacrificial layer on the surface layer and the entire surface of the hole to form a planarized layer of the second sacrificial layer on the bottom of the hole; forming a conductive emitter layer having a different thickness at a different location on the entire surface of the second sacrificial layer; eliminating the entire thickness of the emitter layer from the hole bottom and anisotropic-etching-back the entire surface of the emitter layer to form a penetrating hole on the emitter layer; and eliminating at least a part of the substrate and the second sacrificial layer to expose at least the vicinity of the emitter end.

Description

Field emission device and manufacturing method thereof {FIELD EMISSION ELEMENT AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a field emission device and a method for manufacturing the same, and more particularly, to a field emission device having a field emission cathode from which electrons are emitted from its tip and a method for manufacturing the same.

The field emission device emits electrons from the tip of a sharp emitter (field emission cathode) using field concentration. For example, flat panel displays are constructed using a field emitter array (FEA) with multiple emitters disposed above the array. Each emitter controls the brightness and the like for each pixel of the corresponding display.

A paper by Baoping Wang, "Novel Single- and Double-Gate Race-Track-Shaped Field Emitter Structures" (Proc. IEDM, pp. 313-316, 1996, reports a race track type field emission emitter with a gate electrode in the longitudinal direction. In the device of this emitter structure, the emitter electrode is disposed so as to be between the inner post-gate electrode and the outer second gate electrode. The post-gate electrode on the inside of the device applies an electric field to the emitter tip to emit electrons, and the external second gate electrode strengthens the electric field of the emitter tip to between the post-gate electrode and the emitter electrode. It lowers the threshold voltage. Also not described in this document, the external second gate electrode also serves to converge the emitted electron beam.

The diameter of this post-gate is 4 [mu] m, one unit larger (1 digit) than the conventional form. Therefore, exposure to 1/4, 1/5 times, 1/10 exposure stepper, electron beam (EB), or focused ion beam (FIB) is expensive and has low throughput per unit time. Without the use of devices, contact aligners, proximity aligners, mirror aligners, or steppers with 1/1, 1/2, 1 / 2.5 exposure, etc. As a device having a low cost or high throughput per unit time, a vacuum micro device can be formed.

The distance between the emitter electrode and the gate electrode is determined by the thickness of the insulating film such as SiO ₂ . Since the area of the emitter is large, the current density with respect to the unit area is large.

Reportedly, there is a method of improving the current density with respect to the unit area by increasing the number of sharp emitter electrodes corresponding to one gate electrode.

In addition, a method of forming a self-dispersible ultrafine particle or the like on a sacrificial film having a recess serving as a mold and manufacturing a current-emitting emitter has also been proposed.

In the paper published by Akama, "Field Emission Devices Using β-W Films", Japanese Society of Spring Applied Physics Publication No. 2, P640, 30p-T-3, an electric field using β-W films Emission element has been reported.

Japanese Patent Laid-Open No. 5-211030 discloses a field electron emission device in which a cathode is made of a thermoionic emission material formed in a hole of a porous aluminum anodization film.

The processing flow for a single gate type field emission device is shown in FIG. 6 of the aforementioned paper "New Structure of Single or Double Gate Race Track Type Field Emission Emitter." In this figure, the height of the post-gate electrode is equal to the height of the emitter electrode. However, in the SEM image of the cross-sectional view shown in Fig. 9, the emitter electrode contracts and lies far below that of the gate electrode. A positive voltage is applied to this post-gate electrode as compared to the emitter electrode. Many electrons emitted from an emitter electrode located far below the gate electrode will be absorbed by the post-gate electrode before arriving at the anode or phosphor. In addition, the position of the emitter electrode is larger than the etching time or condition.

21A is a cross-sectional view for explaining a step of forming an emitter electrode using ultra-fine particles constructed in accordance with the prior art. The gate electrode 201 is formed on the substrate 200, and the side space forming part 202 is formed on the sidewall of the hole formed to pass through the gate electrode 201. The sacrificial film 203 of the Si oxide film is formed on the entire surface of the gate electrode 201 and the side space forming portion 202. The conductive self-dispersible ultrafine particles 204 are applied onto the sacrificial film 203 and baked at 150 ° C. for 5 minutes to improve the embedding characteristics of the ultrafine particles. However, when baked at 200 ° C. for 5 minutes, small voids are generated among the ultrafine particles 204. In addition, when baked at 300 ° C. for 5 minutes, a large void 205 is generated and the void 205 disconnects the emitter electrode into two parts, so that no voltage is applied to the tip of the emitter.

The reason why the voids are formed is not only due to the growth and volume shrinkage of the fine particles. This is also because the slipperiness with the surface of the Si oxide film 203 is deteriorated. The baking temperature should be as low as possible to prevent the increase in void or particle diameter. On the other hand, in order to reduce the resistance of an emitter electrode, it is necessary to bake at about 250 degreeC or more. Large emitter resistance prevents the field from weakening or emitting at the emitter tip. Increasing the voltage applied between the emitter and the gate electrode makes the driving circuit expensive, complicated, and increases the power consumption.

In addition, the adhesion between the self-dispersible ultrafine particles such as Au and Ag and glass or SiO ₂ is poor. Therefore, the adhesion with the mold or the support substrate is deteriorated. In order to prevent peeling of the emitter electrode due to the difference in thermal expansion coefficient in the manufacturing process, high temperature treatment is inevitable.

Since the field emission device using the β-W film has a gate electrode and an emitter electrode formed far from each other in the height direction, the electric field becomes weak at the tip of the emitter electrode.

The field emission device whose cathode is the hot electron emission material formed in the hole of the porous aluminum anodic oxide film is not manufactured by the automatic alignment method. That is, it is necessary to design in consideration of the lateral shift between the gate and the emitter. This widens the distance between the gate and the emitter electrode and weakens the electric field at the emitter tip.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a field emission device capable of raising the electric field at the emitter tip and a method of manufacturing the same.

It is still another object of the present invention to provide a field emission device capable of facilitating control of the emitter tip in the height direction during the manufacturing process and a method of manufacturing the same.

Still another object of the present invention is to provide a field emission device and a method of manufacturing the same, which do not disconnect the emitter even if voids are generated in the emitter electrode in the manufacturing process.

1A to 1I are cross-sectional views illustrating a manufacturing step of a two-electrode field emission device according to a first embodiment of the present invention;

2A and 2B illustrate a method of strengthening the field emission device of the first embodiment by using a support substrate;

3A to 3H are cross-sectional views illustrating a manufacturing step of a three-electrode field emission device according to a second embodiment of the present invention;

4A and 4B are cross-sectional views for explaining a manufacturing step of a field emission device according to a modification of the second embodiment of the present invention;

5A to 5I are cross-sectional views for explaining a manufacturing step of a two-pole field emission device according to a third embodiment of the present invention;

6A and 6B are cross-sectional views for explaining a manufacturing step of a field emission device according to a modification of the third embodiment of the present invention;

7A to 7H are cross-sectional views illustrating manufacturing steps of a three-electrode field emission device according to a fourth embodiment of the present invention;

8A and 8B are cross-sectional views illustrating a manufacturing step of a field emission device according to a modification of the fourth embodiment of the present invention;

9A to 9I are cross-sectional views for explaining a manufacturing step of a two-electrode field emission device according to a fifth embodiment of the present invention;

10A and 10B are cross-sectional views for explaining a manufacturing step of a field emission device according to a modification of the fifth embodiment of the present invention;

11A to 11H are cross-sectional views illustrating manufacturing steps of a field emission device according to a sixth embodiment of the present invention;

12A and 12B are cross-sectional views illustrating a manufacturing step of a field emission device according to a modification of the sixth embodiment of the present invention;

13A to 13I are cross-sectional views illustrating a manufacturing step of a two-electrode field emission device according to a seventh embodiment of the present invention;

14A to 14C are cross-sectional views for explaining a manufacturing step of a field emission device according to a modification of the seventh embodiment of the present invention;

15A to 15H are cross-sectional views illustrating manufacturing steps of a three-electrode field emission device according to an eighth embodiment of the present invention;

16A to 16C are cross-sectional views illustrating a manufacturing step of a field emission device according to a modification of the eighth embodiment of the present invention;

17A to 17I are cross-sectional views illustrating a manufacturing step of a two-electrode field emission device according to a ninth embodiment of the present invention;

18A and 18B are cross-sectional views illustrating a manufacturing step of a field emission device according to a modification of the ninth embodiment of the present invention;

19A to 19H are cross-sectional views illustrating manufacturing steps of a three-electrode field emission device according to a tenth embodiment of the present invention;

20A to 20C are cross-sectional views illustrating a manufacturing step of a field emission device according to a modification of the tenth embodiment of the present invention;

21A is a cross-sectional view illustrating a manufacturing step of a field emission device according to the prior art, FIG. 21B is a cross-sectional view illustrating in detail a manufacturing step of a field emission device according to a ninth embodiment of the present invention, and FIG. Sectional drawing for explaining in detail the manufacturing steps of the field emission device according to the seventh embodiment,

22 is a perspective view of a field emission device according to an embodiment of the present invention;

23 is a cross-sectional view of a flat panel display using a field emission device;

24 is an enlarged view of the tip of the emitter electrode shown in FIG. 1I.

<Description of the symbols for the main parts of the drawings>

10, 20, 30, 40, 50, 60, 70, 80, 90, 100: substrate

11, 21, 31, 41, 51, 61, 71, 81, 91, 101: gate electrode film

11a, 21a, 31a, 41a, 51a, 61a, 71a, 81a, 91a, 101a, 114: gate electrode

13a, 23a, 33a, 43a, 54a, 64a, 74a, 84a, 93a: side spacers

15a, 25a, 35a, 45a, 56a, 66a, 76a, 86a, 87a, 95a, 105a, 106a, 113: emitter electrode

40b, 60b, 80b, 100b: anode electrode

According to a first aspect of the present invention as a means for achieving the above object, a support substrate; The support substrate having a base supported by and attached to the support substrate, a protrusion projecting from the base in a direction opposite to the support substrate, and an opening formed in a portion from the tip of the protrusion to the surface of the support substrate; A first emitter electrode formed on the substrate surface of the substrate; A first sacrificial layer formed at a base of the first emitter electrode and having an opening surrounding a peripheral area outside the protrusion; And a gate electrode formed on the first sacrificial film having an opening surrounding a peripheral area outside the protrusion.

According to a second aspect of the present invention, there is also provided a method for forming a surface layer comprising: (a) forming a surface layer including a conductive gate film on a substrate; (b) removing a portion of the surface layer to form a hole passing through the surface layer; (c) forming a side space forming portion made of a material of a first sacrificial film on the sidewall of the hole; (d) forming a second sacrificial film on the entire surface of the surface layer and the hole such that a flat surface of the second sacrificial film is formed at the bottom of the hole; (e) forming a conductive emitter film to have different thicknesses at different locations on the entire surface of the second sacrificial film; (f) removing the entire thickness of the emitter film from the bottom of the hole and anisotropically etching back the entire surface of the emitter film to form a through hole in the emitter film; And (g) removing at least a portion of the substrate and the second sacrificial film to expose at least the vicinity of the tip of the emitter film.

Since the tip of the emitter electrode is opened to form a through hole in the emitter film, the electric field in the emitter electrode can be strong.

In addition, since the flat surface of the second sacrificial film is flush with the surface of the emitter film, the position of the tip of the emitter in the height direction can be controlled.

In addition, if the emitter electrode is made of the second emitter film formed by the first emitter film and the ultrafine particles, electrical disconnection of the emitter electrode can be prevented even if voids are generated.

Further, by etching back the tip of the emitter electrode, the radius of curvature of the tip of the emitter electrode at the outer periphery can be formed to 5 nm or less in cross section. Since the area of the emitter electrode is large, the emission current can be increased.

In addition, the baking temperature for the ultrafine particles of the emitter film can be lowered, and an increase in the radius of the ultrafine particles can be prevented.

In addition, since the emitter electrode can be operated at a low applied voltage, the drive device can be configured with a simple design and lower the power consumption.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration of the present invention.

1A to 1I are cross-sectional views illustrating manufacturing steps of the field emission device of the two electrodes according to the first embodiment of the present invention. The two-electrode element has two electrodes: an emitter electrode (cathode) through which electrons are emitted and a gate electrode that controls the emission of electrons.

As shown in FIG. 1A, a gate electrode film 11 is formed on a single layer substrate made of glass, quartz, or the like, or a substrate 10 made of a stack of Si and Si oxide films. The gate electrode 11 is made of polysilicon doped with P (phosphorus) or boron (B) to have a thickness of 0.2 탆.

For example, this polycrystalline silicon film is formed by introducing HeH-diluted SiH ₄ gas into a film forming chamber at a flow rate of 0.6 slm and subjecting the vessel to a temperature of 625 占 폚 and a pressure of 30 Pa. Thereafter, for the purpose of lowering the resistance value of the membrane, a gas having a flow rate of POCl ₃ = 50 mg / min, N ₂ = 20 slm and O ₂ = 0.1 slm was introduced, respectively, and a vertical diffusion furnace was conducted at a temperature of 850 ° C. P is diffused into the polycrystalline silicon film by using.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the gate electrode film 11 by photolithography. Then, the gate electrode film 11 is anisotropically etched using a resist pattern as a mask to form the recess 12 as shown in FIG. 1B, leaving the gate electrode 11a having a predetermined pattern. . This recess 12 has a generally vertical inner wall, and its shape (on plan view) is circular with a diameter of 0.5 mu m and a depth of about 0.2 mu m.

Next, as shown in FIG. 1C, the Si oxide film is deposited to a thickness of 0.15 μm by atmospheric pressure CVD (chemical vapor deposition) to expose the first sacrificial film (insulating film) 13 to the recess 12. It is formed on the surface of the board | substrate 10 and the gate electrode 11a.

For example, this sacrificial film is formed by O ₃ and TEOS (Tetraethoxysilane) as source gas at a substrate temperature of 400 ° C. Instead of the Si oxide film, an insulating film such as a Si nitride film or a conductive film such as polycrystalline silicon, W silicide, Al alloy, TiN _x or the like may also be used.

Next, as shown in FIG. 1D, the first sacrificial film 13 is anisotropically dry-etched (etched back) to form the side space forming part 13a of the hole 12 of the gate electrode 11a. Only part of the first sacrificial film is left on the inner wall. By this etching, the surface of the gate electrode 11a is exposed, and the surface of the substrate 10 is exposed in the hole 12.

For example, this etching is performed using a magnetron RIE system under CHF ₃ + CO ₂ + Ar etching gas and a reaction chamber pressure of 50 mTorr.

Next, as shown in Fig. 1E, a second sacrificial film 14 made of SiO ₂ is isotropically deposited on the entire substrate surface to a thickness of 0.1 mu m by atmospheric pressure CVD. For example, this film is formed at a substrate temperature of 400 ° C. using TESO and O ₃ as source gas. The deposited second sacrificial film 14 is left on the surface of the gate electrode 11a and the side space forming part 13a (to be integrated).

Next, as shown in FIG. 1F, the emitter electrode film 15, for example, TiN _x, is deposited on the second sacrificial film 14 by a reactive sputtering method to a thickness of 0.15 μm measured at the upper flat surface portion. . For example, reactive sputtering is formed using a DC sputtering system under a target of Ti and a supply condition of N ₂ + Ar gas. The emitter electrode film 15 is thick on the top flat surface of the second sacrificial film, gradually thinner on the side space forming portion 13a, and thinnest at the bottom of the hole 12.

Next, as shown in FIG. 1G, the emitter electrode film 15 is etched back to about 0.05 μm as measured on the upper planar surface so that the emitter electrode film 15 is only on the bottom of the hole 12. ) Is completely removed, leaving the emitter electrode 15a on the gate electrode 11a and the side space forming portion 12a. The emitter electrode 15a includes a base 15c and a protrusion (volcano crater-shaped portion: 15d) that extends from and protrudes from the base 15c. An opening 15b is formed through the protrusion 15b through the hole 15e from the tip of the emitter electrode 15a to the etching-back. This etch-back is anisotropically performed by dry-etching. For example, a magnetron RIE system using Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr is used.

Next, as shown in FIG. 1H, portions of the substrate 10, the side space forming portion 13a, and the second sacrificial film 14 are removed by etching to form the gate electrode 11a and the emitter electrode 15a. To expose. The opening 14b is formed in the second sacrificial film, and the opening 11b is formed in the gate electrode 11a. If the substrate 10 is formed of Si, it is etched using HF + HNO ₃ + CH ₃ COOH. SiO ₂ such as the side space forming portion 13a is etched by HF + NH ₄ F.

Finally, as shown in FIG. 1I, the support substrate is bonded to the emitter electrode 15a by electrostatic bonding to impart mechanical strength to the emitter electrode 15a. The support substrate 16 may be made of glass, quartz or Al ₂ O ₃ .

According to this embodiment, a two-electrode field emission device having a gate electrode 11a disposed close to the side of the emitter electrode 15a can be manufactured. The emitter electrode 15a has a base 15c to which it is attached and supported by the support substrate 16, and a hollow hollow projection 15d which extends and protrudes by gradually decreasing an inner diameter downward from the base 15c. ) The protruding portion 15d of the emitter electrode 15a is formed through the hole 15e and has a volcanic shape. The inner surface of the volcanic protrusion 15c gradually increases the angle relative to the upper surface of the base 15b.

The diameter of the boundary between the protrusion 15d and the base 15c is, for example, about 0.4 mu m, and the tip diameter of the protrusion 15d is about 0.1 mu m.

The thickness of the protrusion 15d is about 0.4 mu m at the boundary with the base 15c and about 0.05 mu m at its tip.

The volcanic emitter electrode 15a may have a stronger electric field than the conventional emitter electrode. Reactive ion etching (RIE) etch-back treatment can reduce the radius of curvature of the tip of the emitter electrode to 5 nm or less.

As the radius of curvature of the tip of the emitter electrode 15a decreases, the electric field is concentrated on the tip of the emitter electrode 15a, and the performance of the field emission device is improved. Since the area of this emitter electrode 15a is large, the emission current can be increased.

24 is an enlarged view of the tip 201 of the emitter electrode 15a. The radius of curvature of the inner circumferential portion 203 of the tip portion 201 is determined by the etching process shown in FIG. 1G. The radius of curvature of the outer circumferential portion 202 of the tip portion 201 is determined by the shape of the second sacrificial film 14 formed as shown in FIG. 1E. For example, the radius of curvature of the inner circumference 203 is smaller than the radius of curvature of the outer circumference 202.

2A and 2B are cross-sectional views showing an embodiment modified from the first embodiment. This variant provides another method of strengthening the emitter electrode 15a with a support substrate. A third sacrificial film 17 is formed on the emitter electrode 15a of the first embodiment obtained in the process of FIG. 1G. This third sacrificial film 17 is formed of polycrystalline silicon by a low pressure CVD method, and the thickness thereof is 0.2 탆. In order to lower the resistance, the polycrystalline silicon is introduced with impurity ions such as P or B by ion implantation, thermal diffusion, or the like.

Next, as shown in FIG. 2A, the concave portion of the third sacrificial film is filled with a planarization film made of, for example, spin on glass (SOG).

The surface of the planarization film 18 is planarized by chemical mechanical polishing (CMP) or etching (etching-back). The planarization layer may be formed by reflowing Phosphosilicate Glass (PSG) or Borophosphosilicate Glass (BPSG) instead of SOG.

Next, the support substrate 19 is bonded to the emitter electrode by electrostatic bonding. For example, the support substrate 19 is made of glass, quartz or Al ₂ O ₃ .

Next, the substrate 10 or the like is etched away by an etching process similar to that of FIG. 1H to expose the lower portion of the emitter electrode, as shown in FIG. 2B. The third sacrificial film 17 is present between the support substrate 19 and the emitter electrode 15d. This emitter electrode 15a has a base 15c and a protrusion 15d. The passage hole 15b is formed through the protrusion part 15d. A part of the third sacrificial film 17 is partially filled in the protrusion 15d on the base side.

A method of manufacturing a two-electrode field emission device having an emitter and a gate electrode has been described so far. Next, a method of manufacturing another form of the field emission device that is a three-electrode device will be described. This three-electrode element has three electrodes, an emitter electrode, a gate electrode and an anode electrode.

3A to 3H are views for explaining the manufacturing steps of the three-electrode field emission device according to the second embodiment of the present invention.

As shown in Fig. 3A, the anode electrode 20b of polycrystalline silicon doped with P and B is deposited to a thickness of 0.15 mu m by sputtering on a starting substrate 20a made of a Si oxide film.

Next, a first sacrificial film (insulating film 20c) is deposited on the anode electrode 20b by CVD to obtain a substrate 20. The gate electrode film 21 is formed in this board | substrate 20 to thickness of 0.3 micrometer by sputtering. The gate electrode film 21 is made of polycrystalline silicon doped with P or B.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the gate electrode film 21 by the photolithography method. Using this resist pattern as a mask, the gate electrode film 21 is anisotropically etched to leave the gate electrode 21a having the concave portion (through hole 22) as shown in Fig. 3A. The concave portion (through hole) 22 is cylindrical in shape (on plan view) having a diameter of 0.5 탆 and a depth of 0.3 탆.

This etching is performed, for example, by dry-etching using magnetron RIE using HBr as the etching gas at a reaction chamber pressure of 100 mTorr.

Next, processes are performed similar to those of the first embodiment shown in FIGS. 1C and 1D, so that only SiO is formed on the inner wall of the recess (through hole 22) of the gate electrode 21a, as shown in FIG. 3B. _The side space forming part 23 made of the second sacrificial film 2 is formed.

Next, as shown in Fig. 3C, a third sacrificial film made of SiO ₂ (insulating film 24) is isotropically formed on the entire surface of the substrate at a thickness of 0.1 mu m by the atmospheric pressure CVD method. For example, this film is formed at a substrate temperature of 400 ° C. using TEOS and O ₃ .

Next, as shown in FIG. 3D, the emitter electrode film 25 is made of TiN _x , for example, and is formed on the third sacrificial film 24 to have a thickness of 0.15 μm by reactive sputtering. For example, reactive sputtering is performed using a DC sputtering system under conditions of supply of Ti target and N 2 + Ar gas.

Next, as shown in FIG. 3E, the emitter electrode film 25 is etched back by 0.05 [mu] m and completely removed only on the bottom of the concave portion (through hole 22) so that the third sacrificial film 24 is removed. The emitter electrode 25a is left on the inner wall and the upper surface. The emitter electrode 15a includes a base 25c and a protrusion 25d (crater-shaped portion of a volcano). With this etching-back, the tip of the protrusion 25d of the emitter electrode 25a is opened, and the through hole 25e extends to this tip. Etch-back is performed by dry-etching. For example, the magnetron RIE system uses Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr.

Next, a resist mask (not shown) is formed on the emitter electrode 25a by a normal photolithography method. Using this resist mask, the emitter electrode 25a is partially etched away to form the slit-shaped opening 26 shown in FIG. 3F. The inside of the emitter electrode portion of this slit-shaped opening 26 is represented by 25b, and the outside of the emitter electrode portion of this slit-shaped opening 26 is represented by 25c. This slit-shaped opening 26 is formed by anisotropic dry-etching. For example, the magnetron RIE system uses Cl ₂ as an etching gas at a reaction pressure of 125 mTorr. The process of FIG. 3E and the process of FIG. 3F may be reversed.

Next, as shown in FIG. 3G, the lateral space forming portion 23 and a part of the first and third sacrificial films 20c and 24 are isotropically wet-etched and removed to emit the emitter. The electrodes 25b and 25c, the gate electrode 21a and the anode electrode 20b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F.

The slit-shaped openings 26 formed in the process shown in FIG. 3F may not be formed. In this case, after the process shown in Fig. 3E, the lateral space forming portion 23 and a part of the first and second sacrificial films 20c and 24 are isotropically wet-etched and removed through the protrusion 25d. The emitter electrodes 25b and 25c, the gate electrode 21a and the anode electrode 20b are exposed to complete the three-electrode element as shown in FIG. 3H. SiO ₂ is etched by HF and NH ₄ F. As described above, the emitter electrode 25a has a base portion 25c and a protrusion portion 25d protruding from and extending from the base portion. The protrusion 25d has a through hole 25e.

4A and 4B are sectional views showing a modified example of the second embodiment. As shown in FIG. 4A, the first and third sacrificial films 20c and 24 are emitters using the emitter electrode of the field emission device formed by processing as shown in FIG. 3E of the second embodiment as a mask. It is anisotropically etched in the depth direction through the protrusion 25d of the electrode 25a. This anisotropic dry-etching is performed by using CHF ₃ + CO ₂ + Ar as an etching gas at a reaction chamber pressure of 50 mTorr, for example, using a magnetron RIE system.

Thereafter, portions of the lateral space forming portion 23 and the first and third sacrificial films 20c and 24 are isotropically wet-etched and removed through the protrusion 25d of the emitter electrode 25a to emit the electrode. A three-electrode element as shown in Fig. 4B is completed by exposing 25a, gate electrode 21a and anode electrode 20b. SiO ₂ is etched by HF + NH ₄ F.

5A to 5I are cross-sectional views illustrating a manufacturing step according to a third embodiment of the present invention. A method of drawing a two-electrode element having an emitter electrode (field emission cathode) and a gate electrode will be described below.

As shown in Fig. 5A, a gate electrode film 31 is formed on a substrate 30 which is a single layer substrate made of glass, quartz, or a stack of Si and Si oxide films. The gate electrode 31 is formed of a polycrystalline silicon film doped with P or B so as to have a thickness of 0.1 탆.

This polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into a film forming chamber at a temperature of 625 ° C. and a pressure of 30 Pa at a flow rate of 0.6 slm. Thereafter, for the purpose of lowering the resistance of the film, gases of POCl ₃ = 50 mg / min, N ₂ = 20 slm, and O ₂ = 0.1 slm were introduced into the polycrystalline silicon film at a temperature of 850 占 폚 in a vertical diffusion furnace. P diffuses.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the gate electrode film 31 by the photolithography method. Then, the gate electrode film 31 is anisotropically etched using a resist pattern as a mask to form a concave portion (through hole) 32 as shown in FIG. 5B, and the gate electrode 31a having a predetermined pattern. Leave it. This concave portion (through hole) 32 has a generally vertical inner wall, and its shape (on plan view) is circular with a diameter of 0.5 mu m and a depth of about 0.15 mu m.

Next, as shown in FIG. 5C, a second gate electrode film 33 is formed on the surfaces of the substrate 30 and the gate electrode 31a exposed to the recessed portion (through hole 32). The second gate electrode film 33 is a polycrystalline silicon film doped with P or B and is formed to have a thickness of 0.15 μm.

This polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into the film forming chamber at a temperature of 625 ° C. and a pressure of 30 Pa at a flow rate of 0.6 slm. Thereafter, for the purpose of lowering the resistance of the film, gases of POCl ₃ = 50 mg / min, N ₂ = 20 slm, and O ₂ = 0.1 slm were introduced into the polycrystalline silicon film at a temperature of 850 占 폚 in a vertical diffusion furnace. P diffuses. Instead of polycrystalline silicon, the second gate electrode 33 may be formed of W silicide, Al alloy, TiN _x, or the like.

Next, as shown in FIG. 5D, the second gate electrode film 33 is anisotropically dry-etched (etched-back) and has side spaces only on the inner wall of the recess (through hole 32) of the gate electrode 31a. A portion of the gate electrode is left as the forming portion 33a. By this etching, the surface of the gate electrode 31a is exposed, and the surface of the substrate 30 in the concave portion (through hole 32) is exposed.

This etching is performed by using magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

Next, as shown in Fig. 5E, a first sacrificial film made of SiO ₂ (insulating film 34) is deposited on the entire substrate surface by the atmospheric pressure CVD method at a thickness of 0.1 mu m on the entire substrate surface. This film is formed at a substrate temperature of 400 ° C., for example, using TESO and O ₃ as source gas. The first sacrificial film 34 is left on the surface of the gate electrode 31a and the side space forming portion 33a (to be integrated).

Next, as shown in FIG. 5F, an emitter electrode film 35 made of TiN _x , for example, is deposited on the first sacrificial film 34 to a thickness of 0.15 μm through reactive sputtering. Reactive sputtering is performed under the conditions of a DC sputtering system, for example, under a target of Ti and a supply condition of N ₂ + Ar gas. Next, as shown in FIG. 5G, the emitter electrode film 35 is etched back by 0.05 μm so that the emitter electrode film 35 is completely removed only at the bottom of the concave portion (through hole 12), and the gate The electrode 31a and the side space forming portion 33a remain as the emitter electrode 35a. This etch-back is performed by anisotropic dry-etching. The magnetron RIE system uses Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr.

Next, as shown in FIG. 5H, a portion of the substrate 30 and the first sacrificial film 34 are etched away to expose the lateral space forming portion 33a and the emitter electrode 35a. When the substrate 30 is formed of Si, it is etched using HF + HNO ₃ + CH ₃ COOH. SiO ₂ such as the side space forming portion 13a is etched by HF + NH ₄ F. The emitter electrode 35a includes a base 35c and a protrusion (volcano crater-shaped portion: 35d) that extends from and protrudes from the base 35c. This protrusion (crater 35d) has a through hole 35e.

Finally, as shown in FIG. 5I, the support substrate 36 is bonded to the emitter electrode 35a by electrostatic bonding to impart mechanical strength to the emitter electrode 35a. The support substrate 36 may be made of glass, quartz or Al ₂ O ₃ .

After the process shown in FIG. 5G, the support substrate 36 may be adhered to the emitter electrode 35a by electrostatic bonding, after which the substrate 30 and a portion of the first sacrificial film 34 are part of FIG. 5H. It can be removed as shown.

According to this embodiment, in addition to the advantages of the first embodiment, the side-space forming portion 33a made of a conductive material remains as the gate electrode, so that the distance between the emitter tip and the gate electrode is shortened so that the electric field at the emitter tip is An additional effect arises that becomes strong and the device performance can be improved. That is, the diameter of the gate hole defined by the second gate or side space forming portion 33a is smaller than that defined by the gate electrode 31a, so that the distance between the gate electrode and the emitter electrode is shortened. Therefore, electron emission is possible at a low voltage.

6A and 6B are cross-sectional views for explaining a modified example of the third embodiment. This variant provides another method of strengthening the emitter electrode 35a with a support substrate. A second sacrificial film (conductive film 36) is formed on the emitter electrode 35a of the device obtained in the process of Fig. 5G of the above-described third embodiment. The second sacrificial film (conductive film 36) is made of polycrystalline silicon, and is formed to a thickness of 0.2 占 퐉 by reduced pressure CVD. The second sacrificial film may be made of an insulating film such as an Si oxide film and a Si nitride film. In order to lower the resistance, impurities such as P and B can be introduced into the polycrystalline silicon by ion implantation, thermal diffusion, or the like.

Next, as shown in FIG. 6A, the recess is filled with a planarization film 37 made of SOG, for example, on the second sacrificial film. This planarization film 37 is planarized by CMP or etching (etching-back). Instead of the SOG, the planarization film 38 may be formed by reflowing the PSG or the BPSG.

Next, the support substrate 38 is bonded to the emitter electrode 35a by electrostatic bonding. For example, the support substrate 38 is made of glass, quartz, or Al ₂ O ₃ .

Next, the substrate 30 or the like is etched away by an etching process similar to that of FIG. 5H to expose the bottom of the emitter electrode as shown in FIG. 6B to complete the field emission device.

7A to 7H are cross-sectional views illustrating a manufacturing step of a three-electrode type field emission device according to a fourth embodiment of the present invention.

As shown in FIG. 7A, the substrate 40 is composed of a start substrate 40a, an anode electrode 40b and a first sacrificial film 40c formed on the start substrate 40a. An anode electrode 40b of polycrystalline silicon doped with P or B is deposited to a thickness of about 0.15 mu m by sputtering on a starting substrate 40a made of a Si oxide film.

Next, a first sacrificial film (insulation film) 40c is deposited on the anode electrode 40b by CVD to obtain a substrate 40. The gate electrode film 41 is formed on the substrate 40 with a thickness of 0.3 탆 by sputtering or low pressure CVD. This gate electrode film 41 is made of polycrystalline silicon doped with P or B.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the gate electrode film 41 by the photolithography method. Using the resist pattern as a mask, the gate electrode film 41 is anisotropically etched, leaving a gate electrode 41a having a recess (through hole 42) as shown in Fig. 7A. The shape of the concave portion (through hole 42) is circular when viewed from a plan view having a diameter of 0.5 mu m and a depth of about 0.3 mu m, and is formed in a cylindrical shape as a whole.

This etching is performed by using magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

A process similar to that of the third embodiment shown in Figs. 5C and 5D is executed, so that the side space forming portion 43a made of the second gate electrode film of Si or another conductive material is formed as shown in Fig. 7B. It forms only on the inner wall of the recessed part (passing hole 42) of 41a.

Next, as shown in Fig. 7C, a second sacrificial film (insulation film: 44) made of SiO ₂ is deposited on the entire substrate surface by an atmospheric pressure CVD method with a thickness of 0.1 mu m. This film is formed at a substrate temperature of 400 ° C. using TEOS and O ₃ as source gas, for example.

Next, as shown in FIG. 7D, the emitter electrode film 45 is made of TiNx, for example, and is deposited on the second sacrificial film 44 to a thickness of 0.15 μm by reactive sputtering. Reactive sputtering is formed using, for example, a DC sputtering system under the condition of supplying a Ti target and N ₂ + Ar gas.

Next, as shown in FIG. 7E, the emitter electrode film 45 is etched back by about 0.05 μm to remove the emitter electrode film 45 only on the bottom of the recess (through hole 42). 2 is left as the emitter electrode 45a on the upper surface and the inner wall of the sacrificial film 44. The emitter electrode 45a includes a base 45c and a protrusion (crater-like portion of the volcano: 45d). By this etching-back, the tip of the protrusion (crater: 45d) of the emitter electrode 45a is opened, and a through hole 45e is formed in the protrusion 45d. This etch-back is formed by anisotropic dry-etching. The Madronon RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr.

Next, a resist mask (not shown) is formed on the emitter electrode 45a by a conventional photolithography method. Using this resist mask, the emitter electrode 45a is partially etched and removed to form the emitter electrode portions 45b and 45c and the slit opening 46 as shown in FIG. 7F. The slit opening 46 is formed by anisotropic dry-etching. The Madronon RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr. The process of FIG. 7E and the process of FIG. 7F may be interchanged.

Next, as shown in FIG. 7G, portions of the first and second sacrificial films 40c and 44 are isotropically wet-etched and removed through the slit-shaped openings 46 to emitter electrodes 45b and 45c. ), The gate electrode 41a, the second gate electrode 43a and the anode electrode 40b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F.

The slit-shaped openings 46 formed in the process shown in FIG. 7F may not be formed. In this case, after the process shown in Fig. 7E, portions of the first and second sacrificial films 40c and 44 are isotropically wet-etched to be removed through the protrusion 45d, and the emitter electrode 45a. The gate electrode 41a, the second gate electrode 43a, and the anode electrode 40b are exposed to complete the three-electrode element shown in FIG. 7H. SiO ₂ is etched by HF + NH ₄ F.

8A and 8B are cross-sectional views showing a modified example of the fourth embodiment of the present invention. As shown in Fig. 8A, the first and second sacrificial films 40c and 44 use the emitter electrode of the field emission device formed by the process up to that shown in Fig. 7E of the fourth embodiment as a mask, It is anisotropically etched in the depth direction through the projection 45d of the emitter electrode 45a. This anisotropic dry-etching is performed by using a magnetron RIE system using CHF ₃ + CO ₂ + Ar as the etching gas at a reaction pressure of 50 mTorr.

A portion of the first and second sacrificial films 40c and 44 is isotropically wet-etched and removed through the protrusion 45d of the emitter electrode 45a, and the emitter electrode 45a and the gate electrode ( 41a), the lateral space forming portion 43a and the anode electrode 40b are exposed to complete the three-electrode element shown in FIG. 8B. SiO ₂ is etched by HF + NH ₄ F.

According to the fourth embodiment of the present invention, in addition to the advantages of the second embodiment, the electric field strength is increased at the tip of the emitter because the side space forming portion 43a of the conductive material remains as the second gate electrode, and the device performance is improved. This is improved.

9A to 9I are views for explaining the manufacturing steps of the two-electrode field emission device according to the fifth embodiment of the present invention. As shown in FIG. 9A, a gate electrode film 51 is formed on a single layer substrate made of glass or quartz or a substrate 50 which is a stack of Si and Si oxide films. The gate electrode 51 is formed of a polycrystalline silicon film doped with P (phosphorus) or B (boron) and has a thickness of 0.01 μm.

The polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into the film forming chamber at a substrate temperature of 625 ° C. Thereafter, for the purpose of reducing the resistance of the film, P or B is introduced into the polycrystalline silicon film by diffusion or implantation.

Next, as shown in FIG. 9A, a first sacrificial film (insulation film) 52 is formed on the gate electrode film 51. For example, the first sacrificial film 52 is formed to a thickness of 0.2 占 퐉 by depositing an Si oxide film on the gate electrode film 51 using O ₃ and TEOS as source gas at a substrate temperature of 400 ° C.

Next, a resist film (not shown) is formed on the entire surface of the first sacrificial film 52 by the photolithography method. Using a resist pattern as a mask, the first sacrificial film 52 is anisotropically etched, and as shown in FIG. 9B, the first sacrificial film 52a having a predetermined pattern together with the concave portion (through hole 53). ) Is left. The concave portion (through hole) 53 has a vertical inner wall, and its shape (as viewed in plan view) is circular having a diameter of 0.5 mu m and a depth of about 0.2 mu m.

Next, as shown in FIG. 9C, a second sacrificial film (insulation film) 54 is formed on the surfaces of the first sacrificial film 52a and the gate electrode film 51 exposed to the concave portion (through hole 53). Is formed. The second sacrificial film 54 is made of SiO ₂ deposited to a thickness of 0.15 mu m by atmospheric pressure CVD, for example, under conditions using O ₃ and TEOS as source gas at a substrate temperature of 400 deg.

Next, as shown in FIG. 9D, the second sacrificial film 54 is anisotropically dry-etched (etched-back) so that only the inner wall of the recess (through hole 53) of the first sacrificial film 52a is provided. A part of the second sacrificial film 54 is left as the side space forming portion 54a.

This etching is performed using a magnetron RIE system, for example, under conditions using a reaction chamber pressure of 50 mTorr and a CHF ₃ + CO ₂ + Ar etching gas. The gate electrode film 51 is etched using the first sacrificial film 52a and the side space forming portion 54a as a mask. This etching is performed by using magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

Next, as shown in Fig. 9E, a third sacrificial film made of an oxide film (insulating film 55) is isotropically deposited on the entire substrate surface by a thickness of 0.1 mu m by the atmospheric pressure CVD method. This film is formed at a substrate temperature of 400 ° C. using, for example, TEOS and O ₃ as source gas. The deposited third sacrificial film 55 forms the surface shapes of the side space forming part 54a and the substrate 50.

Next, as shown in FIG. 9F, for example, an emitter electrode film 56 made of TiN _x is deposited to a thickness of 0.2 μm on the third sacrificial film 55 by reactive sputtering. Reactive sputtering is formed using a DC sputtering system, for example, under conditions of supply of Ti target and N ₂ + Ar gas.

Next, as shown in FIG. 9G, the emitter electrode film 56 is etched back by about 0.1 μm to remove the emitter electrode film 56 only on the bottom of the recess (through hole 53). 3 is left as the emitter electrode 56a on the upper surface and the inner wall of the sacrificial film 55. This etch-back is formed by anisotropic dry-etching. The magnetron RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr.

Next, as shown in FIG. 9H, portions of the substrate 50, the lateral space forming portion 54a, and the third sacrificial film 55 are etched away to form the gate electrode 51a and the emitter electrode 56a. By exposing, a two-electrode element is formed. When the substrate 50 is formed of Si, it is etched using HF + HNO ₃ + CH ₃ COOH. The silicon oxide film and the like are etched by HF + NH ₄ F. The emitter electrode 56a includes a base 56c and a protrusion (volcano crater-shaped portion 56d). This projecting portion (crater 56d) has a through hole 56e.

FIG. 9I is a cross-sectional view illustrating a process of attaching the support substrate 57 to the emitter electrode 56a by electrostatic bonding to impart mechanical strength to the emitter electrode 56a before the process of FIG. 9H. In this case, after the process of adhering the support substrate, unnecessary portions such as the substrate are removed by the etching process of Fig. 9H.

When the same gate-emitter voltage is applied, the electric field becomes stronger at the tip of the emitter electrode shown in FIG. 5I, enabling lower voltage electron emission. However, since the distance between the emitter electrode 35a and the side space forming portion 33a is short, circuit shorting and leakage are likely to occur. On the other hand, although the emitter electrode shown in Fig. 9I is inferior in the low voltage electron emission portion compared to the emitter electrode shown in Fig. 5I, the margin for preventing short circuit and leakage can be increased.

10A and 10B are cross-sectional views illustrating a modified example of the fifth embodiment of the present invention. This variant is intended to provide another method of reinforcing the emitter electrode 56a with a supporting substrate. The fourth sacrificial film 58 is formed on the emitter electrode 56a of the fifth embodiment obtained in the process of Fig. 9G. The fourth sacrificial film 58 is made of polycrystalline silicon deposited by low pressure CVD. For the purpose of lowering the resistance value, impurity ions such as P and B can be introduced into the polycrystalline silicon by ion implantation, thermal diffusion, or the like.

Next, as shown in Fig. 10A, the concave portion on the fourth sacrificial film 58 is filled with a planarization film 59 made of SOG, for example. This planarization film 59 is planarized by CMP or etching (etching-back). Instead of the SOG, the planarization film 59 may be formed by reflowing the PSG or the BPSG.

Next, the support substrate 57 is adhered to the fourth sacrificial film 58 by the planarization film 59 by electrostatic bonding.

Next, unnecessary portions such as the substrate 50 are etched away by an etching process similar to that of FIG. 5H to expose the tip of the emitter electrode and the gate electrode 51 as shown in FIG. Create and complete the device. This emitter electrode 56a also includes a base 56c and a protrusion 56d, through which a passing hole 56e is formed.

11A to 11H are cross-sectional views illustrating a manufacturing step of a three-electrode type field emission device according to a sixth embodiment of the present invention.

As shown in Fig. 11A, the anode electrode 60b is deposited to a thickness of 0.15 mu m by the low pressure CVD method or sputtering on the start substrate 60a made of the Si oxide film. This anode electrode 60b is made of polycrystalline silicon or amorphous silicon doped with P or B.

Next, a first sacrificial film (insulation film: 60c) made of SiO ₂ is deposited on the anode electrode 60b with a thickness of 0.2 탆 by the CVD method. On this substrate 60, a gate electrode film 61 is deposited to a thickness of 0.1 mu m by low pressure CVD or sputtering. This gate electrode film 61 is made of polycrystalline silicon or amorphous silicon doped with P or B. A second sacrificial film (insulation film) 62 is deposited on the gate electrode film 61 with a thickness of 0.2 탆.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the second sacrificial film 62 by photolithography. Using the resist pattern as a mask, the second sacrificial film 62 is anisotropically etched, and the second sacrificial film 62a having a predetermined pattern together with the concave portion (through hole 63) as shown in Fig. 11A. ) Is left. The shape (viewed in plan view) of the concave portion (through hole 63) is circular having a diameter of 0.5 탆 and a depth of about 0.2 탆.

This etching is formed using a magnetron RIE system, for example, under conditions using a reaction chamber pressure of 50 mTorr and a CHF ₃ + CO ₂ + Ar etching gas. It is preferable that the bottom of the substrate 60 be cooled to He in order to prevent the resist from softening by the temperature rise during the etching process.

Next, a third sacrificial film 64 made of an Si oxide film was applied to the surface of the gate electrode 61 and the second sacrificial film 62a exposed to the concave portion (through hole 63) at a thickness of 0.15 占 퐉 in the atmospheric pressure CVD method. Is deposited. This third sacrificial film 64 is formed at a substrate temperature of 400 ° C. using TEOS + O ₃ as the source gas, for example.

Next, as shown in FIG. 11B, the third sacrificial film 64 is anisotropically dry-etched (etched-back) to remove a portion of the third sacrificial film 64 as the lateral space forming portion 64a. Only the inner wall of the sacrificial film 62a is left. Next, using the second sacrificial film 62a and the side space forming portion 64a as a mask, the gate electrode film 61 is etched by anisotropic dry etching. This dry etching is performed using a magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

Next, as shown in Fig. 11C, a fourth sacrificial film (insulation film: 65) made of SiO ₂ is isotropically deposited to a thickness of 0.15 mu m by the atmospheric pressure CVD method on the entire substrate surface. This film is formed using, for example, TEOS and O ₃ as source gas at a substrate temperature of 400 ° C.

Next, as shown in FIG. 11D, the emitter electrode film 66 made of TiN _x , for example, is DC on the fourth sacrificial film 65 under a supply of a target of Ti and N ₂ + Ar gas at a thickness of 0.2 μm. It is formed using a sputtering system.

Next, as shown in Fig. 11E, the emitter electrode film 66 is etched back by 0.1 mu m, so as to completely remove the emitter electrode film 66 only on the bottom of the recess (through hole 63). The emitter electrode 66a is left on the inner wall and the upper surface of the fourth sacrificial film 65. The emitter electrode 66a includes a base 66c and a protrusion (like a crater of volcano: 66d). By this etching-back, the tip of the protrusion (crater: 66d) of the emitter electrode 66a is opened, and the through hole 66e is formed in the protrusion of the emitter electrode 66a. This etch-back is formed by anisotropic dry etching. The magnetron RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr.

Next, a resist mask (not shown) is formed on the emitter electrode 66a by a conventional photolithography method. Using this resist mask, the emitter electrode 66a is partially etched away and removed to form the emitter electrode portions 66b, 66c and the slit opening 67 as shown in FIG. 11F. The slit-shaped opening 67 is formed by anisotropic dry-etching. The Madronon RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr. The process of FIG. 11E and the process of FIG. 11F may be interchanged.

Next, as shown in FIG. 11G, portions of the first and fourth sacrificial films 60c and 65 are isotropically wet-etched and removed through the slit-shaped opening 67 to emit emitter electrodes 66b and 66c. ), The gate electrode 61a and the anode electrode 60b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F.

The slit-like opening 67 formed in the process shown in FIG. 11F may not be formed. In this case, after the process shown in Fig. 11E, portions of the first and fourth sacrificial films 60c, 65 are isotropically wet-etched and removed through the projections 66d, 3 shown in Fig. 11H. Complete the electrode element. SiO ₂ is etched by HF + NH ₄ F.

12A to 12B are cross-sectional views for explaining a modification according to the sixth embodiment of the present invention. As shown in Fig. 12A, the first and fourth sacrificial films 60c and 65 have already used the emitter electrode of the field emission device formed by the process up to the process shown in Fig. 11E of the sixth embodiment as a mask. It is anisotropically etched in the depth direction through the projection 66d of the electrode electrode 66a. For example, this anisotropic dry-etching is performed by using a magnetron RIE system using CHF ₃ + CO ₂ + Ar as an etching gas at a reaction pressure of 50 mTorr.

In addition, a portion of the lateral space forming portion 64a and the first and fourth sacrificial films 60c and 65 are isotropically wet-etched and removed through the protrusion 66d of the emitter electrode 66a, and the emitter is removed. The electrode 66a, the gate electrode 61a and the anode electrode 60b are exposed to complete the three-electrode element shown in FIG. 12B. SiO ₂ is etched by HF + NH ₄ F.

13A to 13I are cross-sectional views illustrating a manufacturing step of a two-electrode field emission device according to a seventh embodiment of the present invention.

As shown in Fig. 13A, a gate electrode film 71 is formed on a substrate 70 which is a single layer substrate made of glass or quartz or a stack of Si and Si oxide films. The gate electrode 71 is formed of a polycrystalline silicon film doped with P or B and has a thickness of 0.01 μm.

The polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into a film formation chamber (reaction chamber) at a substrate temperature of 625 ° C. Thereafter, for the purpose of reducing the resistance of the film, P or B is introduced into the polycrystalline silicon film by diffusion or implantation.

Next, as shown in FIG. 13A, a first sacrificial film (insulation film) 72 is formed over the gate electrode film 71. For example, the first sacrificial film 52 is formed to a thickness of 0.2 占 퐉 by depositing an Si oxide film on the gate electrode film 71 using O ₃ and TEOS as source gas at a substrate temperature of 400 ° C.

Next, a resist film (not shown) is formed on the entire surface of the first sacrificial film 72 by the photolithography method. Using a resist pattern as a mask, the first sacrificial film 72 is anisotropically etched, and as shown in FIG. 13B, the first sacrificial film 72a having a predetermined pattern together with the concave portion (through hole 73). ) Is left. The concave portion (through hole 73) has a vertical inner wall, and the shape is circular having a diameter of 0.5 mu m and a depth of about 0.2 mu m (as viewed in plan view).

Next, as shown in FIG. 13C, a second sacrificial film (insulation film) 74 is formed on the surfaces of the first sacrificial film 72a and the gate electrode film 71 exposed to the recessed portion (through hole 53). Is formed. The second sacrificial film 74 is made of SiO ₂ deposited to a thickness of 0.15 mu m by atmospheric pressure CVD, for example, under conditions using O ₃ and TEOS as source gas at a substrate temperature of 400 deg.

Next, as shown in FIG. 13D, the second sacrificial film 74 is anisotropically dry-etched (etched-back) so that only the inner wall of the concave portion (through hole 73) of the first sacrificial film 72a is provided. A part of the second sacrificial film 74 is left as the side space forming part 74a.

This etching is performed using a magnetron RIE system, for example, under conditions using a reaction chamber pressure of 50 mTorr and a CHF ₃ + CO ₂ + Ar etching gas.

Next, as shown in FIG. 13D, using the first sacrificial film 72a and the side space forming portion 74a as a mask, the gate electrode film 71 is etched to form a gate electrode having a predetermined pattern with holes. It forms 71a.

Next, as shown in Fig. 13E, a third sacrificial film (insulation film) 75 made of a Si oxide film is isotropically deposited on the entire substrate surface by a thickness of 0.1 mu m by the atmospheric pressure CVD method. This film is formed at a substrate temperature of 400 ° C. using, for example, TEOS and O ₃ as source gas.

Next, as shown in FIG. 13F, for example, an emitter electrode film 76 made of TiN _x is deposited to a thickness of 0.2 μm on the third sacrificial film 75 by reactive sputtering. Reactive sputtering is formed using a DC sputtering system, for example, under conditions of supply of TiN _x target and N ₂ gas. Conventional sputtering or deposition may be used. The first emitter electrode film 76 may be formed of a metal such as Ti, W, Mo, Ni, Cr, Au, Pt, Pd, Ag, or an alloy such as TiO _x N _y , TiW _x, and CrN _x . .

Next, as shown in FIG. 13G, the first emitter electrode film 76 is etched back by about 0.1 [mu] m to remove the emitter electrode film 76 only on the bottom of the recess (through hole 73). It is completely removed to leave the emitter electrode 76a on the upper surface and the inner wall of the third sacrificial film 75. This etch-back is formed by anisotropic dry-etching. The magnetron RIE system can be used, for example, using Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr. The first emitter electrode 76a includes a base portion 76c, a projection portion (crater: 76d), and a through hole 76e formed in the projection portion 76d.

Next, as shown in FIG. 13H, a second emitter electrode film 77 is formed on the surfaces of the first emitter electrode 76a and the third sacrificial film 75. The second emitter electrode film 77 is coated with, for example, independent dispersible ultrafine particles such as Au, Pt, Pd, Ag, and the like, and these are coated with a temperature in the range of 200 ° C to 300 ° C or more preferably 200 ° C. It is formed by baking at the following temperature. This through hole 76e is filled with freely dispersible ultrafine particles. Instead of coating the ultrafine particles, a dry method using a jet printing system may be used to directly draw the autonomous superfine particles on the surface of the third sacrificial film 75 and the first emitter electrode 76a. . Instead of using ultra-fine particles, the metal material may be plated. Other materials, for example, Al, Cr, Ni, Mo, and Hf are used by sputtering and vapor deposition, or W, Cu, Al, and the like are used by CVD to form the second emitter electrode film 77. It may be formed.

Next, as shown in FIG. 13I, portions of the substrate 70, the lateral space forming portion 74a, and the first and third sacrificial films 72a and 75 are etched away to expose the emitter electrode 76a. To form a two-electrode element. When the substrate 70 is formed of Si, it is etched using HF + HNO ₃ + CH ₃ COOH. The silicon oxide film and the like are etched by HF + NH ₄ F.

In the example shown in FIG. 14C, after the process of FIG. 13H, the second emitter electrode film 77 is etched back by ion milling or the like to pass through the hole 76e of the first emitter electrode 76a. ), Leaving the second emitter electrode 77a only, and prior to the process of removing unnecessary portions such as the substrate 70 as shown in FIG. It is adhered to the electrodes 76a and 77a to impart mechanical strength to the emitter electrode.

FIG. 21C is a cross-sectional view showing in detail the process of baking the independent dispersed ultrafine particles as shown in FIG. 13H. Although large voids 79 are formed in the ultrafine particles and the second emitter electrode 77 is disconnected by the voids, electrical conduction is caused by the first emitter electrode 76a so that a voltage is applied to the emitter tip. Can be applied. Conventional emitter electrodes formed by baking ultra-fine particles do not have the first emitter electrodes of this embodiment, and therefore voids can be fatal defects.

14A and 14B show a modification of the seventh embodiment of the present invention. This variant provides another method of reinforcing the emitter electrode 76a with a support substrate. As shown in Fig. 14A, the support substrate 78 is bonded to the second emitter electrode film 77 of the element formed in the process shown in Fig. 13H of the seventh embodiment.

Although not shown, if the support substrate 78 is made of an insulating film such as glass, quartz, or the like, the second substrate is formed by depositing TiN _x to a thickness of 0.2 μm by reactive sputtering and adhering the support substrate 78 to the adhesive layer. It is preferable to form an adhesive or adhesive layer on the emitter electrode 77. This reactive sputtering is preferably performed by a DC sputtering system using Ti as the target and introducing N ₂ + Ar gas. If conventional sputtering is used, TiN _x is preferably used as the sputtering target while the N ₂ gas is introduced. Deposition methods may be used. This adhesive layer can be made using metals such as Ti, W, Mo, Ni, Cr, Au, Pt, Pd and Ag or alloys such as TiO _x N _y , TiW _x , and CrN _x .

Next, unnecessary portions of the substrate 70 and the like are removed by an etching process similar to that shown in FIG. 13I, thereby completing the field emission device by exposing the tip portion of the emitter electrode shown in FIG. 14B.

15A to 15H are cross-sectional views illustrating manufacturing steps of the field emission device according to the eighth embodiment of the present invention.

As shown in Fig. 15A, the anode electrode 80b is deposited to a thickness of 0.15 mu m by a low pressure CVD method or sputtering on a start substrate 80a made of a Si oxide film. This anode electrode 80b is made of polycrystalline silicon or amorphous silicon doped with P or B.

Next, a first sacrificial film 80c made of SiO ₂ is deposited on the anode electrode 80b to form a substrate 80. On this substrate 60, a gate electrode film 81 made of polycrystalline silicon or amorphous silicon doped with P or B is deposited to a thickness of 0.1 mu m, and a second sacrificial film (insulating film 82) is formed on the gate electrodes. This thickness is deposited to 0.2 탆.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the second sacrificial film 82 by photolithography. Using the resist pattern as a mask, the second sacrificial film 82 is anisotropically etched, and the second sacrificial film 82a having a predetermined pattern together with the concave portion (through hole 83) as shown in Fig. 15A. ) Is left. The shape of the concave portion (through hole 83) (viewed from the top view) is circular having a diameter of 0.5 mu m and a depth of about 0.2 mu m.

This etching is formed using a magnetron RIE system, for example, under conditions using a reaction chamber pressure of 50 mTorr and a CHF ₃ + CO ₂ + Ar etching gas. The bottom of the substrate 80 is preferably cooled to He in order to prevent the resist from softening by the temperature rise during the etching process.

Next, the third sacrificial film 84 made of an Si oxide film was applied to the surface of the gate electrode 81 and the second sacrificial film 82a exposed to the concave portion (through hole 83) at a thickness of 0.15 占 퐉 in the atmospheric pressure CVD method. Is deposited. This third sacrificial film 84 is formed at a substrate temperature of 400 ° C. using, for example, O ₃ + TEOS as the source gas.

Next, as shown in FIG. 15B, the third sacrificial film 84 is anisotropically dry-etched (etched-back) to remove a portion of the third sacrificial film 84 as the lateral space forming portion 84a. Only the inner wall of the sacrificial film 82a is left. Next, using the second sacrificial film 82a and the side space forming portion 84a as a mask, the gate electrode film 81 is etched by anisotropic dry etching to form a gate electrode 81a having a through hole. This dry etching is performed using a magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

Next, as shown in Fig. 15C, a fourth sacrificial film made of SiO ₂ (insulating film: 85) isotropically deposited to a thickness of 0.15 mu m by the atmospheric pressure CVD method on the entire substrate surface. This film is formed using, for example, TEOS and O ₃ as source gas at a substrate temperature of 400 ° C.

Next, as shown in FIG. 15D, the emitter electrode film 86 made of TiN _x , for example, is 0.2 μm thick on the fourth sacrificial film 85 under a target of Ti and N ₂ + Ar gas supply conditions. It is formed using a DC sputtering system.

Next, as shown in FIG. 15E, the first emitter electrode film 86 is etched back by 0.1 μm so that the first emitter electrode film 86 is only on the bottom of the recess (through hole 83). ) Is completely removed and the emitter electrode 86a is left on the inner wall and the upper surface of the fourth sacrificial film 85. The emitter electrode 86a includes a base 86c and a protrusion (crater 86d). By this etching-back, the tip of the protrusion (crater: 86d) of the emitter electrode 86a is opened, and the through hole 86e is formed in the protrusion of the emitter electrode 86a. This etch-back is formed by anisotropic dry etching. The magnetron RIE system may consider using Cl ₂ as an etching gas, for example, at a reaction chamber pressure of 125 mTorr.

Next, as shown in FIG. 15F, a second emitter electrode film 87 is formed on the surfaces of the first emitter electrode 86a and the third sacrificial film 85. The second emitter electrode film 87 is coated by coating, for example, independent dispersible ultrafine particles such as Au, Pt, Pd, Ag, and the like, and these are in the range of 200 ° C to 300 ° C or more preferably 200 ° C. It is formed by baking at the following temperature. Instead of applying the ultrafine particles, a dry method using a spray printing system may be used to directly draw the autonomous particulates on the surfaces of the third sacrificial film 85 and the first emitter electrode 86a. Instead of using ultra-fine particles, the metal material may be plated. Other materials, for example, Al, Cr, Ni, Mo, and Hf are used by sputtering and vapor deposition, or W, Cu, Al, and the like are used by CVD to form the second emitter electrode film 87. It may be formed.

Next, a resist mask (not shown) is formed on the emitter electrode 87 by a conventional photolithography method. Using this resist mask, the first and second emitter electrodes are partially etched away to form slit openings 89 as shown in FIG. 15G, and the first on both sides of the slit openings 89. Emitter electrode portions 86a and 87b and second emitter electrode portions 86c and 87c are formed. The slit-like opening 89 is formed by ion milling under the conditions of, for example, an Ar gas, an acceleration energy of 700 eV, a current of 800 mA, and an ion beam having an inclination angle of 0 degrees (reference normal direction).

Next, as shown in FIG. 15H, portions of the lateral space forming portion 84a and the first and fourth sacrificial films 80c and 85 are isotropically wet-etched and removed through the slit-shaped opening 89. The emitter electrodes 86b and 86c, the gate electrode 81a and the anode electrode 80b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F.

16A, 16B and 16C are cross sectional views showing modifications of the eighth embodiment. As shown in Fig. 16A, the second emitter electrode 87 of the element formed by the process up to that shown in Fig. 15F of the eighth embodiment is etched back by ion milling or the like to make the first emitter electrode 86a The second emitter electrode 87a is left only through the hole of the &lt; RTI ID = 0.0 &gt;

Next, a resist mask (not shown) is formed over the first and second emitter electrodes 86a and 87a by a conventional photolithography method. Using this resist mask, the first and second emitter electrodes are partially etched away to form a slit opening 89 as shown in FIG. 16B, and the first on both sides of the slit opening 89. Emitter electrode portions 86b and 86c are formed. This slit-like opening 89 is formed by anisotropic dry-etching, for example, using a magnetron RIE system using Cl ₂ as an etching gas in a 125 mTorr reaction chamber.

Next, as shown in FIG. 16C, portions of the lateral space forming portion 84a and the first, second and fourth sacrificial films 80c, 82a, and 85 are isotropically through the slit-shaped opening 89. It is wet-etched and removed, and the first and second emitter electrodes 86b and 87a, the gate electrode 81a and the anode electrode 80b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F. The first emitter electrode 86a has a base portion 86c and a protrusion portion 86d, and a through hole 86e is formed in the protrusion portion 86d.

17A to 17I are cross-sectional views illustrating a manufacturing step of a two-electrode field emission device according to a ninth embodiment of the present invention.

As shown in Fig. 17A, a first gate electrode film 91 is formed on a substrate 90 made of Si, for example. It is preferable to form a silicon oxide film or a silicon nitride film between the silicon substrate 90 and the polycrystalline silicon first gate electrode film 91, which is used as an etching stopper when the first gate electrode film is etched. The gate electrode 31 is formed of a polycrystalline silicon film doped with P (phosphorus) or B (boron) to have a thickness of 0.15 탆.

This polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into 0.6 slm under a temperature of 625 ° C. and a pressure of 30 Pa. Thereafter, POCl ₃ = 50 mg / min, N ₂ = 20 slm and O ₂ = 0.1 slm are introduced in a vertical diffusion furnace at a temperature of 850 ° C. for the purpose of lowering the resistance of the film, thereby diffusing P into the polycrystalline silicon film. .

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the first gate electrode film 91 by the photolithography method. Then, using the resist pattern as a mask, the first gate electrode film 91 is anisotropically etched to form a first gate electrode having a predetermined pattern including recesses (through holes 92) as shown in FIG. 91a). This recess (through hole 92) generally has a vertical inner wall, and its shape (on plan view) is circular with a diameter of 0.5 mu m and a depth of about 0.15 mu m.

Next, as shown in FIG. 17C, the substrate 90 and the first gate electrode exposed to the concave portion (through hole 92) such that the polycrystalline silicon film doped with P or B has a thickness of 0.15 μm by low pressure CVD. By depositing on the surface of 91a, the second gate electrode film 93 is formed. This polycrystalline silicon film is formed by, for example, introducing SiH ₄ gas diluted with He into the film forming chamber at a temperature of 625 ° C. and a pressure of 30 Pa at a flow rate of 0.6 slm. Thereafter, POCl ₃ = 50 mg / min, N ₂ = 20 slm, O ₂ = 0.1 slm is introduced into the vertical diffusion furnace at a temperature of 850 ° C. for the purpose of lowering the resistance value of the film to diffuse P into the polycrystalline silicon film. Instead of polycrystalline silicon, W silicide, Al alloy, TiN _x and the like can be used.

Next, as shown in FIG. 17D, the second gate electrode film 93 is anisotropically dry-etched (etched-back) and side-only on an inner wall of the recess (through hole 92) of the first gate electrode 91a. A part of the second gate electrode film 93 is left as the space forming portion 93a. By this etching, the surface of the gate electrode 91a is exposed, and the surface of the substrate 90 in the recess (through hole 92) is exposed.

This etching is performed by using magnetron RIE using HBr as an etching gas, for example, at a reaction chamber pressure of 100 mTorr.

Next, as shown in Fig. 17E, a first sacrificial film made of SiO ₂ (insulating film 94) is deposited on the entire substrate surface by the atmospheric pressure CVD method at a thickness of 0.1 mu m on the entire substrate surface. This film is formed at a substrate temperature of 400 ° C., for example, using TESO and O ₃ as source gas. The first sacrificial film 94 is left on the surfaces of the first gate electrode 91a and the side space forming portion 93a (to match).

Next, as shown in FIG. 17F, an emitter electrode film 95 made of TiN _x , for example, is deposited to a thickness of 0.15 μm on the first sacrificial film 94 through reactive sputtering. Reactive sputtering is performed under the conditions of a DC sputtering system, for example, under a target of Ti and a supply condition of N ₂ + Ar gas. Next, as shown in FIG. 17G, the emitter electrode film 95 is etched back by 0.1 μm so that the emitter electrode film 95 is completely removed only at the bottom of the recess (through hole 92). One remains as an emitter electrode 95a on the side and top surface of the sacrificial film 94. This etch-back is performed by anisotropic dry-etching. The magnetron RIE system uses Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr.

Next, as shown in FIG. 17H, a second emitter electrode film 96 is formed on the surfaces of the first emitter electrode 95a and the first sacrificial film 94. The second emitter electrode film 96 is coated with, for example, independent dispersible ultrafine particles such as Au, Pt, Pd, Ag, and the like, and these are coated with a temperature in the range of 200 ° C to 300 ° C, more preferably 200 ° C. It is formed by baking at the following temperature. Instead of coating the ultrafine particles, a self-dispersible ultrafine particle may be directly drawn on the surfaces of the first sacrificial film 94 and the first emitter electrode 95a by a dry method using a spray printing system. Instead of using ultra-fine particles, the metal material may be plated. Other materials, for example, Al, Cr, Ni, Mo, and Hf are used by sputtering and vapor deposition, or W, Cu, Al, and the like are used by CVD to form the second emitter electrode film 96. It may be formed.

Next, as shown in FIG. 17I, a portion of the substrate 90 and the first sacrificial film 94 are removed by etching to form the first gate electrode 91a, the side space forming part 93a, and the first emitter electrode. 95a is exposed to complete the two-electrode element. If the substrate 70 is formed of Si, it is etched using HF + HNO ₃ + CH ₃ COOH. The silicon oxide film and the like are etched by HF + NH ₄ F.

21B is a cross-sectional view showing in detail the process of baking the independent dispersible ultrafine particles shown in FIG. 17H of the present invention. Although a large void 98 is formed in the ultrafine particles, and the second emitter electrode 96 is disconnected by the void, electrical conduction is made by the first emitter electrode 95a so that a voltage is applied to the emitter tip. Be sure to The conventional emitter electrode formed by baking independent dispersible ultrafine particles does not have the first emitter electrode of this embodiment, so that voids can become a fatal defect.

18A and 18B show a modification of the ninth embodiment. This variant provides a method of strengthening the emitter electrode 96 with a support substrate. As shown in Fig. 18A, a support substrate 97 is adhered to the second emitter electrode 96 of the element formed in the process shown in Fig. 17H of the ninth embodiment.

Although not shown, if the support substrate 97 is made of an insulating film such as glass and quartz, TiN _x is deposited to a thickness of 0.2 μm by reactive sputtering to form an adhesive layer on the second emitter electrode 96. It is preferable to adhere the support substrate 97 to the adhesive layer. This reactive sputtering is performed by a DC sputtering system using Ti as the target and introducing N ₂ + Ar gas. If conventional sputtering is used, TiN _x is preferably used as the sputtering target while the N ₂ gas is introduced. Deposition methods may be used. This adhesive layer can be made using metals such as Ti, W, Mo, Ni, Cr, Au, Pt, Pd and Ag or alloys such as TiO _x N _y , TiW _x , and CrN _x .

Next, unnecessary portions such as the substrate 90 are removed by an etching process similar to that shown in FIG. 17I, and as shown in FIG. 18B, the first gate electrode 91a, the side space forming portion 93a, and The two-electrode field emission device is completed by exposing the tip of the first emitter electrode 95a.

19A to 19H are cross-sectional views illustrating a manufacturing step of a three-electrode field emission device according to a tenth embodiment of the present invention.

As shown in FIG. 19A, the anode electrode 100b is deposited to a thickness of 0.15 μm by low pressure CVD or sputtering on a starting substrate 100a made of an insulating material. Here, the start substrate 100a is made of a silicon oxide film, and the anode electrode 100b is made of polycrystalline silicon or amorphous silicon doped with P and B.

Next, a first sacrificial film (insulation film 100c) of SiO ₂ is deposited on the anode electrode 100b by CVD to obtain a substrate 100. On this substrate 100, a gate electrode film 101 made of polycrystalline silicon or amorphous silicon doped with P or B is formed to a thickness of 0.3 탆 by sputtering.

Next, a resist film (not shown) having a predetermined pattern is formed on the entire surface of the gate electrode film 101 by the photolithography method. Using this resist pattern as a mask, the gate electrode film 101 is anisotropically etched to leave the gate electrode 101a having a predetermined pattern including recesses (pass holes 102) as shown in Fig. 19A. The shape (on plan view) of the recessed portion (through hole 102) is of a cylindrical shape having a diameter of 0.5 mu m and a depth of 0.3 mu m.

This etching is performed, for example, by dry-etching using magnetron RIE using HBr as the etching gas at a reaction chamber pressure of 100 mTorr.

Next, processes are performed similar to those of the third embodiment shown in FIGS. 5C and 5D, so that only Si is formed on the inner wall of the recess (through hole 102) of the gate electrode 101a as shown in FIG. 19B. Alternatively, the side space forming part 103a made of another conductive material may be formed.

Next, a second sacrificial film made of SiO ₂ (insulating film 104) is deposited to a thickness of 0.15 mu m on the entire surface of the substrate by the atmospheric pressure CVD method. For example, this second sacrificial film 104 is formed at a substrate temperature of 400 ° C. using O ₃ + TEOS.

Next, as shown in FIG. 19D, the emitter electrode film 105 is made of TiN _x , for example, and is formed on the second sacrificial film 104 to a thickness of 0.2 μm by reactive sputtering. For example, a DC sputtering system can be used under the conditions of supplying Ti target and N 2 + Ar gas.

Next, as shown in FIG. 19E, the emitter electrode film 105 is etched back by 0.1 占 so that it is completely removed only on the bottom of the recess (through hole 22), and the second sacrificial film 104 is provided. The emitter electrode 105a is left on the inner wall and the top surface of the substrate. The first emitter electrode 15a includes a base 105c and a protrusion (crater 105d). With this etching-back, the tip of the protrusion 105d of the emitter electrode 105a is opened, and a through hole 105e is formed in the protrusion 105d. Etch-back is performed by anisotropic dry-etching. For example, the magnetron RIE system uses Cl ₂ as an etching gas at a reaction chamber pressure of 125 mTorr.

Next, as shown in FIG. 19F, a second emitter electrode film 106 is formed on the surfaces of the first emitter electrode 105a and the second sacrificial film 104. The second emitter electrode film 106 is coated by coating, for example, self-dispersible ultrafine particles such as Au, Pt, Pd, Ag, and the like, and these are coated with a temperature in the range of 200 ° C to 300 ° C or more preferably 200 ° C. It is formed by baking at the following temperature. Instead of coating the ultrafine particles, a self-dispersible ultrafine particle may be directly drawn on the surfaces of the second sacrificial film 104 and the first emitter electrode 105a by a dry method using a spray printing system. Instead of using ultra-fine particles, the metal material may be plated. Other materials, for example, Al, Cr, Ni, Mo, and Hf are used by sputtering and vapor deposition, or W, Cu, Al, and the like are used by CVD to form the second emitter electrode film 106. It may be formed.

Next, a resist mask (not shown) is formed over the second emitter electrode 106 by a conventional photolithography method. Using this resist mask, the first and second emitter electrodes are partially etched away to form slit openings 107 as shown in FIG. 19G and the first on both sides of the slit openings 107. And second emitter electrode portions 105a, 106a, 105c, 106c. The slit-shaped opening 107 is formed by ion milling under conditions of, for example, an Ar gas, an acceleration energy of 700 eV, a current of 800 mA, and an ion beam having an inclination angle of 0 degrees (reference normal direction).

Next, as shown in FIG. 19H, portions of the first and second sacrificial films 100c and 104 are isotropically wet-etched and removed through the slit-shaped opening 107, and the emitter electrode 105b is removed. The first gate electrode 101a, the side space forming part 103a, and the anode electrode 100b are exposed to complete the three-electrode element. SiO ₂ is etched by HF + NH ₄ F.

20A, 20B and 20C are sectional views showing the modification of the tenth embodiment. As shown in Fig. 20A, the second emitter electrode 106a of the element formed by the process up to that shown in Fig. 19F of the tenth embodiment is etched-back by ion milling or the like and the first emitter electrode 105a. The second emitter electrode film 106 is left only through the through hole.

Next, a resist mask (not shown) is formed over the first and second emitter electrodes 105a and 106c by a conventional photolithography method. Using this resist mask, the first and second emitter electrodes are partially etched away to form slit-shaped openings 108, first emitter electrode portions 105b, 105c as shown in FIG. 20B. This slit-like opening 108 is formed by anisotropic dry-etching using, for example, a magnetron RIE system using Cl ₂ as an etching gas in a reaction chamber of 125 mTorr.

Next, as shown in FIG. 20C, portions of the first and second sacrificial films 100c and 104 are isotropically wet-etched and removed through the slit-shaped opening 108 and the first and second images are already removed. The three-electrode elements are completed by exposing the electrode electrodes 105b and 106c, the side space forming portion 103a, the gate electrode 101a and the anode electrode 100b. SiO ₂ is etched by HF + NH ₄ F.

Fig. 22 is a perspective view of the three-electrode field emission device of the second embodiment shown in Fig. 3G of the present invention. The emitter electrode portion 25b is here supported by it in a continuous form with the emitter electrode portion 25c. The gate electrode 21a has a circular hole (gate hole) near the outer circumferential region of the tip of the emitter electrode 25b. The tip of the emitter electrode 25b has a volcano shape near the gate hole of the gate electrode 21a. The emitter electrode 25b has a base portion 25c and a protrusion (volcano crater portion 25d), and a through hole 25e is formed passing through the protrusion portion (crater: 25d).

This three-electrode element has an emitter electrode 25b as a cathode and an anode electrode 20b. As the positive potential is applied to the gate electrode 21a, electrons are emitted from the emitter electrode 25b toward the anode electrode 20b.

Fig. 23 is a sectional view of a flat panel display constructed using the field emission device of the above-described embodiment.

Each of the field emission devices used herein is a second electrode device formed by the manufacturing method of the first embodiment. On the support substrate 110 made of an insulating material, a wiring layer 111 made of Al, Cu or the like and a resistance layer 112 made of polycrystalline silicon or the like are formed. On the resistive layer 112, a plurality of emitter electrodes 113 having volcanic crater-shaped tips are arranged to form a field emitter array FEA. Each gate electrode 114 has a small opening (gate hole) near the tip of each emitter electrode 113 and is omitted in FIG. 23, but a voltage is applied independently to each gate electrode 114. It is supposed to be. A plurality of emitter electrodes 113 can also be applied independently to a constant voltage.

Facing the electron generating source including the emitter electrode 113 and the gate electrode 114, the opposing substrate is disposed including a transparent substrate made of glass, quartz or the like. The counter substrate is configured to include a transparent electrode (anode electrode) 116 made of ITO or the like placed under the transparent electrode 115, and a light emitting member 117 which is also placed under the transparent electrode 115.

The electron source and the counter substrate are made of a glass substrate, and the distance between the transparent electrode 116 and the emitter electrode 113 is maintained at about 0.1 mm to 5 mm through the space forming portion 119 coated with an adhesive. Combined.

Instead of the space forming portion 119 of the glass substrate, a space forming portion 119 made of an adhesive such as an epoxy resin having glass beads dispersed therein may be used.

The getter 120 is made of Ti, Al, Mg, and the like, and prevents the released gas from reattaching to the surface of the emitter electrode 113.

The air exhaust pipe 118 is coupled to the opposing substrate. By using this air exhaust pipe 118, the inside of the flat panel display is evacuated to about 10 ^-5 Torr to 10 ^-9 Torr, after which the air exhaust pipe 118 is sealed using a burner or the like. Thereafter, an anode electrode (transparent electrode) 116 is wired to the completed flat panel display.

The anode electrode 116 is always kept at a positive potential. Each display pixel is selected in two dimensions by emitter and gate wiring. That is, the field emission device disposed at the intersection of the emitter wiring to which the voltage is applied and the gate wiring is selected.

Negative and positive potentials are applied to the emitter electrode and the gate electrode, respectively, and electrons are emitted from the emitter electrode to the anode electrode. When electrons are emitted to the light emitting member 117, the emitted area (pixel) of the light emitting member emits light.

Semiconductors such as polycrystalline silicon, amorphous silicon or diamond may be used for the emitter electrode and the gate electrode, and include silicide compounds such as WSi _x TiSi _x and MoSi _x , Al, Cu, W, Mo, Ni. Metals such as Cr, Hf and TiN _x may be used.

In addition, the material of the sacrificial film, the insulating film, and the side space forming portion may be a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like.

As described above, the present invention has been described in detail with reference to the preferred embodiment. However, the present invention is not limited to the embodiment described above. For example, one of ordinary skill in the art to which the present invention pertains may perform various combination modifications and the like within the scope of the present invention.

As described above, according to the present invention, the electric field strength of the emitter can be increased by providing an opening at the tip of the emitter film. In addition, the tip of the emitter can be controlled in the height direction by the step of removing the emitter film at the bottom of the hole and providing the opening. In addition, if the emitter electrode is formed of the first emitter electrode film and the second emitter electrode film made of ultra-fine particles, disconnection can be prevented even if voids are generated.

Claims (45)

Support substrate; The support substrate having a base supported by and attached to the support substrate, a protrusion projecting from the base in a direction opposite to the support substrate, and an opening formed in a portion from the tip of the protrusion to the surface of the support substrate; A first emitter electrode formed on the substrate surface of the substrate; A first sacrificial layer formed at a base of the first emitter electrode and having an opening surrounding a peripheral area outside the protrusion; And And a gate electrode formed on the first sacrificial layer having an opening surrounding a peripheral area outside the protrusion. The field emission device according to claim 1, wherein the protrusion has a crater shape in which an inner diameter thereof gradually decreases toward the tip of the protrusion. The field emission device of claim 1, wherein a radius of curvature of the tip of the first emitter electrode protrusion is about 5 nm or less. The field emission device as claimed in claim 1, further comprising a second sacrificial film formed between the first emitter electrode and the support substrate in order to enhance the mechanical strength of the first emitter electrode. The field emission device as claimed in claim 1, further comprising a second emitter electrode deposited in the opening formed in the protrusion. The field emission device of claim 2, wherein the second emitter electrode is made of a conductive ultra-fine particle group. 3. The field emission device of claim 2, wherein the second emitter electrode is made of a metal deposited in the opening formed in the protrusion. The method of claim 2, wherein the second emitter electrode is an electrode made of any one of Al, Cr, Ni, Mo, Hf, W and Cu deposited in the opening formed in the protrusion of the first emitter electrode. A field emission device. 5. The field emission device as claimed in claim 4, wherein the second sacrificial film has a concave portion filled with a planarization material for flattening the surface of the second sacrificial film. Start board; An anode electrode formed on the surface of the starting substrate; A first sacrificial layer formed on the anode and having a first opening; A gate electrode formed on the first sacrificial layer, the gate electrode having a second opening portion concentric with the first opening portion; A second sacrificial layer formed on the gate electrode and having a third opening concentric with the first and second openings; And A first emitter formed on the second sacrificial film and having a base attached to the second sacrificial film, and protruding from the base into the first opening and the third opening and having a through hole therein; A field emission device comprising an electrode. The field emission device of claim 10, wherein the protrusion has a crater shape, and the inner diameter of the through hole decreases toward the anode electrode. The field emission device according to claim 10, wherein slit-shaped openings are formed at both sides of the protrusion of the first emitter electrode. The field emission device of claim 10, further comprising a side space forming portion formed on an inner wall of the second opening of the gate electrode, wherein the second sacrificial layer is formed on the gate electrode and the side space forming portion. device. A gate electrode having a first opening; A side space forming part formed on an inner wall of the first opening part; A first sacrificial film formed on the gate electrode and having a second opening portion concentric with the first opening portion; And A first image formed on the first sacrificial film and having a base supported by the first sacrificial film, and a protrusion having a through hole therein, protruding from the base toward the first opening and the second opening; A field emission device comprising a terminator electrode. The method of claim 14, And the side space forming portion is conductive. The method of claim 14, And the projecting portion has a crater shape in which its inner diameter moves away from the base portion with a predetermined direction and gradually decreases. The method of claim 14, And a support substrate for the base of the first emitter electrode. 15. The field emission device as claimed in claim 14, further comprising a support member attached to the base of the first emitter electrode. 17. The field emission device as claimed in claim 16, wherein the support member is partially filled in a skirt portion of the passage hole of the protrusion. The field emission device according to claim 13, wherein the side space forming portion is conductive. 15. The field emission device as claimed in claim 14, further comprising the second emitter electrode filled in the through hole. 22. The field emission device as claimed in claim 21, wherein the second emitter electrode is made of a conductive ultra-fine particle group. 22. The field emission device as claimed in claim 21, wherein the second emitter electrode is made of a metal deposited inside a through hole of the first emitter electrode. 22. The field emission of claim 21, wherein the second emitter electrode is made of any one of Al, Cr, Ni, Mo, Hf, W, and Cu deposited in the through hole of the first emitter electrode. device. 22. The field emission device as claimed in claim 21, wherein the second emitter electrode is deposited in the through hole. 27. The field emission device as claimed in claim 25, further comprising the second emitter electrode made of a group of conductive ultrafine particles deposited on the base and filled in the through hole. 27. The field emission device as claimed in claim 25, further comprising slit-shaped openings formed through first and second emitter electrodes on both sides of the protrusion. 27. The field emission device as claimed in claim 26, wherein the ultrafine particle group comprises any one of Au, Pt, Pd, and Ag. 27. The field emission of claim 26, wherein the second emitter electrode is made of any one of Al, Cr, Ni, Mo, Hf, W, and Cu deposited in the through hole of the first emitter electrode. device. 27. The field emission device as claimed in claim 25, wherein the second emitter electrode is not deposited on the base and is formed only in the through hole. The method of claim 25, Any of TiN _x , Ti, W, Mo, Ni, Cr, Au, Pt, Pd, Ag, TiO _x N _y , TiW _x , and CrN _x as a mediator between the second emitter electrode and the support substrate A field emission device comprising one material. The method of claim 25, And a side space forming portion formed on an inner wall of the second opening of the gate electrode. Support substrate; A wiring layer formed on the support substrate; A resistance layer formed on the wiring layer and made of a polycrystalline silicon layer; A plurality of emitter electrodes formed on the resistance layer and having a crater shape; A gate electrode formed near each tip of the malleable emitter electrode and having an opening; A transparent substrate facing the support substrate; An anode formed under the transparent substrate; A light emitting layer formed under the anode electrode; And And a space forming portion disposed between the support substrate and the transparent substrate at outer circumferences of the support substrate and the transparent substrate. (a) forming a surface layer comprising a conductive gate film on the substrate; (b) removing a portion of the surface layer to form a hole passing through the surface layer; (c) forming a side space forming portion made of a material of a first sacrificial film on the sidewall of the hole; (d) forming a second sacrificial film on the entire surface of the surface layer and the hole such that a flat surface of the second sacrificial film is formed at the bottom of the hole; (e) forming a conductive emitter film to have different thicknesses at different locations on the entire surface of the second sacrificial film; (f) removing the entire thickness of the emitter film from the bottom of the hole and anisotropically etching-back the entire surface of the emitter film to form a through hole in the emitter film; And (g) removing at least a portion of the substrate and the second sacrificial film so as to expose at least the vicinity of the tip of the emitter film. The method of claim 34, wherein The surface layer is made of only a gate film, and the step of removing a part of the surface layer in the step (b) forms a resist film having a predetermined pattern on the gate film, and using the resist pattern as a mask to Forming a side hole forming portion passing through the gate film downward toward the surface, wherein forming the side space forming portion of the step (c) forms a first sacrificial film on the entire surface of the gate film, And etching back the first sacrificial film to form a lateral space forming portion. The method of claim 34, wherein The surface layer includes the gate film and an insulating film formed on the gate film, and the step of removing a part of the surface layer in the step (b) forms a resist film of a predetermined pattern on the insulating film, and uses the resist film as a mask. And forming a side space forming portion in the step (c), forming a first sacrificial film on the entire surface of the gate film, and forming the side space forming portion on the inner wall of the hole. And forming a hole passing through the gate film by using the lateral space forming portion as a mask. The method of claim 34, wherein And the side space forming part is made of an insulating material. The method of claim 34, wherein The side space forming portion is a manufacturing method of the field emission device, characterized in that made of a conductive material. The method of claim 34, wherein And removing the substrate and part of the second sacrificial film in the step (g) comprises etching the side space forming part. The method of claim 34, wherein The step of forming the conductive emitter film of step (e) includes forming a first emitter film, and depositing conductive ultrafine particles on the first emitter film and baking the particles to form a second emitter film. Wherein the step of performing anisotropic etching-back of the step (f) comprises removing the first emitter film at least with respect to the bottom of the hole to form the through hole. Manufacturing method. The method of claim 40, The step of forming the conductive emitter film of the step (e) includes the step of etching back the ultra-fine particles to planarize the surface of the emitter film. The method of claim 40, The step of forming the second emitter film includes a step of directly coating a group of independent dispersible ultrafine particles on the first emitter electrode in a dry method using a spray printing system. The method of claim 40, The step of forming the second emitter film includes the step of plating a metal material which is not corroded on the first emitter electrode. The method of claim 40, The step of forming the second emitter film includes the step of depositing any one of Al, Cr, Ni, Ni, Mo, and Hf by sputtering or vapor deposition on the first emitter electrode. Method of manufacturing the device. The method of claim 40, The step of forming the second emitter film includes a step of depositing any one of W, Cr, and Al on the first emitter electrode by a CVD method.