KR20000022428A - Method and apparatus for etching a semiconductor wafer - Google Patents

Abstract

PURPOSE: An apparatus for etching a semiconductor wafer is provided to precisely control a profile and speedily etch the wafer by a physical and chemical etching. CONSTITUTION: A method for etching a semiconductor wafer(40) includes a tow step physical and chemical etching. process in order to create vertical side walls (20) required for high density DRAMs and FRAMs. The physical etching process generates a necessary vertical side walls of profiles and an unnecessary veils at the same time. The chemical etching is executed in the continuous process and the veils is eliminated by the chemical etching.

Description

Method and apparatus for etching semiconductor wafer

1 is a micrograph showing a cross section of a semiconductor wafer showing a veil or fence with photoresist remaining after using ion milling techniques.

FIG. 2 is a micrograph showing a cross section of a semiconductor wafer showing a protective film or barrier after removing photoresist after using ion milling techniques.

3 is a schematic view of the cross-sectional shape of the wafer as seen in the photo of FIG. 2 before the photoresist is removed.

4 is a photograph showing a cross-sectional shape of a semiconductor wafer with photoresist remaining after typical chemical etching.

FIG. 5 is a schematic view of the cross section of the wafer as seen in the photograph of FIG. 4 with photoresist remaining; FIG.

6 is a schematic view showing an embodiment of an etching apparatus according to the present invention.

7 is a micrograph showing a cross section of a semiconductor chip after physical and chemical etching is performed in accordance with the present invention.

8 is a micrograph showing a cross section of a semiconductor chip after an ashing or stripping process performed to remove photoresist and etch residue.

FIG. 9 is a cross-sectional micrograph of a semiconductor chip after performing a rinse process with respect to FIG. 8, showing a final contour having an appropriate vertical profile.

Fig. 10 is a schematic diagram of the cross section of the semiconductor chip shown in Fig. 7 with the photoresist remaining as it is.

11 is a graph showing a change in height of the protective film according to the flow rate of the chlorine gas changed for the chemical etching process.

12 is a graph showing the change of ion energy and ion density with RF frequency change when a power supply is supplied.

The present invention relates to an improved plasma etching apparatus and method. Recently developed thin films are useful for the development of highly integrated semiconductor chips such as high density DRAM (DRAM) and ferroelectric random access memories (FRAM). Such materials provide high capacity devices to enable the reduction of individual contours fabricated on a memory substrate. Therefore, more advanced profile control techniques are required.

In the past, numerous techniques have been utilized to obtain sidewall profiles of desired contours. One such technique is ion milling, which is classified as a physical etching method. In other words, an ion milling beam is used that physically collides and removes to partially remove an unwanted semiconductor device layer while leaving a desired outline such as various components and connection paths connecting the components on the semiconductor device. While the ion milling method forms the desired profiles, it has the following disadvantages. That is, the process speed was slow and there was a tendency to form veils or fences extending upward on the sidewalls of the desired contours.

The photoresist material is used as a protective film and used to define the desired contours produced by ion milling techniques. Once the photoresist material is stripped, an unwanted protective film or barrier remains and it is difficult to remove such structures.

Chemical etching may also be used to remove portions of the semiconductor wafer layer that are not protected by the photoresist material. However, although the chemical etching method has a high etching speed, it is disadvantageous that accurate profile control, such as using ion milling, is impossible.

Accordingly, there is a need for an etching method and apparatus capable of quickly and accurately etching new thin films used in recent semiconductor products.

The present invention has been made in view of the above problems with the conventional etching method, and includes an apparatus and a method for processing a new thin film material. The new thin film materials are, for example, platinum, barium strontium titanate (BST), and these materials are used for the development of highly integrated DRAM devices. Platinum, lead, zirconium, titanate (PZT), bismuth, strontium, and tantalum salts (Y-1) are used to develop nonvolatile frams (ferroelectric memories). Among the new thin film materials, BST, PZT, and Y-1 are materials having a high dielectric constant and are required to develop devices having a very narrow line width, that is, a highly integrated circuit. In order to further increase the degree of integration of the features, the control of the complete vertical profile is required.

The present invention relates to the performance of stringent etching to form anisotropic profiles (straight or vertical sidewalls) and is also highly selective and hardly damages underlying layers or other wafer materials, and can perform etching uniformly over non-uniform areas. It is about the etching method that can be.

Accordingly, the present invention provides an etching method and apparatus for performing physical etching and chemical etching to obtain a wafer profile that is best for obtaining a vertical profile. The present invention provides an etching apparatus and method for performing a chemical etching in succession after performing a physical etching method, which is mainly a physical etching such as ion milling.

Such a technique is unique and counterintuitive in that it forms the desired vertical profile in the ion milling portion during the etching process and together with the unwanted protective film. However, the present invention performs chemical etching in a continuous process, and the protective film is removed by the chemical etching. Thus, after that, as described in US patent application Ser. No. 08 / 438,261, the semiconductor wafer is subjected to a unique rinse-strip-rinse to obtain the desired features, configurations, densities and profiles. It is influenced by other methods as well. That is, after the chemical etching process is performed, the wafer is rinsed to remove soluble residues before stripping and removing the photoresist material in the stripping or ashing step, and in the subsequent late strip rinse process. Remove residue from the wafer.

Such a method is performed in a chamber having electrodes adjacent to where the semiconductor wafer is placed. The electrode is supplied with a first power supply operating in the range of several megahertz (MHz) and a second power supply operating in the range of several kilohertz (KHz). Also during the first part of the etching method of the present invention, the two power supplies operate to enhance ion milling techniques. During the next part where chemical etching prevails, the operation of the second power supply operating in the range of several kilohertz is stopped to greatly reduce the effect of ion milling.

The method of etching the semiconductor wafer of the present invention is characterized in that it is carried out using a tripolar chamber comprising a lower electrode which is powered and located adjacent to the wafer as mentioned above for the two power supplies. In the tripolar chamber, the edge peripheral electrode is grounded or floating, and the upper electrode, which is away from the wafer and fixed, is grounded or floating.

Further features, objects, and advantages of the invention may be achieved by reference to the specification, claims, and drawings of the invention.

The recent development of highly integrated DRAMs and frams has very narrow line widths with dense patterns, so improving the profile of the patterns is a very important issue. The density of the patterns is measured in pitch, which is defined as the sum of the width of the pattern and the width of the spaced spaces between the patterns. Typically, the pitch of the high density patterns is about 2.0 um or less, preferably about 0.5 um or less. Such narrow pitch patterns can be formed by using novel high-k dielectric films such as PZT, BST, Y-1 with the present invention and dielectric constants of 200 or more, in particular between 200 and 1400.

In recent years, high-density semiconductors are being developed using platinum (Pt), iridium (Ir), iridium dioxide (IrO2), PZT, ruthenium (Ru), ruthenium dioxide (RuO2), BST, Y-1 and other new materials. . Highly integrated semiconductor devices require high capacitance, and in order to obtain such high capacitance, an electrode made of platinum and a dielectric film such as PZT, BST, or Y-1 having a dielectric constant of about 1400 deposited between the platinum electrodes are used. In addition, it is important to control the profile of the patterns in the range of 70 ° to 85 ° in order to fully utilize the advantage of such high capacitance in a narrow space, and close to vertical is most preferable. In addition, there should be no unnecessary residue on the sidewalls of the pattern.

1, 2, and 3 show a micrograph of a predetermined pattern on a semiconductor wafer and a schematic view of its outline, wherein a vertical sidewall of the pattern shows a sidewall protective film or barrier extending upward. These protective films 20 shown in FIG. 3 are produced by an ion milling method in which sputtering predominates during the etching process. Materials sputtered in regions not protected by the photoresist 22 are deposited as the protective film 20. As shown in FIG. 3, this protective film 20 tends to cover the photoresist 22. As shown in FIG. When the photoresist is stripped, the protective films remain as shown in FIG. These protective films are made of platinum protruding from the platinum layer 24 and are deposited on the titanium layer 26 as shown in FIG. These protective films are re-deposited sputtered platinum and may include silicon dioxide, carbon, halogen, and other materials used during the etching process. Such protective films may include materials from layers included in semiconductor wafers or other thin films such as iridium, iridium dioxide, PZT, ruthenium, ruthenium dioxide, BST, Y-1. As described above, the protective films produced by ion milling are more severe when processing patterns having a narrow pitch of 0.5 μm or less used in advanced high-integrated DRAM or fram recently developed. This process is practically beneficial when the resulting sidewalls are vertical walls ranging from 70 ° to 85 ° and above.

4 and 5 show a profile of a semiconductor pattern formed by chemical etching. As shown in Fig. 5, the sidewalls 28 of the platinum pattern 30 have a bad profile, and thus are not suitable for the dense pattern formation required in the above-mentioned highly integrated semiconductor devices. Chemical etching forms a pattern with a profile in the range of 40 ° to 50 °. 4 and 5, the photoresist material 32 is formed on the top surface of the platinum layer 30 and shows a state in which it is not stripped.

The present invention provides a continuous etching method utilizing both the advantages of physical etching (ion milling) and chemical etching to form a semiconductor pattern with a profile as shown in FIG. The present invention provides an etching apparatus (three-pole reactor) shown in FIG. The etching device 34 includes a housing 36 and an etching chamber 38. Wafer 40 is placed on lower electrode 42. Chamber 38 also includes side peripheral electrodes 44 and top electrodes 46. In an embodiment of the present invention, the side peripheral electrode 44 is left grounded or floated by the plasma generated in the chamber 38. The upper electrode 46 is generally grounded. In normal operation, as shown in FIG. 6, the two side peripheral electrodes 44 and the upper electrode 46 are grounded.

Preferably, two power supplies, namely the first power supply 48 and the second power supply 50, are connected to the lower electrode 42 via a matching network and a combiner. The controller 54 also controls the operation of the first and second alternating current (AC) power supplies 48, 50. Typically, the first power supply operates in the range of a few kilohertz, and typically operates in the range of 500 KHz or less, preferably at about 450 KHz. The second power supply generally operates in the range of several megahertz and generally operates at about 1 MHz or more, and preferably at 13.56 MHz. Also, in the present invention, a multiple of 13.56 MHz was used. As shown in FIG. 12, ion energy increases with the kilohertz range, and ion density increases with the megahertz range. Such characteristics are very important in the operation of the present invention to be described below.

As described above, the present invention provides an etching method of performing an etching step in which chemical etching is dominant starting from an etching step in which physical etching (ion milling) is dominant. Such a procedure is very counterintuitive because it requires physical etching at the first stage of the process. Physical etching forms protective films on the sidewalls as shown in FIG. When physical etching, the first stage of the etching method, determined to have reached the end point of etching or a predetermined range is completed, the process is switched to the second stage of chemical etching by introducing another gas and applying different power. The second step is effective to remove the protective films while maintaining the sidewall profile so that the semiconductor pattern as shown in Figs. 7 and 10 is formed. In FIG. 10, the platinum layer 70 has a practical vertical sidewall, and the platinum layer 70 and the photoresist layer 72 have no protective films on the sidewall. Preferably, after the chemical etching process, it is preferable to rinse clean the semiconductor wafer before stripping the photoresist. By rinse cleaning, water soluble compounds, such as water soluble chlorine, are washed off prior to the stripping or ashing step of the photoresist. After the photoresist stripping process, a post strip rinse cleaning process is performed. Such steps will be described below with respect to those shown in FIGS. 7, 8 and 9. Such steps are described in the patent application cited above as reference material of the present invention, that is, in the nature of the rinse-strip-rinse process, the patent application entitled "Integrated Semiconductor Wafer Processing System".

Most preferably, chemical etching occurs during the first stage, which is physical etching, and physical etching or ion milling, in the second stage where chemical etching predominates.

In the etching method of the present invention, ion milling is performed using argon and chemical etching is performed using chlorine. The first preferred method is that, during the physical etching (ion milling) step, argon is fed to the chamber 38 (FIG. 6) from about 10 SCCM (standard cubic centimeter per minute) to 50 SCCM and more preferably 20 SCCM, and chlorine is supplied to the chamber. In the range of about 2SCCM to 50SCCM, particularly preferably 5SCCM to 10SCCM. The pressure in the chamber during the physical etching will be maintained at about 2-10 mtorr, more preferably at 5 mtorr and the temperature at about 80 ° C. The preferred first power supply 48 operates at about 450 KHz in a power range of 50W to 200W. The second power supply 50 operates at about 13.56 MHz in the power range of about 500W to 1100W. Typically, the physical etch step is performed for about 2/3 of the time for 100% of the etch endpoint. When the platinum layer is 1000 microns thick, the optical etch endpoint of platinum is about 70 seconds for wafers in the 6 "to 8" range. The optical etch endpoint when the thickness of platinum is 2000 microns is about 150 seconds for wafers in the 6 "to 8" range. In order to use the endpoint as a method of time measurement, the endpoint time is first determined by performing a trial run of the physical etching process until reaching the endpoint. The production run then performs physical etching based on the segmentation of the endpoint time measured in the test run. The time for performing the physical etching step can be obtained without determining the end point. For example, the time required to etch the entire thickness of the film is determined, and then a physical etching step is performed for a fraction of the time, for example about 2/3 of the time. When the end point is reached or at some time as a percentage of the end point, the process shifts to a step where chemical etching predominates. In this situation, it is preferable that argon is maintained at about 20 SCCM and chlorine is increased to about 15 SCCM. However, for chemical etching, argon gas is allowed to flow at about 0SCCM to 50SCCM, and chlorine gas is allowed to flow at a rate of about 5SCCM to 100SCCM.

In FIG. 11, the height of the final protective film according to the change in the flow rate of chlorine gas is shown in Angstrom units. As the flow rate of chlorine gas increases, the barrier height decreases, especially above 10 SCCM, the barrier is actually attacked and its size decreases. The line denoted by 60 in the graph of Fig. 11 represents a barrier facing the open area. Lines 62 are barriers formed on the sidewalls of the pattern spaced apart with a space of about 0.8 um. Line 64 represents the appearance of a barrier formed on the sidewalls of the pattern spaced about 0.3um apart.

During the chemical etching step, the pressure is reduced to about 2 mtorr to 10 mtorr, especially on the order of 2 mtorr. The first power supply 48 operating in the kilohertz range stops operation to reduce the ion milling effect. Indeed, during the chemical etching step, the first power supply can operate in the range of 0W to 50W. As shown in Figure 12, it is the power supply in the kilohertz range that increases the ion energy to cause ion milling. The second power supply 30 is maintained at about 13.56 MHz and operates in the range of about 50W to 1100W.

In a preferred embodiment of the present invention, in the second step of this two step etching method, the chemical etching step is performed for about 45 to 120 seconds for 1000 mm and 2000 mm thick platinum to remove the protective film formed by the ion milling process. Etching is performed.

Chemicals for etching metals or other conductors include (1) argon and chlorine, (2) argon, chlorine and hydrogen bromide (HBr), (3) argon, chlorine and carbonyl gas, and (4) any of the foregoing. Chemical and oxygen (O ₂ ), (5) SF ₆ or any of the chemicals described above and SF _6, (6) NF ₃ or NF ₃ and any of the chemicals described above, (7) fluorine carbide (CxFy) or Other chemicals described above, and fluorocarbons, (8) argon and chlorine gas.

The result of the two-step etching process for performing the physical and chemical etching is as shown in the micrograph of Figure 7, the photoresist is protruding sharply in the center of each feature, the residue of the protective film ( Can be seen attached to each sidewall of the patterns. In this step, the semiconductor pattern is rinsed clean to remove soluble compounds. After rinsing cleaning, the semiconductor wafer is exposed to a stripping or ashing process to remove photoresist and protective film and etch residue (Figure 8). The stripping process is preferably performed using a wet solvent. The solvent attacks and removes the photoresist and the remaining protective film. After stripping is performed, subsequent rinse cleaning is performed on the semiconductor wafer, resulting in a shape as shown in FIG.

The rinse-striping-rinse process described above can be performed, for example, using the apparatus shown in FIG. The system of FIG. 13 includes a vacuum load lock chamber 116, a positioning module 118, two etching modules 120 and 122, and a strip module 124, all of which are described above. It is connected to a central vacuum chamber 126 via a closable opening and is operated by a computer process control system (not shown). The load lock chamber 116 houses an internal cassette elevator to hold a wafer cassette (load cassette). The vacuum chamber 126 has a robotic wafer handling system 138 for transferring wafers from one chamber or module to another. The strip module 124 is connected to the atmospheric robotic wafer handling system 132 through the opening / closing regulator 127, and in turn is connected to the rinse module 125 and the atmospheric cassette module 134 (export cassette). A commonly used rinse module is the Semitool Equinox rinse system. The atmospheric robotic wafer handling system 132 assists the atmospheric cassette module 134 to hold the wafer after the process is complete. The second robotic wafer handling system 132 also transfers wafers between the strip module 124 and the rinse module 125. During the rinse cleaning process, the rinse module 125 and the robotic handling system 132 are designed to maintain the degree of alignment of the wafer as needed in the strip module 124 for stripping. All operations of the present invention are automated and can be programmed through a computing system.

In actual operation, after etching is performed in the etching module of any of the etching modules 120, 122, the wafer passes through the strip module 124 and is first rinsed by the robotic arm 132. The rinse module 125 is shipped to a rinse module 125 where cleaning occurs. After this rinse clean, robotic arm 132 re-transfers the wafer to strip module 124 where photoresist stripping occurs. After wafer stripping, the wafer is retransmitted by robotic arm 32 to rinse module 25 for final rinse cleaning.

The invention is applicable to structures with photoresists as well as structures with oxides and other such hard masks. The present invention is also applicable here to a variety of other films as well as certain recently developed films.

Reactors other than those specified above may also be used with the above method. By way of example, the present invention may be used with an inductively coupled plasma source reactor (ICP). The ICP may, for example, include a helicon reactor or a spiral reactor. The tripolar reactor is a capacitively coupled reactor. The method of the present invention can also be used using a reactor that combines both induction and capacitance. Electronic synchrotron resonance (ECR) reactors can also be used with the present invention.

Industrial Applicability:

As described above, the apparatus and method of the present invention are intended to have a vertical profile of a pattern to form dense patterns on a semiconductor wafer, which is required for the latest DRAM and FRAM that is being developed. Including two chemical etching steps provides an etching method. In the device and method of the present invention, the barrier is removed after the vertical walls (protective films) are formed. The apparatus and method of the present invention can be applied to new films required for new highly integrated semiconductor products. Other features, effects, objects, and the like of the present invention can be achieved through the claims and drawings of the present invention.

In addition, other embodiments may be developed within the scope and spirit of the present invention and claims.

Claims (46)

17. A method of etching a wafer comprising physically etching the wafer and then chemically etching to obtain a wafer pattern having at least substantially vertical sidewall profiles. The method of claim 1, wherein said physically etching and chemically etching provide a vertical sidewall side profile free of etch residues. The method of claim 1, wherein physically etching the wafer comprises using about 10 SCCM to 50 SCCM of argon gas and about 2 SCCM to 50 SCCM of chlorine gas. The method of claim 1, Physically etching the wafer is performed in the range of about 2 mtorr to 10 mtorr. The method of claim 1, The physical etching may be performed in a chamber in which an electrode to which a power of about 450 KHz and 13.56 MHz is applied is placed, and the wafer is adjacent to the electrode. . The method of claim 1, wherein the physical etching comprises applying an electrode having a first power source of about 500 KHz or less, applying a second power source of about 1 MHz or more, and placing an electrode therein, wherein the wafer is located adjacent to the electrode. A method of etching a wafer, characterized in that performed in a chamber in which it lies. The method of claim 1, wherein the physical etching is performed in a chamber in which the wafer is placed on an electrode connected to a first power supply operating in the kilohertz range and a second power supply operating in the megahertz range. A method of etching a wafer to be used. 8. The method of claim 7, wherein the first power source provides power in the range of about 50 W to 200 W and the second power source provides power in the range of about 500 W to 1100 W. . 8. The method of claim 7, wherein the electrode is a lower electrode, and the method has a side peripheral electrode provided near an edge of the lower electrode, and an upper electrode spaced apart from the lower electrode and disposed above the lower electrode. And wherein the side peripheral electrode is grounded or floating and the top electrode is performed in a grounded or floating chamber. The method of claim 1, wherein the physically etching is performed at about 80 ° C. 3. The method of claim 1, wherein the physically etching is performed for 2/3 hours of the etching end point to the time until the etching end point. The method of claim 3, wherein the etching of the wafer comprises argon gas in the range of about 0SCCM to 50SCCM and chlorine gas in the range of 50SCCM to 100SCCM. The method of claim 4, wherein chemically etching the wafer is performed in a range of 2 mtorr to 10 mtorr. 8. The method of claim 7, wherein the chemically etching comprises applying power to the electrode in a range from about 0 to 50 W from a first power source operating in the kilohertz range and from a second power source operating in the megahertz range. A method of etching a wafer, characterized in that performed with power applied. 15. The method of claim 14, wherein during the chemical etching step, the second power source supplies power in the range of about 500-1100 W. 8. The method of claim 7, wherein, during the chemically etching step, the first power supply operating in the kilohertz range is stopped to reduce the effect of physical etching. The method of claim 1, wherein the physical etching step is performed for about 70 seconds on a platinum layer of about 1000 mm thick, the chemical etching step is performed on about 60 seconds to 120 seconds, and the physical etching step is performed on about 2000 mm thick platinum layer. Is carried out for 150 seconds, and the chemical etching step is performed for about 60 to 120 seconds. The method of claim 1, wherein the physical etching and chemical etching of the metal layer comprises (1) argon and chlorine gas, (2) argon, chlorine and hydrogen bromide (Hbr), (3) argon, chlorine and carbonyl gas, ( 4) the above-described chemicals and oxygen, (5) the above-described chemicals and SF ₆ or SF ₆ , (6) any of the above chemicals and any of NF ₃ or NF ₃ How to etch. The method of claim 1, wherein the physical etching and the chemical etching for the insulating layer is (1) argon and CF ₄ gas, (2) argon, CF ₄ and chlorine gas, (3) argon, CH ₃ and chlorine gas, ( 4) any of the above combinations with bromine gas, (5) any of the above, SF ₆ or SF ₆ only, (6) any of the above, only NF ₃ or NF ₃ , (7) carbon fluoride only or other chemicals (8) A method of etching a wafer, wherein any one of carbon and argon and chlorine gas is used. The method of claim 1, wherein a first power supply in the kilohertz range and a second power supply in the megahertz range are applied to the electrode during the physical etching step and wherein the second power supply is in the megahertz range during the chemical etching step. A method of etching a wafer, wherein one power supply is applied to the electrode. Making a protective film on the wafer pattern using ion milling, Removing the protective film by chemical etching. 24. The method of claim 23, further comprising: forming the protective film on a material including at least one of platinum, iridium, iridium oxide, ruthenium, ruthenium oxide, bismuth strontium tantalum salt, barium strontium titanium salt, and lead zirconium titanium salt. Removing the wafer; and etching the wafer. 24. The method of claim 23, comprising forming and removing the passivation layer on a high dielectric material. 24. The method of claim 23, comprising forming and removing the passivation layer over a dielectric constant of at least 200 material. Forming a vertical wall profile and a sidewall protective film over the wafer pattern; Removing the protective film leaving the vertical sidewall profile. 28. The method of claim 27, wherein said step is for forming a vertical sidewall profile of at least about 70 degrees. The method of claim 27, Wherein the forming step is performed using a process in which physical etching is predominantly performed, Wherein said removing is performed using a process in which chemical etching predominates. A process which is mainly a physical etching step, performing a wafer by combining physical etching and chemical etching; A method of etching a wafer comprising the step of performing a combination of physical and chemical etching of the wafer in a process which is mainly a chemical etching step. The method of claim 1, wherein the wafer is etched on a semiconductor wafer having a pitch of about 2.0 μm or less, more preferably 0.5 μm. The method of claim 1, wherein the wafer is etched on a semiconductor device having a narrow pattern width having a pitch of 2.0 μm or less and more preferably 0.5 μm or less. An etching chamber; A first electrode; A first power supply operable in the range of kilohertz and optionally connectable with the first electrode; A second power supply operable in the range of megahertz and optionally connectable with the first electrode; A second electrode spaced apart from the first electrode; A wafer that can be placed adjacent to the first electrode; The first and second power supplies can be selectively operated to power the first electrode during the physical etching process, reducing the power of the first power supply operating in the kilohertz range during the chemical etching process while the first electrode An apparatus for etching a semiconductor wafer comprising a controller capable of selectively operating a second power supply operating in the megahertz range for powering it. 34. The apparatus of claim 33, wherein the second electrode is grounded or electrically floating. 33. The method of claim 32, comprising a side peripheral electrode positioned around the first electrode between the first electrode and the second electrode, the side peripheral electrode being grounded or electrically floating. Device. The method of claim 3, wherein physically etching the wafer uses about 20 SCCM of argon gas and about 5 SCCM to 10 SCCM of chlorine gas. 5. The method of claim 4, wherein the step of physically etching the wafer is performed in the range of about 5 mtorr. 10. The method of claim 8, wherein the first power source applies a power in the range of about 100W to 200W and the second power source applies a power in the range of about 500W to 700W. The method of claim 1, wherein chemically etching the wafer comprises argon gas of 0 SCCM to 50 SCCM and chlorine gas in a range of 5 SCCM to 100 SCCM. 4. The method of claim 3, wherein chemically etching the wafer comprises argon gas of 20 SCCM and chlorine gas in the range of 10 SCCM to 15 SCCM. 38. The method of claim 37, wherein the step of chemically etching the wafer comprises argon gas of about 20 SCCM and chlorine gas in the range of 10 SCCM to 15 SCCM. The method of claim 13, wherein chemically etching the wafer is performed at about 2 mtorr. 15. The method of claim 14, wherein the chemically etching is performed without applying power to the electrode from a first power source operating in the kilohertz range. The method of claim 1, wherein the physically etching is performed during a percentage of etch endpoint detection time. The method of claim 1, wherein the physically etching is performed for a percentage of the time required to fully etch the film. The wafer of claim 1, wherein one of (1) an inductively coupled plasma source reactor, (2) an electron synchrotron resonance reactor, and (3) a tripolar reactor having a high and low frequency power supply connected to one electrode is used. How to. The method of claim 1, wherein the reactor uses both inductive coupling and capacitive coupling. The method of claim 1, wherein the wafer is etched using any one of (1) an inductively coupled reactor and (2) a capacitively coupled reactor.