KR20000020154A - Tuner for digital satellite broadcasting receiver - Google Patents

Abstract

PURPOSE: A tuner for a digital satellite broadcasting receiver capable of promoting a system performance by compensating a lost frequency according to a temperature drift by means of a voltage control oscillator is provided. CONSTITUTION: In a tuner for a digital satellite broadcasting receiver, a QPSK link IC(200)compares a phase of a third base band signal from a third mixer with a phase of a second base band signal from a second mixer and stores a frequency drift value in a register. A microcomputer(210) compares a current frequency symbol with the frequency drift value stored in the register of the QPSK link IC(200) and an enable pulse signal according a generation of a frequency drift. A low pass filter(220) converts the enable pulse signal from microcomputer(210) into a direct current. A voltage control oscillator(230) supplies different phase shifted oscillating frequencies to the second and third mixers according to an output of the low pass filter(220).

Description

Tuner for receiving digital satellite broadcasting

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuner for receiving digital satellite broadcasting, and more particularly, to a tuner for receiving digital satellite broadcasting that improves the performance of a system by compensating a frequency lost by temperature drift by a voltage controlled oscillator circuit. It is about.

In general, the tuner for receiving a satellite broadcast is a receiver tuner that can receive satellite broadcast directly on a TV without going through a satellite relay station. It is a product corresponding to HDTV, and it is a key component that enables simultaneous listening in a wide range of regions. The tuner is a receiver that amplifies and mixes the primary intermediate frequency signal, changes the secondary intermediate frequency to a secondary intermediate frequency, and detects.

As shown in FIG. 1, the digital satellite broadcast receiving tuner includes an input tuning circuit 10 for inputting a signal of a high frequency band applied from an antenna, and a high frequency signal passing through the input tuning circuit 10. And a high frequency amplification circuit 20 for selecting a desired high frequency signal among the high frequency signals amplified by the high frequency amplification circuit 20.

And a local oscillation circuit 50 interlocked by a frequency synthesizer (not shown) controlled by a microcomputer (located outside of the tuner) to output an oscillation frequency, and a predetermined reference frequency and the local oscillation circuit 50. The oscillation frequency is compared to determine whether it is higher or lower than the reference frequency. If it is high, the oscillation frequency of the local oscillation circuit 50 is lowered, and if it is low, it is controlled to increase the phase synchronization loop (Phase Locked) to obtain an accurate oscillation frequency. Loop: PLL) IC 60.

And a first mixing circuit 40 for mixing the high frequency signal selected through the high frequency tuning circuit 30 and the oscillation frequency of the local oscillation circuit 50 to output an intermediate frequency, and the first mixing circuit 40. A first intermediate frequency amplifier circuit 70 for amplifying the intermediate frequency of the antenna, an intermediate frequency filter 80 for filtering the intermediate frequency amplified by the first intermediate frequency amplifier circuit 70, and the intermediate frequency filter And a second intermediate frequency amplifier circuit 90 which amplifies the intermediate frequency filtered through 80.

In addition, an intermediate frequency oscillation circuit 120 for generating an oscillation frequency having an oscillation frequency of 90 ° and 0 ° respectively by an AFT (Automatic Fine Tunning) signal outside the tuner, and the second intermediate frequency amplifier circuit 90 A second mixing circuit 100 for mixing the intermediate frequency amplified by < RTI ID = 0.0 >) < / RTI > and the frequency (0 ° phase) from the intermediate frequency oscillating circuit 120 to output a demodulated baseband signal I, A third mixed circuit for mixing the intermediate frequency amplified by the intermediate frequency amplifier circuit 90 and the oscillation frequency shifted 90 degrees out of the intermediate frequency oscillation circuit 120 to output a demodulated baseband signal Q; 110).

The operation of the conventional digital satellite tuner according to the above configuration will be briefly described as follows.

First, a signal of a high frequency band received from an antenna passes through the input tuning circuit 10, the high frequency amplifying circuit 20, and the high frequency tuning circuit 30 so that only one broadcasting frequency is selected. The selected high frequency signal is mixed with the oscillation frequency of the local oscillation circuit 50 and the first mixing circuit 40 to output an intermediate frequency.

In this case, the local oscillation circuit 50 is interlocked by a frequency synthesizer (not shown) controlled by a microcomputer (located outside of the tuner) to output the oscillation frequency to the first mixed circuit 40. In addition, a phase locked loop (PLL) IC 60 that controls the operation of the local oscillation circuit 50 compares an oscillation frequency of the local oscillation circuit 50 with a predetermined reference frequency, rather than a reference frequency. It is determined whether the high or low is high to lower the oscillation frequency of the local oscillation circuit 50, and if it is low to control the height to obtain the accurate oscillation frequency.

The intermediate frequency output from the first mixed circuit 40 is amplified by the first intermediate frequency amplifier circuit 70 and then filtered by the intermediate frequency filter 80, and the second intermediate frequency amplifier circuit 90 The amplification is again amplified by the second and third mixing circuits 100 and 110, respectively.

On the other hand, the intermediate frequency oscillator circuit 120 is controlled by an AFT signal outside the tuner to shift the oscillation frequency by 0 ° or 90 ° phase to supply to the second and third mixed circuits 100 and 110, respectively.

The second mixed circuit 100 is demodulated by mixing the intermediate frequency amplified by the second intermediate frequency amplifier circuit 90 and the oscillation frequency (0 ° phase) from the intermediate frequency oscillator circuit 120. And outputs a band signal (I), wherein the third mixed circuit (110) is shifted 90 degrees out of the intermediate frequency amplified by the second intermediate frequency amplifier (90) and the intermediate frequency oscillator (120). The oscillation frequency is mixed to output a demodulated baseband signal Q.

However, in the conventional digital satellite tuner configured as described above, the intermediate frequency oscillator circuit outputs a 0 ° and 90 ° phase shifted signal to the second mixed circuit 100 and the third mixed circuit 110, respectively. Since 120 is configured as a fixed oscillator, there is a problem that the oscillation frequency changes with temperature change. Such a problem has caused a problem that the baseband signals I and Q cannot be extracted by changing the frequencies output to the second and third mixed circuits 100 and 110, respectively, thereby degrading the performance of the entire system. .

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to compensate for the frequency lost by the temperature drift by the voltage controlled oscillator circuit. Is to provide a credit tuner.

1 is a block diagram of a conventional tuner for digital satellite broadcasting reception

2 is a block diagram of a tuner for receiving digital satellite broadcasting according to the present invention.

3 is a circuit diagram of the low pass filter shown in FIG.

4 is an operation flowchart of the present invention.

* Explanation of symbols for the main parts of the drawings

10: input tuning circuit 20: high frequency amplification circuit

30: high frequency tuning circuit 40: first mixed circuit

50: local oscillation circuit 60: phase locked loop (PLL) IC

70: first intermediate frequency amplifier circuit 80: intermediate frequency filter

90: second intermediate frequency amplifier circuit 100: second mixed circuit

110: third mixed circuit 120: intermediate frequency oscillator circuit

200: Quartile Phase Shift Modulation (QPSK) Link ICs

200a: Frequency drift register

210: microcomputer 220: low pass filter

230: voltage controlled oscillation circuit

In order to achieve the above object, the digital satellite broadcast receiving tuner according to the present invention,

A first mixing circuit for mixing the high frequency signal inputted through the high frequency tuning circuit and the oscillation frequency of the local oscillating circuit to output an intermediate frequency, and an intermediate frequency amplifier for amplifying and filtering the intermediate frequency of the first mixing circuit into a predetermined band; A digital satellite broadcasting tuner including a circuit and an intermediate frequency filter, and second and third mixed circuits for inputting respective intermediate frequencies filtered through the intermediate frequency filter to output baseband signals.

A quartile phase shift keying (QPSK) link IC which compares the phase difference of the baseband signals output from the second and third mixing circuits, and stores a calculated value of the frequency drift in a register;

A micro-com that generates an enable pulse signal when it is determined that a frequency drift has occurred by comparing a value stored in the register of the quartile shift modulation link IC with a current frequency symbol rate;

In addition, the low-pass filter for inputting the enable pulse signal of the microcomputer to a DC value, and

And a voltage controlled oscillation circuit for generating a phase shifted oscillation frequency having a different magnitude by the output value of the low pass filter to the second mixed circuit and the third mixed circuit, respectively.

In the above configuration, the microcom is configured to control the voltage controlled oscillation circuit to be fixed oscillation when the symbol rate is high, and to compensate for the frequency drift by changing the voltage value of the voltage controlled oscillation circuit when the symbol rate is low. It is preferable.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a block diagram of a tuner for receiving digital satellite broadcasting according to the present invention, FIG. 3 is a circuit diagram of the low pass filter shown in FIG. 2, and FIG. 4 is an operation flowchart of the present invention.

Referring to FIG. 2, the tuner for receiving digital satellite broadcasting according to the present invention compares the phase difference between the baseband signals I and Q output from the second mixing circuit 100 and the third mixing circuit 110, respectively, and frequency drifts. Quarter Phase Shift Keying (QPSK) Link IC (hereinafter referred to as a 'QPSK Link IC') (200) for storing the calculated value in the frequency drift register 200a and the quartile phase shift keying. The micro-com 210 generates a pulse width modulation (PWM) waveform when it is determined that the frequency drift has occurred by comparing the value stored from the frequency drift register 200a of the (QPSK) link IC 200 with the current frequency symbol rate. ). In addition, a low pass filter 220 for inputting a pulse width modulation (PWM) waveform of the micro-com 210 and converting it into a direct current (DC) value and a different size by an output value of the low pass filter 220 The voltage controlled oscillation circuit 230 for generating the phase shifted oscillation frequencies (0 ° and 90 °), respectively, is configured differently from the conventional digital satellite broadcasting reception tuner shown in FIG.

In the above configuration, the frequency drift register 200a is a register that stores the frequency drift as a 1 byte value.

The tuner for digital satellite broadcasting reception according to the present invention having the above-described configuration includes a first mixed circuit 40 and a high frequency signal received by a local oscillation circuit 50 oscillating in conjunction with the phase locked loop (PLL) IC 60. When the signal corresponding to the sum is oscillated, the difference signal with the input signal having a constant frequency and bandwidth is output by the action of the first mixing circuit 40. This signal is again input to the intermediate frequency filter 80 via the first intermediate frequency amplifier circuit 70, and only the signal corresponding to the characteristics of the filter 80 is output to the second intermediate frequency amplifier circuit 90. do. The signal amplified by the second intermediate frequency amplifier circuit 90 is input to the second and third mixed circuits 100 and 110, respectively.

On the other hand, the voltage controlled oscillation circuit 230 for the intermediate frequency oscillation outputs a signal shifted 0 ° and 90 ° phase to the second and third mixed circuit (100, 110). The output signal of the voltage controlled oscillator circuit 230 having a 0 ° phase with the output signal of the second intermediate frequency amplifier circuit 90 causes the second mixed circuit 100 to output the baseband signal I. The output signal of the voltage controlled oscillator circuit 230 having a 90 ° phase with the output signal of the second intermediate frequency amplifier circuit 90 receives the baseband signal Q by the third mixed circuit 110. Will print.

The baseband signals I and Q are frequency drift values in the frequency drift register 200a by a block (not shown) that compares the phase difference between I and Q in the QPSK link IC 200 and calculates a frequency drift. Will be saved.

On the other hand, the micro-com 210 from the frequency drift register 200a by using the I ² C line according to the "algorithm for controlling the operation of the voltage controlled oscillation circuit 230" shown in Figure 4 (to be described later). The value is read. At this time, if it is determined that the frequency drift has occurred, generates a PWM waveform by using the output port of the microcomputer (210). The generated PWM waveform is changed into a direct current (DC) value through the low pass filter 220, and the changed direct current (DC) value is inputted to the voltage controlled oscillation circuit 230 to generate the voltage controlled oscillation circuit 230. By controlling the operation, the oscillation frequency, which is an output signal, is changed.

Therefore, the present invention compares the present symbol rate with the value stored in the frequency drift register, and when the present symbol rate is high, oscillates the voltage controlled oscillation circuit 230, and when the symbol rate is low, the voltage control. The frequency drift can be compensated for by changing the voltage value of the oscillator circuit 230.

3 is a circuit diagram of the low pass filter 220 shown in FIG. And a resistor R1 connected between the input terminal and the power supply voltage Vcc, and a capacitor C1 connected between the output terminal and the ground voltage Vss.

In the above configuration, the resistor R1 serves to pull-up the power supply voltage Vcc, and the resistor R2 and the capacitor C1 are low-pass filters as the low voltage pass filter. In consideration of the frequency deviation according to the voltage change of 230 should be designed as a time constant value.

4 is a flowchart for controlling the operation of the voltage controlled oscillation circuit 230, which is embedded in the micro com.

First, when the current symbol rate is high by comparing the current symbol rate with a value stored in the frequency drift register 200a, a pulse width modulation (PWM) is used to fix the voltage controlled oscillation circuit 230 to oscillate fixedly. In step 310 to 320, the control routine of the voltage controlled oscillation circuit 230 is immediately finished so as not to generate a waveform.

On the other hand, when the current symbol rate is low (310 to 320) by comparing the current symbol rate with the value stored in the frequency drift register 200a, the current value is read from the frequency drift register 200a (step 330). ). The frequency drift value is calculated from the current symbol rate and the value of the frequency drift register 200a (step 340). According to the calculated frequency drift value, a pulse width modulation (PWM) waveform is generated at the output port of the microcomputer 210 (step 350).

The pulse width modulation (PWM) waveform is converted into direct current (DC) through the low pass filter 220 and input to the voltage controlled oscillation circuit 230. According to the magnitude of the input voltage, the voltage controlled oscillator circuit 230 generates an oscillation frequency having a 0 ° phase and a 90 ° phase.

As described above, according to the tuner for receiving digital satellite broadcasting according to the present invention, a very excellent effect of improving the performance of the system by compensating for the frequency lost by the temperature drift by the voltage controlled oscillator circuit. There is.

That is, in the conventional intermediate frequency oscillator circuit having a fixed oscillation, when the frequency drift occurs, the baseband signals (I, Q) cannot be extracted and data cannot be extracted. In particular, this problem is caused by the frequency drift a lot when the symbol rate is low, which causes the performance of the overall system.

However, the tuner for receiving digital satellite broadcasting according to the present invention controls to oscillate a voltage controlled oscillation circuit that generates an oscillation frequency when the symbol rate is high, and changes the voltage value of the voltage controlled oscillator circuit when the symbol rate is low. In order to compensate for the frequency drift, the performance of the entire system is improved, and compared with the intermediate frequency oscillation circuit used as a conventional fixed oscillator, there is a very excellent effect that can be configured.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the present invention disclosed in the appended claims.

Claims (2)

A first mixing circuit for mixing the high frequency signal inputted through the high frequency tuning circuit and the oscillation frequency of the local oscillating circuit to output an intermediate frequency, and an intermediate frequency amplifier for amplifying and filtering the intermediate frequency of the first mixing circuit into a predetermined band; A digital satellite broadcasting tuner including a circuit and an intermediate frequency filter, and second and third mixed circuits for inputting respective intermediate frequencies filtered through the intermediate frequency filter to output baseband signals. A quartile phase shift modulated link IC configured to compare a phase difference between the baseband signals output from the second and third mixed circuits and store a value obtained by calculating a frequency drift in a register; A micro-com that generates an enable pulse signal when it is determined that a frequency drift has occurred by comparing a value stored in the register of the quartile shift modulation link IC with a current frequency symbol rate; A low pass filter for inputting the enable pulse signal of the microcom to a DC value; And a voltage controlled oscillator circuit for generating a phase shifted oscillation frequency different in magnitude by an output value of the low pass filter to the second mixed circuit and the third mixed circuit, respectively. 2. The method of claim 1, wherein the microcom is configured to control the voltage controlled oscillator circuit to be fixed oscillation when the symbol rate is high, and to compensate for frequency drift by changing the voltage value of the voltage controlled oscillator circuit when the symbol rate is low. Tuner for receiving digital satellite broadcasting, characterized in that to give.