KR20000020107A - Method for forming contact of semiconductor device and structure of the contact - Google Patents

Abstract

PURPOSE: A method for forming contact of semiconductor device and structure of the contact are provided to prevent the increase of a floating gate contact resistance and the short between a floating gate contact and a bulk. CONSTITUTION: A method for forming contact of semiconductor device comprises a step of forming a second conductive type well(102), a step of forming an element isolation film(104), a step of forming an electrode(106), a step of forming a layer insulation film(108), a step of forming an electrode contact hole(109), and a step of forming a contact electrode(110). The element isolation film(104) defines an active region and an inactive region. The contact hole(109) is formed by etching the interlayer dielectrics(108) and the width of the hole is wider than that of the electrode(106).

Description

A METHOD OF FABRICATING CONTACT OF SEMICONDUCTOR DEVICE AND THE STRUCTURE THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a contact forming method and a structure of a semiconductor device.

FIG. 1 is a layout view of a conventional semiconductor memory device, and FIGS. 2A to 2C are cross-sectional views taken along the line AA ′ of FIG. 1, and are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor memory device.

Referring to FIG. 1, a conventional semiconductor memory device includes an active region 2 and a floating gate 4a overlapping the active region 2. And a control gate 12 overlapping the active region 2 and overlapping a portion of the floating gate 4a.

The device comprises a metal line 16 and a metal contact 18 formed to overlap the floating gate 4a and the control gate 12. Reference numeral 14 denotes a source line, and reference numeral 20 denotes a unit cell.

Referring to FIG. 2A, in the conventional method of manufacturing a semiconductor memory device, a cell gate oxide 3 is formed on a semiconductor substrate 1 in which an active region and an inactive region are defined. The first polysilicon film 4 is deposited on the gate oxide film 3. The first polysilicon film 4 is a film for forming a floating gate and is deposited in a thickness range of about 1000 kPa to 2000 kPa. A silicon nitride film 6 is deposited on the first polysilicon film 4 within a thickness range of about 500 kW to 2000 kW. The silicon nitride film 6 is partially etched until the floating gate forming portion is exposed.

In FIG. 2B, the first polysilicon film 4 is oxidized by a local oxidation of silicon (LOCOS) process which is generally well known in the art to form an interpoly oxide 8. After the silicon nitride film 6 is stripped, the first polysilicon film 4 is etched using the interpoly oxide film 8 as a mask. Then, the floating gate 4a is formed.

Finally, as shown in FIG. 2C, a process of oxidizing the floating gate 4a is performed, and as a result, a tunnel oxide 10 is formed. A second polysilicon film is deposited on the entire surface of the semiconductor substrate 1. The second polysilicon film serves as a word line as a control gate forming film.

Next, the second polysilicon film is patterned by a photolithography process, which is well known in the art, to form a control gate 12. A photolithography process and an impurity ion implantation process are performed to form the source region 14 of the cell. Subsequently, when the photolithography process and the impurity ion implantation process for forming the n + and p + source / drain regions are performed, a split gate flash cell structure is completed as shown in FIG. 3.

In a subsequent process, a metal contact forming process is performed.

The split gate flash cell performs a program operation by inducing electrons to a floating gate by a source side hot electron injection method. Then, Vpp is applied to the control gate to induce electrons by a Fowler nordheim tunneling method from the floating gate to the control gate to perform an erase operation. It is possible to distinguish such a program cell and an erase cell by sensing an on / off cell by a relative amount of current.

However, in sensing the on-cell and off-cell, using a reference cell is advantageous for implementing a high speed device. The reference cell normally applies a bias to the floating gate to reference the threshold voltage of the floating gate.

However, in the split gate flash cell using the oxidation of the floating gate polysilicon film, the floating gate polysilicon film remains thin after the oxidation process with a thickness of about 400 kPa to 600 kPa. As a result, as shown in FIG. 4, during the process of forming the floating gate contact 38 electrically connected to the floating gate 34, the floating gate contact 38 contacts the field oxide film 32 (reference numeral 39). The contact resistance becomes very high.

In addition, the cell is usually formed in a p-type substrate or a p-type well, even if the field oxide layer 32 is etched by an overetch process for forming the floating gate contact 40. As in 5, a short is generated between the floating gate contact 40 and the p-type substrate (p-type well) 30 (reference numeral 41).

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and it is possible to reduce the thickness consumption of the floating gate poly in the floating gate poly-oxidation process, and thus to increase the floating gate contact resistance. Its purpose is to provide that structure.

Another object of the present invention is to form a well of a different conductivity type from a semiconductor substrate in a semiconductor substrate under the floating gate contact region to prevent shorting between the floating gate contact and the bulk when forming a floating gate contact wider than the floating gate polysilicon film. The present invention provides a method for forming a contact and a structure of the semiconductor device.

1 is a layout diagram of a conventional semiconductor memory device;

2A through 2C are cross-sectional views taken along the line AA ′ of FIG. 1 and sequentially illustrating processes of a method of manufacturing a semiconductor memory device;

3 is a cross-sectional view taken along the line BB ′ of FIG. 1, showing a state after a control gate is formed;

4 is a cross-sectional view illustrating a contact structure according to a contact forming method of a conventional semiconductor memory device;

5 is a cross-sectional view showing another contact structure according to a contact forming method of a conventional semiconductor memory device;

6 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 7 is a cross-sectional view taken along the line CC ′ of FIG. 6, illustrating a floating gate contact structure according to the method for forming a contact according to the present invention.

* Explanation of symbols for the main parts of the drawings

1, 30, 100: semiconductor substrate 2, 120: active region

3: cell gate oxide film 4a, 34, 35, 106: floating gate

8 interpoly oxide film 10 tunnel oxide film

12: control gate 16: metal line

18 metal contact 20 unit cell

32, 104: field oxide film 36, 108: interlayer insulating film

38, 40, 110: floating gate contact 102: well

122: bit line contact 130: reference cell

(Configuration)

According to the present invention for achieving the above object, a method of forming a contact of a semiconductor device, forming a second conductivity type well 102 in a first conductivity type semiconductor substrate 100; Forming an isolation layer (104) for defining active and inactive regions on the semiconductor substrate (100); Forming an electrode (106) on the device isolation film (104); Forming an interlayer insulating film (108) on the electrode (106) and the device isolation film (104); The electrode contact hole 109 is formed by etching the interlayer insulating layer 108, but the width of the electrode contact hole 109 is greater than the width of the electrode 106 so that the upper and both sides of the electrode 106 are exposed. Forming and forming on top of the wells (102); And forming a contact electrode 110 electrically connected to the electrode 106 through the electrode contact hole 109.

According to the present invention for achieving the above object, a contact structure of a semiconductor device includes an electrode 106 formed on the device isolation film 104 and an interlayer formed on the device isolation film 104 including the electrode 106. In the semiconductor device including an insulating film 108 and a contact electrode 110 formed through the interlayer insulating film 108 to be electrically connected to the electrode 106, the width of the contact electrode 110 is the electrode ( Is formed relatively larger than the width of the 106, the contact electrode 110 is formed in contact with the upper and both sides of the electrode 106, is formed in the semiconductor substrate 100 below the electrode 106, The semiconductor substrate 100 may include a well 102 formed in a different conductivity type from that of the semiconductor substrate 100.

(Action)

Referring to FIG. 7, in the novel semiconductor device contact forming method according to the embodiment of the present invention, an n-type well is formed in a p-type semiconductor substrate. An interlayer insulating film is formed on the floating gate and the device isolation film. The interlayer insulating layer is etched to form floating gate contact holes. In this case, the width of the floating gate contact hole is formed to be relatively larger than the width of the floating gate. Thus, by reducing the width of the floating gate, it is possible to reduce the thickness consumption of the floating gate during the floating gate oxidation process, thereby preventing the floating gate contact resistance from increasing. Further, by forming a well of a different conductivity type from the semiconductor substrate in the semiconductor substrate under the floating gate contact region, it is possible to prevent a short between the floating gate contact and the bulk when forming a floating gate contact wider than the floating gate polysilicon film. .

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 6 and 7.

6 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, a semiconductor memory device according to an embodiment of the present invention includes a reference cell 130 having a bit line contact 122 formed on an active region 120, such as a p-type substrate or a p-type well. do. Here, the bit line is not shown. The floating gate 106 is formed of polysilicon so as to overlap a part of the reference cell 130. An n-type well 102 is formed to overlap one end of the floating gate 106. A floating gate contact 110 is formed in the n-type well 102 and has a width relatively larger than that of the floating gate 106.

FIG. 7 is a cross-sectional view taken along the line CC ′ of FIG. 6, illustrating a floating gate contact structure according to the method for forming a contact according to the present invention.

In FIG. 7, in the method for forming a contact of a semiconductor memory device according to an embodiment of the present invention, a novel n-type well 102 according to the present invention is first formed on a p-type substrate or a p-type well 100. Next, a field oxide 104 is formed on the semiconductor substrate 100 to define an active region and an inactive region.

A cell gate oxide (not shown) is formed on the semiconductor substrate 100. After the floating gate polysilicon film is formed on the gate oxide film, an interpoly oxide film (not shown) is formed by locally oxidizing the floating gate polysilicon film using a silicon nitride film mask (not shown). At this time, the interpoly oxide film is formed thinner than the conventional one. This is possible by forming the open area of the silicon nitride film narrower than before. That is, the width of the floating gate 106 is formed to be narrower than conventional.

After the silicon nitride film is stripped, the floating gate polysilicon film is etched using the interpoly oxide film as a mask to form the floating gate 106. In this case, the floating gate 106 extends to the active region 120 to form a contact in the reference cell 130.

After the tunnel oxide (not shown) is formed by the process of oxidizing the semiconductor substrate 100, a control gate (not shown) is formed. A photolithography process and an impurity ion implantation process are performed to form a source region (not shown in the figure) of the cell. Subsequently, a photolithography process and an impurity ion implantation process are performed to form n + and p + source / drain regions.

Next, after the interlayer insulating film 108 is deposited on the entire surface of the semiconductor substrate 100, a contact forming process and a metal process are performed to complete a split gate flash cell structure.

That is, the interlayer insulating layer 108 is etched to form a floating gate contact hole 109. In this case, the floating gate contact hole 109 is formed to be larger than the width of the floating gate 106. This is to reduce the resistance between the floating gate contact 110 and the floating gate 106 by allowing the sidewall of the floating gate 106 to also contact the floating gate contact 110.

On the other hand, since the n-type well 102 is formed in the p-type substrate (p-type well) 100 in the region where the floating gate contact 110 is to be formed, the field oxide layer is formed when the floating gate contact hole 109 is formed. Even if 104 is overetched, a short between the floating gate contact 110 metal and the bulk is prevented.

The floating gate contact 110 is formed by patterning after the floating gate contact hole 109 is filled with a metal film.

The present invention can reduce the thickness consumption of the floating gate during the floating gate oxidation process by reducing the width of the floating gate, thereby preventing the increase of the floating gate contact resistance.

In addition, by forming a well of a different conductivity type from the semiconductor substrate in the semiconductor substrate under the floating gate contact region, a short between the floating gate contact and the bulk can be prevented when forming a floating gate contact wider than the floating gate polysilicon film. It works.

Claims (4)

Forming a second conductivity type well (102) in the first conductivity type semiconductor substrate (100); Forming an isolation layer (104) for defining active and inactive regions on the semiconductor substrate (100); Forming an electrode (106) on the device isolation film (104); Forming an interlayer insulating film (108) on the electrode (106) and the device isolation film (104); The electrode contact hole 109 is formed by etching the interlayer insulating layer 108, but the width of the electrode contact hole 109 is greater than the width of the electrode 106 so that the upper and both sides of the electrode 106 are exposed. Forming and forming on top of the wells (102); Forming a contact electrode (110) electrically connected to the electrode (106) through the electrode contact hole (109). The method of claim 1, The well 102 is a contact of a semiconductor device that is formed to prevent the contact electrode 110 and the semiconductor substrate 100 from shorting when the device isolation layer 104 is overetched when the electrode contact hole 109 is formed. Forming method. The electrode 106 formed on the device isolation film 104, the interlayer insulating film 108 formed on the device isolation film 104 including the electrode 106, and the interlayer insulating film 108 are formed through the electrode 106. A semiconductor device comprising a contact electrode 110 formed to be electrically connected to a semiconductor device. The width of the contact electrode 110 is formed relatively larger than the width of the electrode 106, the contact electrode 110 is formed to contact the upper and both sides of the electrode 106, And a well (102) formed in the semiconductor substrate (100) below the electrode (106), and having a different conductivity type than the semiconductor substrate (100). The method of claim 3, wherein The well 102 is a contact structure of a semiconductor device is formed to prevent a short between the contact electrode 110 and the semiconductor substrate (100).