KR20000019229A - Circuit for generating clock for semiconductor device - Google Patents

Abstract

PURPOSE: A circuit for generating a clock for a semiconductor device is provided to reduce a power consumption. CONSTITUTION: A circuit for generating a clock for a semiconductor device includes a clock buffer (100), a divider(200), a first through third delays(300,400,600), a switch signal generator(500), an output driver(800) and a switch circuit(700). The circuit for generating clock generates an internal clock synchronized with an external clock having a predetermined pulse width. The clock buffer receives the external clock. The divider divides the external clock output from the clock buffer. The first delay delays a divided signal divided by the divider. The second delay receives the divided signal divided delayed by the first delay and generates a first group of delay signals, each having a predetermined delay time on the divided signals. The switch signal generator receives the first group of delay signals and generates a plurality of switch signals varied by a time period of the divided signal in response to the divided signal. The third delay receives the external clock output from the clock buffer and generates a second group of switch signals, each having a predetermined delay time on the external clock. The output driver generates an internal clock. The switch circuit transfers a delay signal to the output driver. The delay signal has a phase same as the external clock among the external clock delayed by the clock buffer and the second group of delay signals output from the third delay in response to the switch signals.

Description

A CIRCUIT FOR GENERATING CLOCK OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a clock generating circuit for generating an internal clock signal synchronized with an external clock signal.

1 and 2, the clock generation circuit according to the related art includes a clock buffer 10, a main delay circuit 20, a first delay circuit 30, a switch control signal generator 40, and a second. The delay circuit part 50, the switch circuit 60, and the output drive circuit 70 are provided. The clock buffer 10 receives an external clock signal CLK from the outside. The main delay circuit 20 outputs a delay signal DCLK0 which delays the clock signal PCLK delayed by the clock buffer 10 by a predetermined time. The first delay circuit unit 30 receives the delay signal DCLK0 from the main delay circuit 20 and includes a plurality of first delay signals having predetermined delay times for the delay signal DCLK0, respectively. Outputs DCLK1, DCLK2, ..., DCLKn).

The switch control signal generator 40 controls the first delay signals DCLK1, DCLK2,. DCLKn) and outputs a plurality of switch control signals CON1, CON2, ... CONn, CONn + 1 for controlling the switch circuit 60. The second delay circuit unit 50 receives the clock signal PCLK from the clock buffer 10 and includes a plurality of second delay signals D having predetermined delay times with respect to the clock signal PCLK. Outputs' CLK1, D'CLK2, ..., D'CLKn). The switch circuit 60 outputs the output from the clock buffer 10 under the control of the switch control signals CON1, CON2,... CONn, CONn + 1 from the switch control signal generator 40. The conductive path of the clock signal PCLK supplied to the driving circuit 70 is switched. The output driving circuit 70 outputs the internal clock signal PCLK_M buffered with the clock signal PCLK supplied through the switch circuit 60 to an internal circuit (not shown).

Referring to FIG. 3, the clock buffer 10 receives the external clock signal CLK and outputs the clock signal PCLK having a predetermined delay time. The main delay circuit 20 delays and outputs the clock signal PCLK. Delay circuits D1, D2,..., Dn of the first delay circuit unit 30 receive the clock signal PCLK and the first delay signals DCLK1, DCLK2 having predetermined delay times, respectively. , ..., DCLKn). The switch control signal generation circuits SC1, SC2,..., SCn, SCn + 1 of the switch control signal generation unit 40 receive the first delay signals DCLK1, DCLK2,..., DCLKn. The switch control signals CON1, CON2, ... CONn, CONn + for receiving and storing and for controlling the switches S1, S2, ..., Sn, Sn + 1 of the switch circuit 60; Output 1).

Delay circuits D'1, D'2,..., D'n of the second delay circuit unit 50 have a predetermined delay time from the clock signal PCLK from the clock buffer 10. The branch outputs the second delay signals D'CLK1, D'CLK2, ..., D'CLKn. The switches S1, S2,..., Sn, Sn + 1 of the switch circuit 60 are the switch control signals CON1, CON2, ... from the switch control signal generator 40. The external clock signal of the second delay signals D'CLK1, D'CLK2, ..., D'CLKn delayed through the second delay circuit unit 50 under the control of CONn and CONn + 1. One delay signal having a phase coinciding with CLK is supplied to the output driving circuit 70.

The clock generation circuit receives the external clock signal CLK from the outside and outputs the internal clock signal PCLK_M for operation of the internal circuit. The clock generation circuit is a synchronous delay line (SDL) type synchronization device for preventing a difference in delay time between the external clock signal CLK and the internal clock signal PCLK_M. The clock generation circuit of the SDL scheme includes delay circuits such as the main delay circuit 20 and the first and second delay circuit units 30 and 50. The clock generation circuit of the SDL method outputs the internal clock signal PCLK_M having a phase coinciding with the external clock signal CLK. For this reason, the delay of the first and second delay circuit parts 30 and 50 is made to match the phase of the external clock signal CLK and the internal clock signal PCLK_M at every period of the external clock signal CLK. The circuits are all operated. This causes a problem in that the clock generation circuit consumes a large amount of current to generate the internal clock signal PCLK_M.

It is therefore an object of the present invention to provide a clock generation circuit of a semiconductor device with reduced current consumption.

1 is a block diagram of a clock generation circuit according to the prior art;

2 is a circuit diagram of the clock generation circuit of FIG. 1;

3 is an operation timing diagram illustrating an operation of the clock generation circuit of FIG. 1;

4 is a block diagram of a clock generation circuit according to the present invention;

5 is a detailed circuit diagram of the clock generation circuit of FIG. 4;

6 is an operation timing diagram illustrating an operation of the clock generation circuit of FIG. 4.

* Explanation of symbols on the main parts of the drawings

100: clock buffer 200: frequency divider circuit

300: main delay circuit 400: first delay circuit portion

500: switch control signal generation circuit 600: second delay circuit portion

700: switch circuit 800: output drive circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a clock generation circuit includes a clock buffer for receiving the external clock; Dividing means for dividing the external clock from the clock buffer; First delay means for delaying the divided signal divided by said distributing means; Second delay means for receiving the divided signal delayed by the first delay means and outputting a first group of delay signals each having predetermined delay times for the divided signal; Switch signal generation means for receiving the delay signals of the first group and generating a plurality of switch signals that are varied in accordance with a period of the division signal in response to the division signal from the division means; Third delay means for receiving said external clock from said clock buffer and outputting a second group of delay signals each having predetermined delay times for said external clock signal; An output driver circuit for outputting the internal clock; Driving the output of one delay signal having a phase coinciding with the external clock among the external clock delayed by the clock buffer and the second group of delay signals from the third delay means in response to the switch signals; It includes a switch circuit for transferring to the circuit.

In this embodiment, the second delay means comprises a plurality of delay circuits for delaying the divided signal from the divider to have predetermined delay times, respectively.

In this embodiment, the switch signal generating means comprises: a latch circuit portion for latching the first group delay signals from the second delay means, delay signals of the first group latched in the latch circuit portion and the; And a switch signal generating circuit for combining the divided signals from the distributing means to generate the switch signals.

(Action)

By such an apparatus, by dividing an external clock signal and performing a switching operation every cycle of the divided signal having a period longer than the external clock, current consumption caused by switching every cycle of the external clock can be reduced. have.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 6 according to an embodiment of the present invention.

Referring to FIG. 4, the novel clock generator circuit of the present invention includes a clock buffer 100, a divider circuit 200, a main delay circuit 300, a first delay circuit unit 400, and a switch control signal generator 500. And a second delay circuit unit 600, a switch circuit 700, and an output driving circuit 800. The clock buffer 100 receives an external clock signal CLK from the outside and outputs a clock signal PCLK having a predetermined delay time. The division circuit 200 outputs a division signal PCLK_S obtained by dividing the clock signal PCLK from the clock buffer 100 by a predetermined magnification. The main delay circuit 300 outputs a delay signal DCLK0 delaying the divided signal PCLK_S. The first delay circuit unit 400 receives the delay signal DCLK0 and outputs a plurality of first delay signals DCLK1, DCLK2,..., DCLKn each having predetermined delay times.

The switch signal generator 500 may control the first delay signals from the first delay circuit unit 400 by controlling the divided signal PCLK_S having a period of a predetermined magnification with respect to the external clock signal CLK. Stores (DCLK1, DCLK2, ..., DCLKn) and outputs a plurality of switch control signals (CON1, CON2, ... CONn, CONn + 1) for controlling the switch circuit 700. The second delay circuit unit 600 receives the clock signal PCLK from the clock buffer 100 and performs second delay signals D'CLK1, D'CLK2, ..., each having predetermined delay times. , D'CLKn). The switch circuit 700 receives one of the clock signal PCLK and the second delay signals D'CLK1, D'CLK2, ..., D'CLKn from the second delay circuit unit 600. Transfer to the output driving circuit 800. The output driving circuit 800 outputs an internal clock signal PCLK_M buffered with a delay signal supplied through the switch circuit 700 to an internal circuit.

In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.

Referring to FIG. 3, the clock generation circuit according to the present invention includes a clock buffer 100, a divider circuit 200, a main delay circuit 300, a first delay circuit unit 400, a switch control signal generator 500, The second delay circuit unit 600, the switch circuit 700, and the output driving circuit 800 are included. The clock buffer 100 receives an external clock signal CLK from the outside and outputs a clock signal PCLK having a predetermined delay time. The division circuit 200 outputs a division signal PCLK_S obtained by dividing the clock signal PCLK from the clock buffer 100 by a predetermined magnification. The main delay circuit 300 outputs a delay signal DCLK0 delaying the divided signal PCLK_S. The first delay circuit unit 400 receives the delay signal DCLK0 and outputs a plurality of first delay signals DCLK1, DCLK2,..., DCLKn each having predetermined delay times.

The switch signal generator 500 may control the first delay signals from the first delay circuit unit 400 by controlling the divided signal PCLK_S having a period of a predetermined magnification with respect to the external clock signal CLK. Stores (DCLK1, DCLK2, ..., DCLKn) and outputs a plurality of switch control signals (CON1, CON2, ... CONn, CONn + 1) for controlling the switch circuit 700. The second delay circuit unit 600 receives the clock signal PCLK from the clock buffer 100 and performs second delay signals D'CLK1, D'CLK2, ..., each having predetermined delay times. , D'CLKn). The switch circuit 700 receives one of the clock signal PCLK and the second delay signals D'CLK1, D'CLK2, ..., D'CLKn from the second delay circuit unit 600. Transfer to the output driving circuit 800. The output driving circuit 800 outputs the internal clock signal PCLK_M buffering the delay signal supplied through the switch circuit 700 to an internal circuit.

Referring to FIG. 5, an input terminal of the clock buffer 100 is connected to the external clock signal CLK input terminal and an output terminal is connected to an input terminal of the division circuit 200. An input terminal of the division circuit 200 is connected to an output terminal of the clock buffer 100 and an output terminal is connected to an input terminal of the main delay circuit 300. The main delay circuit 300 includes inverters 310, 320, 330, and 340 connected in series between the division circuit 200 and the first delay circuit unit 400. The first delay circuit unit 400 includes a plurality of delay circuits 410. Each delay circuit 410 includes inverters 411 and 412 connected in series.

The switch control signal generator 500 includes an inverter 510, a plurality of latch circuits 520, and a plurality of combination circuits 530 and 540. The input terminal of the inverter 510 is connected to the output terminal of the frequency divider circuit 200 and the output terminal is connected to the transfer gates 521 and 524 of the latch circuit portion 520. Each latch circuit portion 520 includes transfer gates 521 and 524, latch circuits 522 and 525, and an inverter 523. The transfer gate 521 is a current path formed between the output terminals of the corresponding delay circuits 300 and 400 and the inverter 523, and a gate connected to the division circuit 200 and the inverter 510, respectively. Have them. The latch circuit 522 is connected between the transfer gate 521 and the inverter 523 and includes inverters having input / output terminals cross-connected. The transfer gate 524 has a current path formed between the output terminal of the inverter 523 and the latch circuit 525 and gates connected to the division circuit 200 and the inverter 510, respectively. The latch circuit 522 is connected between the transfer gate 521 and the inverter 523 and includes inverters having input / output terminals cross-connected.

The combination circuit 530 includes end gates 521 and 532 and an inverter 533. The first input terminal of the AND gate 521 is connected to a power supply voltage VCC, the second input terminal is connected to the latch circuit 525, and the output terminal is a second input terminal of the AND gate 532. Is connected to. The first input terminal of the AND gate 532 is connected to the power supply voltage VCC, the second input terminal is connected to the output terminal of the AND gate 531, and the output terminal is connected to the switch circuit unit 700. Connected. The input terminal of the inverter 533 is connected to the output terminal of the AND gate 531 and the output terminal is connected to the first input terminals of the AND gates 531 and 532 of the combination circuit 530 of the next stage. do.

The second delay circuit unit 600 includes a plurality of delay circuits 610. Each delay circuit 610 includes inverters 611 and 612 connected in series. The switch circuit 700 includes a plurality of switch circuits 710. Each switch circuit 710 includes an inverter 711 and a transfer gate 712. An input terminal of the inverter 711 is connected to an output terminal of the AND gate 532 of the combination circuit 530 and an output terminal is connected to a corresponding gate of the transfer gate. The transfer gate 712 is a current path formed between the output terminal of the delay circuits of the corresponding clock buffer and the second delay circuit unit 600 and the input terminal of the output driving circuit 800 and the combination circuit 530. And gates connected to the output terminals of the AND gate 532 and the inverter 711, respectively. The output drive circuit 800 includes inverters 810 and 820. The inverters 810 and 820 are connected in series between the output terminal of the switch circuit unit 700 and the internal circuit.

4 to 6, the operation of the clock generation circuit according to the preferred embodiment of the present invention will be described.

4 to 6, the clock buffer 100 of FIG. 5 receives the external clock signal CLK and outputs the clock signal PCLK having a predetermined delay time. The division circuit 200 outputs the division signal PCLK_S obtained by dividing the clock signal PCLK from the clock buffer 100 at a predetermined magnification. For example, assuming that the division circuit divides the clock signal PCLK by '2', the period of the division signal PCLK_S is twice the period of the clock signal PCLK. The main delay circuit 300 outputs a delay signal DCLK0 delaying the divided signal PCLK_S. The delay circuits D1, D2,..., And Dn of the first delay circuit unit 400 receive the delay signal DCLK0 and each of the first delay signals DCLK1, which have predetermined delay times. Outputs DCLK2, ..., DCLKn).

The switch control signal generation circuits SC1, SC2,..., SCn, and SCn + 1 of the switch control signal generation unit 500 receive the first delay signals DCLK1, DCLK2,..., DCLKn. The switch control signals CON1, CON2, ... CONn, CONn + for receiving and storing and controlling the switches S1, S2, ..., Sn, Sn + 1 of the switch circuit 700; Output 1). The switch control signal generator 500 may include one delay signal having a phase coinciding with the clock signal PCLK among the switch control signal generators SC1, SC2,..., SCn, and SCn + 1. The switch control signal CON of a high level is output through the switch signal generation circuit SC supplied with DCLK. When the switch control signal CON of a low level is output from one of the switch control signal generation circuits SC1, SC2,..., SCn, SCn + 1, another switch control signal is generated. The circuits output the high level switch control signal CON.

Delay circuits D ′ 1, D ′ 2,..., D ′ n of the second delay circuit unit 600 may set the clock signal PCLK from the clock buffer 100 to a predetermined delay time. The branch outputs the second delay signals D'CLK1, D'CLK2, ..., D'CLKn. The switches S1, S2,..., Sn, Sn + 1 of the switch circuit 700 are connected to the switch control signals CON1, CON2, ... from the switch control signal generator 40. The second delay signals D'CLK1, D'CLK2, ..., D'CLKn delayed through the clock buffer 100 and the second delay circuit unit 50 under the control of CONn and CONn + 1. One delay signal is supplied to the output driving circuit 800.

The clock generation circuit according to the related art selects and outputs the internal clock signal PCLK_M corresponding to the external clock signal CLK for each period of the external clock signal CLK. However, in the clock synchronizing circuit according to the present invention, the division circuit 200 matches the internal clock signal PCLK_M with the external clock signal CLK according to the division ratio at which the external clock signal CLK is divided. Do this. For example, as described above, when the division circuit 200 divides the external clock signal CLK by '2', the delay delayed by the main delay circuit 300 and the first delay circuit unit 400 may occur. The periods of the delay signals DCLK1, DCLK2,..., DCLKn are twice the period of the external clock signal CLK.

The switch control signal generating circuits SC1, SC2,..., SCn, and SCn + 1 of the switch signal generator 500 may generate the external clock signal once every two periods of the external clock signal CLK. The switch control signals CON for selecting the clock signal PCLK corresponding to the period of CLK are varied. The switch circuits S1, S2,..., Sn and Sn + 1 perform a switching operation once every two cycles of the external clock signal CLK by the control of the switch control signal CON. As illustrated in FIG. 6, the clock generation circuit outputs the internal clock signal PCLK_M having the same phase as the external clock signal CLK once every two periods of the external clock signal CLK. Thus, the current consumed by the first delay circuit portion 400 of the clock generation circuit according to the present invention can be reduced by half compared to that of the conventional clock generation circuit. The first delay circuit unit 400 is selected by selecting the clock signal PCLK corresponding to a period of the external clock signal CLK according to the division ratio for dividing the external clock signal CLK by the division circuit 200. The current consumed at the N can be reduced in proportion to the division ratio.

In the above, the configuration and operation of the circuit according to the present invention is shown according to the above description and drawings, but this is merely described for example, and various changes and modifications are possible without departing from the technical spirit of the present invention. .

As described above, by dividing an external clock signal and performing a switching operation every period of the divided signal having a period longer than the external clock, current consumption caused by switching every cycle of the external clock can be reduced. .

Claims (3)

In a clock generation circuit for generating an internal clock synchronized with an external clock having a predetermined pulse width: A clock buffer which receives the external clock; Dividing means for dividing the external clock from the clock buffer; First delay means for delaying the divided signal divided by said distributing means; Second delay means for receiving the divided signal delayed by the first delay means and outputting a first group of delay signals each having predetermined delay times for the divided signal; Switch signal generation means for receiving the delay signals of the first group and generating a plurality of switch signals that are varied in accordance with a period of the division signal in response to the division signal from the division means; Third delay means for receiving said external clock from said clock buffer and outputting a second group of delay signals each having predetermined delay times for said external clock signal; An output driver circuit for outputting the internal clock; Driving the output of one delay signal having a phase coinciding with the external clock among the external clock delayed by the clock buffer and the second group of delay signals from the third delay means in response to the switch signals; A clock generating circuit comprising a switch circuit for transmitting to the circuit. The method of claim 1, And the second delay means comprises a plurality of delay circuits for delaying the divided signal from the frequency division means to have predetermined delay times, respectively. The method of claim 1, The switch signal generating means, A latch circuit portion for latching the first group of delay signals from the second delay means; And a switch signal generation circuit for generating the switch signals by combining the first group of delay signals latched in the latch circuit portion and the division signal from the division means.