KR20000018867A - Bus arbitration system in exchange system - Google Patents

Abstract

PURPOSE: A bus arbitration system in an exchange system is provided to improve the use efficiency of the bus and prevent a communication from being accumulated, and give a priority right to a processor which a data to process is crowded, thereby preventing a data from being crowded. CONSTITUTION: An arbitration circuit part is only in a master processor. A bus occupy requirement signal of all processor is approved and, simultaneously, a processor state signal which presents a transmitting standby state of the bus, an important degree of each processor, and a flow degree of a data and so on, and a state of each node is confirmed, thereby a bus occupy priority order is given. A bus occupy permission signal is generated, as a result, a bus occupy right of each processor is arbitrated.

Description

Bus arbitration system at the exchange

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration system of an exchange. In particular, the present invention relates to a bus arbitration system, and gives priority to the processor according to the state and importance of each processor when giving a share of the common bus. It relates to a bus arbitration system at an exchange to arbitrate a common bus.

In the conventional exchange, a serial bus is used as a common bus system in which several processors are used together, and a circuit for controlling bus arbitration so that only one processor occupies the bus at any point in time for accurate data transfer is possible. Is necessary.

In the conventional bus arbitration system, as illustrated in FIG. 1, a bus that arbitrates so that only one processor may occupy a serial bus in the master processor 10 and the plurality of slave processors 20-1 to 20-n is shown. Arbitrary circuit section 11, 21, Serial input output (SIO) 12, 22 for controlling input / output of data using HDLC (High-level Data Link Control) with serial communication channel, and frame to be sent to another processor It includes a transmission FIFO (13, 23) for storing the temporary, and the receiving FIFO (14, 24) for temporarily storing a frame authorized by another processor. In addition, the processor 10, 20-1 to 20-n may further include a counter and complicated circuits required for occupying the bus.

Here, the data DATA represent frames transmitted and received between the processors 10, 20-1 to 20-n, and the clocks correspond to synchronization between the processors 10, 20-1 to 20-n. Represents a clock signal as a reference so that data DATA can be transmitted. In addition, as a signal for arbitrating the serial bus, a response output signal ASTOUT, a response clock signal ASTCLK, a frame sync signal / FRS, a response signal / AST, a bus occupancy request signal / RTS, and a bus There is an occupancy permission signal (/ CTS).

Referring to the operation of the bus arbitration system configured as described above, each processor (10, 20-1 ~ 20-n), if there is data to be transmitted, temporarily stores the corresponding transmission data in the transmission FIFO (13, 23) When the authority to occupy the bus is synchronized, the frame synchronization signal (/ FRS) is synchronized, and then the data stored in the corresponding transmission FIFOs (13, 23) is read out and converted into HDLC-type frames. To the processor.

In this case, each of the processors 10, 20-1 through 20-n searches for a frame on the serial bus and transmits it to itself, i.e., the identification address of the frame corresponds to its own address. If there is a match, the frame is received and temporarily stored in the reception buffers 14 and 24.

The SIOs 12 and 22 then read and process the data stored in the receive buffers 14 and 24.

Herein, the process of granting the bus occupancy authority is as follows. Each processor 20-1 to 20-n generates a bus occupancy request signal / RTS to generate a bus arbitration circuit 11 of the master processor 10. To be sent.

Accordingly, the bus arbitration circuit unit 11 receives the bus occupancy request signal / RTS, generates a response clock signal ASTCLK, and transmits the response clock signal ASTCLK to each processor 20-1 to 20-n. -1 ~ 20-n) receives the corresponding response clock signal (ASTCLK) to drive the counter, and when the processor reaches a certain value first, it generates and sends a bus occupancy permission signal (/ CTS) to another processor and sends it to itself. Indicate that you have occupied.

Then, the bus arbitration circuit unit 11 of the master processor 10 generates the response output signal ASTOUT and stops the generation of the response clock signal ASTCLK to stop the counters of the processors that do not occupy the bus.

When the processor occupying the serial bus sends out all the frames and then inverts the bus occupancy request signal / RTS again, the bus arbitration circuit 11 of the master processor 10 returns the response clock signal. Generate (ASTCLK) to send the next bus occupancy request signal (/ RTS) to allow another processor to occupy the serial bus.

As such, all processors 10, 20-1 through 20-n are authorized to occupy the serial bus in a round robin manner, and the round robin scheme includes all the processors 10, 20. Since -1 to 20-n) have the same chance to occupy the serial bus, an irrational case can occur where a large amount of data is stored in a buffer on a processor with a lot of data to transmit.

In other words, in the prior art, all processors have the same opportunity to occupy the bus regardless of their status and importance, but there is a lot of data to send to the transmit FIFO, but not at the right time. Data may be lost due to exceeding the capacity of.

In addition, when the processor occupying the bus continues to occupy the bus even when an error occurs, even if the possession of the bus is transferred to another processor, the two processors may occupy the bus at the same time and data collision may occur.

In order to solve the problems as described above, the present invention prioritizes the common bus in the communication between the processors using the common bus in the exchange, according to the state and importance of each processor to give priority to the corresponding common bus. By using arbitration, an object of the present invention is to provide a bus arbitration system in an exchange implemented to reduce communication delay and to improve the performance of a corresponding bus.

1 is a block diagram illustrating a bus arbitration system in a conventional exchange.

2 is a block diagram illustrating a bus arbitration system in an exchange according to an embodiment of the present invention;

3 is a timing diagram illustrating signals related to the occupancy of the bus in FIG. 2; FIG.

Explanation of symbols on the main parts of the drawings

30: master processor 40-1 to 40-n: slave processor

31, 41: SIO (Serial Input Output)

32, 42: transmit FIFO (First In First Out)

33, 43: Receive FIFO 34: Bus Abitration Logic

In order to achieve the above object, the present invention includes a master processor and a plurality of slave processors, and includes a bus arbitration circuit unit only for the master processor to receive a bus occupancy request signal from each processor and to simultaneously apply a processor status signal. And generate a bus occupancy permission signal to arbitrate bus occupancy rights of the respective processors.

Hereinafter, with reference to the accompanying drawings will be described as follows.

FIG. 2 is a block diagram illustrating a bus arbitration system in an exchange according to an exemplary embodiment of the present invention, and FIG. 3 is a timing diagram illustrating signals related to occupancy of a bus in FIG.

In the switch according to the embodiment of the present invention, the bus arbitration system includes one master processor 30 and a plurality of slave processors 40-1 to 40-n, as shown in FIG. Each processor 30, 40-1 to 40-n includes an SIO 31 and 41, a transmission FIFO 32 and 42, and a reception FIFO 33 and 43, respectively, and includes a corresponding master processor 30. ) Further comprises a bus arbitration circuitry 34.

The master processor 30 controls bus occupancy arbitration of all the processors 30 and 40-1 to 40-n, and the bus occupancy request signal from each of the processors 30 and 40-1 to 40-n. / RTSM, / RTS1 to / RTSn), and at the same time waiting for the transmission of the transmission FIFO (32, 42) provided in each processor (30, 40-1 ~ 40-n), each processor (30, 40) After checking the status of each node by receiving the Processor State Signal, which indicates the importance of -1 to 40-n, the flow of data, etc., the bus occupancy permission signal (/ CTSM, / CTS1 to / CTSn) is applied. It generates and applies it to each of the processors 30, 40-1 to 40-n so as to collectively process the arbitration of the bus.

In addition, each of the processors 30, 40-1 to 40-n sends clock signals CLOCK to synchronize synchronization when data DATA is transmitted through the serial bus.

The operation of the bus arbitration system in the exchange according to the embodiment of the present invention will be described as follows.

First, each processor 30, 40-1 to 40-n, when there is data to send, temporarily stores the corresponding transmission data in the transmission FIFOs 32 and 42, respectively, and has the authority to occupy the bus. When given, the clock signal CLOCK is synchronized, and then the data stored in the transmission FIFOs 32 and 42 is read, converted into HDLC frames, and transmitted to another processor.

Here, referring to the process of granting the occupancy rights of the bus, the bus occupancy request signals (/ RTSM, / RTS1 to / RTSn) applied from all the processors 30, 40-1 to 40-n in the master processor 30 will be described. ) And generate bus occupancy permission signals (/ CTSM, / CTS1 to / CTSn) in consideration of the state of transmit FIFOs 32 and 42 provided in the respective processors 30, 40-1 to 40-n. Authority to occupy the bus.

That is, high priority is given to a processor having a large amount of transmitted data or having a high flow of data in the transmit FIFOs 32 and 42, and a low priority is given to a processor having a relatively small amount of data waiting or having a low data flow. In addition, even when an error occurs in the processor currently occupying the bus and tries to continue to occupy the bus, the master processor 30 forcibly removes the bus occupancy right and gives the bus possession right to a higher priority processor. To facilitate data flow.

Then, referring to FIG. 2, the operation of each component will be described in more detail. First, in the SIOs 31 and 41 provided in the processors 30 and 40-1 to 40-n, the bus occupancy request signal ( / RTSM and / RTS1 to / RTSn) are generated and sent to the bus arbitration circuit section 34 provided in the master processor 30.

At the same time, in the transmission FIFOs 32 and 42 provided in each of the processors 30, 40-1 to 40-n, an Almost Full State Signal (AMF, AT1), which is a signal indicating a state in which data is almost filled. AFn) or a half full state signal (HFM, HF1 to HFn), which is a signal indicating that the data is half filled, and sent to the bus arbitration circuit unit 34 provided in the master processor 30. do.

Accordingly, the bus arbitration circuit section 34 receives the bus occupancy request signals / RTSM and / RTS1 to / RTSn from the respective SIOs 31 and 41, respectively, and at the same time receives the processor from the respective transmission FIFOs 32 and 42. Among the status signals, the full status signals AFM, AT1 to AFn, or the half status signals HFM and HF1 to HFn are respectively applied to determine the processors 30, 40-1 to 40-n to which the bus is to be assigned. The occupation permission signals / CTSM and / CTS1 to / CTSn are generated and applied to the SIOs 31 and 41 provided in the processors 30, 40-1 to 40-n, respectively.

Accordingly, the processor 30, 40-1 to 40-n, which has been granted bus occupancy rights, reads data stored in the transmission FIFOs 32 and 42, converts the data into HDLC-type frames, and converts the corresponding data DATA. Is synchronized with the clock signal (CLOCK) and transmitted to another processor.

For example, the above-described operation will be described with reference to FIG. 3. FIG. 3 illustrates bus occupancy request signals (/ RTSM) of the master processor 30 and the first and second slave processors 40-1 and 40-2. A timing diagram showing a process in which the bus occupancy permission signals / CTSM, / CTS1, and / CTS2 are output to / RTS1 and / RTS2 and the authority to occupy the bus is given.

Initially, only the master bus occupancy request signal / RTSM of the master processor 30 exists, so that the master processor occupies the bus by applying a master bus occupancy permission signal / CTSM to the master processor 30, and the master processor 30 The second slave processor 40-2 has occupied the bus after a clock at the moment when the master bus occupancy permission signal / CTSM is inverted.

This is because the first slave processor 40-1 generates the first bus occupancy request signal / RTS1 before the bus occupancy request signal / RTS1 of the second slave processor 40-2. At this moment, the master processor 30 checks the FIFO state and recognizes that the second full state signal AF2 has been generated by the bus arbitration circuit unit 34 of the master processor 30 and the second slave. The processor 40-2 is first given a bus occupancy permission signal / CTS2.

Next, the second slave processor 40-2 releases the bus occupancy and then transfers the bus occupancy right to the first slave processor 40-1.

As described above, since the bus arbitration circuit section 34 is only in the master processor 30, the overall circuit configuration is simplified and the bus use of the lower slave processors 40-1 to 40-n is reduced. Management is enhanced, and processors with different data processing speeds and requirements, such as the main processor, the device processor, and the number seven (No. 7) processor in the exchange, may use a common bus.

In addition, the priority of occupying the bus can be set according to the buffer waiting state, the importance of each processor, the flow of data, etc., thereby improving the bus utilization efficiency and preventing communication jams, and temporarily processing data. Priority can be given to congested processors to prevent data congestion.

In addition, if the present invention is applied, it is possible to use in a communication method using a single bus of one-to-multipoint method in common.

As described above, according to the present invention, the bus arbitration circuit unit is provided only in the master processor to receive the bus occupancy request signals of all the processors, and at the same time, the processor status signal indicating the buffer waiting state, the importance of each processor, the degree of data flow, and the like. By checking the status of each node to prioritize bus occupancy and generate bus occupancy permission signals to mediate bus occupancy rights for each processor, it not only improves bus utilization efficiency and prevents traffic congestion, but also temporarily Priority can be given to processors that have congested data to be processed to prevent congestion of data.

Claims (3)

It is provided with a master processor 30 and a plurality of slave processors (40-1 to 40-n), Only the master processor 30 includes a bus arbitration circuit section 34 to receive bus occupancy request signals / RTSM and / RTS1 to / RTSn from each of the processors 30 and 40-1 to 40-n. The bus is exchanged by receiving a processor status signal and generating bus occupancy permission signals (/ CTSM, / CTS1 to / CTSn) to arbitrate bus occupancy rights of the processors 30, 40-1 to 40-n. Arbitration system. The method of claim 1, The bus arbitration circuit unit 34 checks the state of each node according to the processor status signal and gives a bus occupancy priority to each of the processors 30, 40-1 to 40-n. Arbitration system. The method according to claim 1 or 2, The processor status signal is a transmission wait state of the transmission FIFOs 32 and 42 in each of the processors 30 and 40-1 to 40-n, the importance and data of each processor 30 and 40-1 to 40-n. A bus arbitration system at an exchange characterized by indicating a flow degree.