KR20000015949A - Combined program and data nonvolatile memory with concurrent program read/data write capability - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is disclosed which a single set of address lines (Ai) and a single set of data lines (Dj) are used for both read and write operations for both memory arrays. CONSTITUTION: The nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory (11) and an EEPROM (13). A single set of address lines (Ai) and a single set of data lines (Dj) are used for both read and write operations for both memory arrays. Address decoding circuitry includes separate column decoders (31, 33) and data latches (23, 39) for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry (24) associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory.

Description

Combined program and data nonvolatile memory for simultaneous program read / write data

U.S. Patent No. 5,307,314 (Lee) discloses a separate write enable input ( And Disclosed is a memory device divided into banks having a. Two memory banks can be accessed at the same address at the same time. When the two write enable signals are in an active state, the memory device performs word writing to the same address position of both memory banks. The two write enable signals are inactive and a single output enable signal ( Becomes), the memory device performs word reading from the same address position of both memory banks. When one of the two write enable signals becomes active, the memory device performs byte writing only to one memory bank. The logic circuit of the memory device also allows separate read / write operations when one of the two write enable signals becomes active and the output enable signal becomes active. Thus, byte write is performed from a memory bank corresponding to the active write enable signal, while byte write is performed from another memory bank corresponding to the active write enable signal. Here, both memory banks are accessed with the same address. Each bank has its own set of byte widths of data input / output lines.

U.S. Patent 5,513,139 (Butler) discloses a memory having two address decoders. One decoder is for the read operation and the other individual decoder is for the write operation. The memory also has separate input and output data buses. Both address decoders receive addresses having a sequential order from an address counter and decode the address bits to scan rows of memory cells that are in the opposite direction to this sequential direction. Thus, memory rows can be written sequentially in ascending order and read sequentially in descending order (or vice versa). In addition, the address counter is a binary counter having an output provided to the write decoder, which is shifted by one bit from the output provided to the read decoder, so that a read cycle occurs twice per write cycle. The number of memory rows is a multiple of (n + 1) to prevent both reading and writing of memory rows, where "n" is the ratio of read frequencies to write frequencies (e.g., 2: 1). .

U.S. Patent 5,502,683 (Marchioro) discloses a dual port data cache memory using two row decoders, one for each word line or row. Each row decoder enables a given word line when its corresponding row is accessed (read and written) for the address input. The storage cells of the active word lines are accessed by bit lines suitably connected to sense amplifiers or write control circuits. The rows are organized into words having a predetermined bit length, and each row is separated by column boundaries into four words. The two data ports each access a different one of the four possible word strings through the data multiplexer. In order to avoid collisions between two row decoders trying to drive the same word line, an access switch is placed in each row at the boundary between these word lines. These access switches are normally closed so that each word line is completely connected. However, if two row decoders access the same row, the access switch is opened by a control logic circuit (including an address comparator) to separate the word lines of the row into two separate parts. In this manner, the memory circuits can independently and independently access two different words of the memory array simultaneously.

US Pat. No. 5,367,494 (Shenbanow et al.) Discloses a memory having a plurality of memory banks each having its own address latch and decoder, data input latch and driver, data output latch and driver. Control signals include read / write signals, address strobes, data in strobes, and data out strobes, which are provided in all memory banks and multiple bit address banks, and include data in and data out bank address signals. The signals are decoded and provided only to the selected memory bank. The memory banks selected by these control signals can latch addresses and latch data and drive output data as required. This configuration allows time overlapping memory access of different memory banks.

U.S. Patent 5,361,343 (Kosonocky et al.) Discloses a system having two nonvolatile memory arrays. Each array has its own address register, decoder and gating and its erase and program voltage switches. The array shares input and output data paths through common data in latches, data output multiplexers, and input / output buffers. Various registers, switches, multiplexers, and enable signals are controlled by logic circuitry that includes an array selection circuit that can select one array for write operations and another array for simultaneous read operations.

When designing a memory device capable of simultaneous read and write operations, substantial circuit duplication is provided when addressing flexibility is required. Simpler devices with minimal control logic and addressing circuitry are typically limited in their simultaneous read / write capabilities, such as the same address access of two memory banks or the sequential scanning of addresses. Memory devices capable of virtually any independent access to two or more memory addresses typically have at least duplicated addressing circuitry simultaneously, such as two or more row decoders for different memory banks or for separate read and write operations. . There may be separate data input and data output paths or replicated data paths for different required memory accesses. One reason for this complexity is due to the fact that memory read operations take less time to complete than memory write operations. In a nonvolatile memory device, the read operation takes only 150 to 200 nanoseconds per address, the write operation takes about 150 μm byte load cycles, and a complete page write takes 10 ms. will be. Thus, reading one from many storage locations will take time to write only one byte or one page of data. By logical addressing (and data) circuits, the address lines (and data lines) are freely used for read operations, and the write operations are made at different addresses with different sets of data bits.

There may be applications that require both high density RAM memory, which stores relatively permanent program instruction code, and smaller data memory, which stores parameters that need to be updated frequently. It would be desirable to have a memory device that combines both types of memory into a single chip. For practical use, such a memory device needs to have a read operation from the program memory and a write operation from the data memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a combined program and data non-volatile memory device in which program reading and data writing are performed simultaneously, without sharing the independent addressing and data access to the program and data memory arrays and possibly sharing as much circuitry as possible. It is.

The present invention relates to a nonvolatile semiconductor memory (eg EPROM, flash memory, EEPROM). More specifically, the invention relates to a plurality of memory bank configurations having addressing and read / write circuits capable of simultaneous read and write operations.

1 is a plan view of a schematic block of a nonvolatile memory device according to the present invention;

2A and 2B are timing diagrams illustrating read and write operations including simultaneous read operations of program memory during write cycles of the data memory of the memory device for each memory array of the memory device of FIG.

The object of the present invention is achieved by, for example, a nonvolatile memory device having two memory arrays to be used as relatively permanent program memory and to be used as relatively frequent updated data memory. This nonvolatile memory device includes a single set of data lines and a single set of address lines used for two memory arrays. The memory device also has address decoding means comprising a shared row decoder common to both memory arrays, wherein the row address latch circuit 24 associated with the data memory receives the decoded row address for the data memory array during a write operation. This is to free the shared row decoder for use in one or more simultaneous read operations for other memory arrays, such as program memory. Both arrays include their individual column decoders, column select circuits and data latches, while these arrays share a common row decoder, common sense amplifiers, data I / O buffers and control logic circuits. The control logic circuit controls various elements of the apparatus to perform a selected read or write operation in the selected memory array in response to the input control signal.

In Fig. 1, the nonvolatile memory device of the present invention is a combination of a program memory 11 and a data memory 13. The program memory 11 may be a flash memory, which means that it is initially programmed with program command code and is updated almost (or not at all). The data memory 13 may be configured as an EEPROM and may be programmed with data parameters and updated frequently. The two memory arrays 11 and 13 need not be the same size, and it is common for the program memory 11 to be larger than the data memory 13. For example, program memory 11 may be a 512K × 8 flash array (i.e., 4 megabits [Mbit]), which may be divided into 2K 256 byte sectors for writing. The data memory 13 can be a single type of 32K x 8 bit EEPROM, and can write a single byte and a page of 16 bytes.

The two memories 11, 13 of the memory device comprise a common address input line A _i , a significant amount of address decoding circuitry, in particular a common row decoder 15, a common data input / output line D _j , and a sense amplifier. Important data circuits including 17 and I / O buffer circuit 19 are shared. Control signal or output enable signal for reading And write enable signals , But the chip enable signal corresponding to the flash memory array 11 and the EEPROM memory array 13 , Are individual. The control logic circuit 21 for the memory device is necessarily shared by both memory arrays. This resource sharing allows smaller memory devices to be configured with fewer pins required for address and data. This is because unnecessary duplication of circuits and signal paths can be avoided. However, the memory device may still have simultaneous access to the two memory arrays 11 and 13. Simultaneous access provides data memory 13 with shared address and data resources having multiple latch circuits 23, 24, and 27, in particular by use by program memory 11 during a write operation to data memory 13. Is achieved by the row address latch 24 which frees the shared row decoder 15 for this purpose.

First, in the specific address circuit of the memory device, the address input Ai is received by the address buffers 25, 27 and 29. In the case of column address bits for the data memory 13, the address buffer 27 may take the form of a read-transparent latch to hold these address bits during the byte write cycle period of the data memory. will be. The latch function for the data memory column address will also be part of the column select circuit 37 after decoding. The other address buffers 25 and 29 may be in the form of latch circuits, or may be simple tri-state buffers that hold these address signals provided to the address input line Ai only while the address signals are held. In either case, all address buffers are enabled in response to control signals C ₁ -C ₃ from control logic circuit 21. As a result, the control logic circuit 21 receives signals received from the input pin of the memory device. , , , From the control signal Ck is derived. The row address buffer 25 is a chip enable signal or Either (but not all) is active (low), output enable signal, or write enable signal or Each time one of (but not all) is also active (low), it is enabled by signal C ₁ . The column address buffer 27 for the data memory 13 has an EEPROM chip enable signal. Is active and the output enable signal Or write enable signal Each time one of them is activated, it is enabled by signal C ₂ . The column address buffer 29 for the program memory 11 has a flash memory chip enable signal. Is active and the output enable signal Or write enable signal It is enabled by signal C ₃ each time one of them is activated. Address information is appropriate chip enable signal or And appropriate output enable signal Or write enable signal Either of which is input to the buffers 23, 27, 29 at the falling edge of the latter. The condition that the two chip enable signals are low or the two output and write enable signals are low is not valid, and no control signal is generated from the logic circuit 21. The row address buffer 25 is allocated to a series of address bits, for example, bits A4 to A14 corresponding to a sector of the flash memory array 11 of 512Kx8 bits and a page of the EEPROM array 13 of 32Kx8 bits. The column address buffers 27 and 29 are allocated to the remaining address bits, for example, bits A0 to A18 of the EEPROM array and to bits A0 to A3 and A15 to A18 of the flash array. Other arrangements of row and column address bits are possible, depending on the size and configuration of each memory array.

The address information is provided to the address decoding circuits 15, 31 and 33 by the buffers 25, 27 and 29. Typically, address decoding is performed in two or more steps, which include a first pre-decoding step and a final decoding step. For the sake of simplicity, all steps are collectively shown in FIG. 1, ie, with a corresponding single decoder circuit 15, 31 and 33. The shared row decoder 15 is connected to two memory arrays 11 and 13. In the case of the program memory 11, the row decoder 15 communicates directly with the row driver 32 that activates the selected word line or word line corresponding to the decoded row address bits. In the case of the data memory 13, the row decoder 15 is connected to a latch circuit 24 having read transparency. This latch circuit 24 is consequently connected to a row driver 34 that activates the selected word line corresponding to the decoded row address received from the row decoder. During the read operation, since the latch circuit 24 is efficient to have transparency, the row decoder 15 communicates directly with the selected row driver. However, during the write operation, the decoded address is latched in the row address latch 24 and spaced apart from the bypass gates of the row decoder 15 controlled by the control signal C ₇ from the control logic circuit 21 (this is = Low, Occurs when = low). This frees the row decoder 15 to decode the address to be read from the program memory 11. The latch circuit 24 holds the decoded row address for writing to the data memory 13 so that the selected word line continues to hold the programming voltage Vpp.

The column decoder 31 for the data memory 13 is connected to the column selector circuit 35. Similarly, the column decoder 33 for the program memory 11 is connected to the column selector circuit 37. The column select circuits 35 and 37 are multiplexed in both directions and are gating circuits that control access of the data path to selected columns of 8 bit lines of each of the memory arrays 11 and 13. The operation of the selection circuits 35, 37 is controlled by signals C ₄ and C ₅ from the control logic circuit 21. During a read operation ( = High, = Low), enabled memory array 11 or 13 ( or The selected column of bit lines corresponding to the column address of the row) is connected to the sense amplifier 17. The data input / output buffer 19 outputs the sensed data byte to the data line Dj in response to another control signal C ₆ . During the recording operation ( = Low, = High), enable column selection circuit (35 or 37) ( or Low) is connected to the data latches 23 and 39 for the selected column of the bit lines of the memory array 11 or 13 with the input / output buffer 19 enabled. Data received from the data line Dj is loaded into the selected data latch 23 or 39, from which the data can be loaded into rows and columns of memory corresponding to the received and decoded address bits Ai.

The control logic circuit 21 is input signal , , , In addition to generating the appropriate control signal Ck in response to this, the generation of the high voltage Vpp for programming data in the memory cell is controlled. In particular, the memory device may include JEDEC standard software data protection (WP). In this structure, each program sequence for a byte or page of a sector or EEPROM of flash memory must be progressed by a program sequence of 3 bytes to generate actual programming. This sequence may consist of a specific combination of alternating 0s and 1s, typically of data bits Dj and address bits Ai.

In Figs. 2A and 2B, the timing diagram shows the main operation features of the present invention. The write operation to program memory (i.e., flash memory array 11 of FIG. 1) starts with three bytes of write enable code to override software write protection. Chip Enable Signals for Flash Memory And record enable signal While is low, a sequence of three addresses and three corresponding data sets is input to the memory device. Typically, address bits A18-A15 are ignored because the write protection logic is shared by the smaller EEPROM array 13. If the actual write to the flash memory has not yet occurred, this sequence causes the control logic to begin allowing the generation of the program voltage Vpp and to start an internal write timer. Flash memory is programmed in 256 byte sectors. The entire sector is erased upon receipt of the sector address for bits A ₁₄ through A ₄ prior to the program. No specific erase command is needed. As a result, any byte in the sector not programmed on the left remains unchanged during the period of sector write, during which the byte addresses A ₁₈ to A ₁₅ and A ₃ to A ₀ in the sector change. It is common for the byte addresses to change sequentially, but this is not essential, and byte programming of the flash sector can proceed in any order. In Figs. 2A and 2B, byte addresses for sectors are executed sequentially from the start address ADDR to the end address ADDR + 255. The corresponding data DATA-IN loaded into the memory represents BYTE 0 to BYTE 255 in the data line.

Byte loading is Wow We make high about Wow Is performed by applying a low pulse. Whichever address is the last or Latches on the falling edge of, and the data or Is latched at the first rising edge of. Once the bytes are loaded into the data latch of the flash memory array, these data are programmed into the memory cell during the internal programming period. Typically the byte write cycle time is approximately 150 μm, but the actual loading may take less time. After the first data byte has been programmed, the bytes are entered in the same way consecutively. Each new byte to be programmed has its own signal (or ) Of the previous byte (or Must transition from high to low within 150 ms of transition from low to high or before the loading period ends. The total write cycle time for a sector of flash memory is typically about 10 ms. A read operation on the EEPROM array is not allowed during the write cycle of the flash memory, and the polling operation of the current byte loaded by attempting to read the flash memory will be efficient. A modification to the memory device of FIG. 1 that also includes decoded row address latch circuits for flash memory 11 and EEPROM 13 would allow the EEPROM to read during the write operation of the flash memory, if desired.

The flash memory read operation 52 is a chip enable signal of the flash memory. And output enable signals While the pulse goes low, Wow The pulse occurs when it is held high. The flash memory array 11 is read similarly to the static RAM. The read is performed for each individual byte, not the entire sector. In addition, for the read operation, the sectors do not show the boundary portion, and the sector boundary does not need to be considered. That is, bytes from different sectors can be read continuously. Wow When is low, the data DATA-OUT to be output is stored in the storage position of the flash memory determined by the address inputs A ₁₈ to A ₀ and provided to the data line. Maximum read time is typically 150 to 200 microseconds per byte.

The data memory 13, typically the EEPROM array, is written more frequently than the program memory 11. The write operation of the EEPROM in FIGS. 2A and 2B represents the capability provided by the read operation of the flash memory 11 with the memory structure occurring simultaneously during the write cycle period of the EEPROM array 13. Write protection is disabled by a 3 byte write enable code sequence. This code sequence is typically the same as the write enable code sequence in flash memory. While the pulse is low The difference is that the pulse is high. The read operation from the flash memory may stop loading of the write enable code sequence, as shown, if the byte loading cycle time of 150 ms is not violated. Since the read operation takes less than 200 ms to complete, many bytes are read from the flash memory between each byte of the code sequence. Once a valid instruction sequence is loaded, the write cycle Wow Is started by going low. The address is whatever or Is latched by the falling edge of, and the data is or The latch 23 of FIG. 1 is latched along the rising edge of.

All write operations to the EEPROM array must comply with page write restrictions. That is, from a single byte of data to 16 bytes of data can be written anywhere, all these bytes must be located on the same page as defined by address bits A14-A4 during the write cycle. signal For each transition from high to low, bits A14-A4 must be identical (pages of FIGS. 2A and 2B). The A3 to A0 address bits are used to specify the bytes in the page to be written. Address bits A18-A15 do not apply to smaller EERPOM arrays and will be ignored. For the full page write operation, the bytes are sequentially loaded by input data BYTE 0-BYTE 15 loaded into sequential bytes starting with the starting address ADDR and ending with the address ADDR + 15, as shown in FIGS. 2A and 2B. It is usually recorded as However, the bytes can be loaded in any order and can be changed within the same loading period if desired. Only the bytes specified for writing will be erased and written with new data held in the data latch.

Read 56 from the flash memory array is allowed through the EEPROM write cycle time (up to 10 ms) as long as the 150 ms byte loading cycle time for EEPROM writes is not violated. As before, reading from flash memory Wow Occurs when the pulse goes low. The data BYTE stored in the flash memory location F.ADDR determined by the address inputs A18 to A0 will be sensed and output to the data line. Attempt to read the EEPROM array during the EEPROM write cycle ( Wow Low) will cause a polling operation of the data held in the latch 23.

EEPROM read operation 58 is selected by the EEPROM array. Is exactly the same as the flash read operation 52 except that is low. The data BYTE stored in the memory location EEADDR determined by the address input A14-A0 will be sensed and output to the data line. EEPROM reads are not performed during any write cycle period.

The memory device of the present invention has been provided for storing infrequently updated program information in one memory array and frequently updated data parameters in another memory array. The configuration of the present invention allows simultaneous read operation of the program memory during the write operation to the data memory, and eliminates many duplications in address and data hardware. The address latch of the data memory frees the row decoder for the program memory during the time period when the data held in the data latch of the data memory is actually programmed into the memory cell. Therefore, only one row decoder is needed. Since the memory device may have independent address latches and drivers in both memory arrays, the read operation may be performed in the other memory array while the write operation is completed in one memory array. Reading and writing two memory arrays requires only a single set of data and address inputs.

Claims (16)

A first nonvolatile memory array; A second nonvolatile memory array; A single set of address lines at least partially common to the first and second memory arrays; Is connected to the address line to receive an address signal from the address line to access a memory location of one of the memory arrays selected from the first and second memory arrays, the address signal being common to the first and second memory arrays; Address decoding and selecting means having a shared row decoder for access on a word line of the selected memory array corresponding to; An address latch means for inputting and outputting said address decoding means in association with said first memory array, said address latch means holding said decoded address during a write operation to said first memory array, said address decoding and selecting means being said second memory; Free access to different memory locations for simultaneous read operations from the array; A single set of data lines common to the first and second memory arrays; Input / output with a selected bit line common to the first and second memory arrays and corresponding to the addressed position of the selected memory array by the address decoding and selection means, the data line for a read operation from the selected memory array A single set of sense amplifiers connecting the selected bit lines to; Connectable to said single set of data lines and bit lines of each of said first and second memory arrays by said address decoding and selecting means, and retaining data received from said data lines during a write operation to said selected memory array. First and second data latching means; And in response to an input control signal, control means for selecting one of the first and second memory arrays and for selecting a read or write operation for the selected memory array. . The nonvolatile memory device of claim 1, wherein the first memory array is an EEPROM array. The method of claim 1, And the second memory array is a flash memory array. A nonvolatile memory device according to claim 1, wherein said address decoding and selection means comprises a separate column decoder and a separate column selection circuit for each memory array. The method of claim 1, wherein the address latch means for the first memory array is efficiently transparent during a read operation of the first memory array, and decoding and selecting the address until the write operation to the first memory array is completed. And separating said retained decoding address from said means. 2. The non- volatile memory device of claim 1, further comprising second address latching means for retaining a decoded address during a write operation to the second memory array in association with the second memory array. The memory array of claim 1, wherein the first and second memory arrays have different sizes, and the memory array having the larger size of the first and second memory arrays has both of the address lines for access to its selected location. And a memory array having a smaller size among the first and second memory arrays requires only a subset of the address lines for access to its selected location. 2. The apparatus of claim 1, wherein the input control signal comprises a first set of signals for selecting only one memory array of the first and second memory arrays and only one memory array of the first and second memory arrays. And a second set of signals enabling only one of the read and write operations, and only one of the read and write operations. A first nonvolatile memory array; A second nonvolatile memory array; An address line set for receiving a signal indicating address bits for designating specific positions in said first and second memory arrays, said set of address lines having row address lines and column address lines at least partially common to both said first and second memories; First and second column decoding and selection circuits for inputting and receiving signals from the column address lines and receiving address bits from the column address lines, wherein the first column decoding and selection circuits comprise the address bits in the first memory array. Access the selected bit line corresponding to the second column decoding and selection circuit to access the selected bit line corresponding to the address bit in the second memory array; A shared row decoder for inputting and outputting signals to and from the row address line to receive address bits from the row address line, and accessing a selected word line corresponding to the address bits in a selected memory array of the first and second memory arrays; ; A word line selection is continued for a period of a write operation to the first memory array by inputting and outputting a signal to and from the shared row decoder associated with the first memory array, and the second memory during a write operation to the first memory array A row address latch circuit for free access to other word lines for simultaneous read operations from the array; A set of data lines common to both the first and second memory arrays; A write operation for a selected memory array of the first and second memory arrays for the respective memory arrays and associated with the bit lines of the memory array and through the first and second column decoding and selection circuits, respectively A data latch set connectable to the data line for connection; Common to both the first and second memory arrays, and capable of input and output for bit lines in a selected memory array through the first and second column decoding and selection circuits, and for read operations from the selected memory array, the output being A sense amplifier set connected to said set of data lines; And control means for controlling an operation of at least said first and second column decoding and selection circuits and said row address latch circuit in response to an input control signal to perform a selected read or write operation on a selected memory array. Nonvolatile memory device. The nonvolatile memory device of claim 9, wherein the first data memory array is an EEPROM array. 12. The nonvolatile memory device of claim 10 wherein the EEPROM array has both single byte and page mode write capabilities. The nonvolatile memory device of claim 9, wherein the second memory array is a flash memory array. 10. The apparatus of claim 9, wherein the second memory array has a larger memory capacity than the first memory array, the second memory array requires both address lines for access to the first memory array, and the first memory And the array requires fewer address lines than all address lines to access it. 10. The circuit of claim 9, wherein the first and second column decoding and selection circuits connect the bit lines to data latches that have bit lines selected for a read operation connected to the sense amplifier and corresponding to bit lines selected for a write operation. And a bidirectional gating circuit. 10. The nonvolatile memory device of claim 9, wherein the row address latch circuit is transparent to the shared row decoder and word line during a read operation to the first memory array. 10. The apparatus of claim 9, wherein the input control signal comprises a first set of signals to select one memory array of the first and second memory arrays and only one memory array; And decode set signals for selecting only one of the write operations and only one of the read and write operations.