KR20000015090A - Method for automatically checking global bus in switching system - Google Patents

Abstract

PURPOSE: A method capable of checking a global bus by a person not having a special knowledge with respect to a switching system by automatically checking the global bus by a software is provided. CONSTITUTION: A method for automatically checking a global bus in a switching system, the method comprising the steps of: i) judging whether a main upper processor is executed; ii) judging whether a buffer of the main upper process is opened when the main upper processor is executed; iii) judging whether a first bus is executed when the buffer of the main upper process is opened; iv) testing the first bus for a predetermined time when the first bus is executed and outputting the testing result; v) judging whether a main upper processor is executed; vi) judging whether a buffer of the main upper process is opened when the main upper processor is executed in step v); vii) judging whether a first bus is executed when the buffer of the main upper process is opened in step vi); viii) testing the second bus for a predetermined time when the first bus is executed in step vii) and outputting the testing result; ix) judging whether a sub upper processor is executed; x) judging whether a buffer of the sub upper process is opened when the main upper processor is executed; xi) judging whether a third bus is executed when the buffer of the sub upper process is opened; xii) testing the third bus for a predetermined time when the third bus is executed and outputting the testing result; xiii) judging whether a sub upper processor is executed; xiv) judging whether a buffer of the sub upper process is opened when the sub upper processor is executed in step xiii); xv) judging whether a fourth bus is executed when the buffer of the main upper process is opened in step xiv); and xvi) testing the fourth bus for a predetermined time when the fourth bus is executed in step xv) and outputting the testing result.

Description

Global bus automatic inspection method in exchange

The present invention relates to a method for checking a channel in an exchange, and more particularly, to a method for automatically checking a global bus in an exchange for automatically checking a global bus that is a matching structure between an upper processor and a lower processor.

In general, the exchange is a subsystem that is in charge of the maintenance and repair of the system, and can be expanded when the subscriber is added to the CENTRAL CONTROL SUBSYSTEM (mainly composed of higher processors) and a matching block with actual subscribers. ASS (ACCESS SWITCHING SUBSYSTEM) composed of sub-processors and devices for controlling the processor and DEVICE, and serves to interface the CCS and ASS, and an upper processor for providing signaling channel and voice channel. It consists of INS (INTERCONNECTION NETWORK SUBSYSTEM) which is composed of subprocessors.

In addition, the matching structure of the upper processors and the lower processor is a dual global bus, and the conventional checking method for checking the global bus is an address or data size for each of the upper and lower processors. This was done using a command with an option.

However, since the conventional global bus inspection method as described above requires knowledge of the entire components of the exchange, it is difficult for the non-expert who does not have the knowledge, and there is a problem that only the system in operation can be inspected.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to implement a global bus check by software to automate and to be able to check the person without expertise in the exchange, and the system in operation Of course, the present invention provides a method for automatically checking a global bus in an exchange that enables inspection of a standby system.

In order to achieve the above object, the global bus automatic checking method in the exchange according to the present invention includes first, second, third and fourth bus paths to match the main and floating processors of the exchange and a plurality of sub-processors. A method for checking a global bus having a dual structure, comprising: a first step of determining whether the main processor is running, and if the main processor is executed in the first step, the buffer of the main processor is opened And a third step of determining whether or not to determine whether or not the first bus is executed when the buffer of the main upper processor is opened in the second step. A fourth step of testing the first bus for a predetermined time and outputting a result when the first bus is executed in the step; and determining whether the main upper processor is executed. In a fifth step, if the main upper processor is executed in the fifth step, a sixth step of determining whether the buffer of the main upper processor is opened, and if the buffer of the main upper processor is opened in the sixth step, A seventh step of determining whether the second bus is executed; an eighth step of testing the second bus for a predetermined time and outputting a result if the second bus is executed in the seventh step; and the injury A ninth step of determining whether or not the above processor is executed; a tenth step of determining whether a buffer of the injured processor is opened when the floating processor is executed in the ninth step; and the tenth step In step 11, if the buffer of the floating processor is opened, determining whether or not the third bus is executed, and if the third bus is executed in the eleventh step, the A twelfth step of testing a third bus and outputting a result, a thirteenth step of determining whether the subordinate processor is executed, and a floating point processor when the floating point processor is executed in the thirteenth step, Determining whether or not the buffer of the processor is open; if the buffer of the floating processor is opened in step 14, determining whether the fourth bus is executed; When the fourth bus is executed in, it is characterized in that it comprises a sixteenth step of testing the fourth bus for a predetermined time and outputs the result.

1 is a view showing an example of the global bus path in the exchange to be applied to the present invention,

2 is a view showing a path for inspecting a first bus by a global bus automatic checking method in an exchange according to an embodiment of the present invention;

3 is a view showing a path for checking a second bus by a global bus automatic checking method in an exchange according to an embodiment of the present invention;

4 is a view showing a path for inspecting a third bus by a global bus automatic checking method in an exchange according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a path for inspecting a fourth bus by a global bus automatic checking method in an exchange according to an embodiment of the present invention; FIG.

6A to 6D are flowcharts illustrating a method for automatically checking a global bus in an exchange according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: major processor 110: floating processor

200: first subprocessor 210: second subprocessor

220: third subprocessor 230: fourth subprocessor

240: fifth subprocessor 250: sixth subprocessor

Hereinafter, a method for automatically checking a global bus in an exchange according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a global bus path in an exchange according to the present invention, in which a global bus is a path for matching an upper processor and a lower processor and has a dual structure. A processor that outputs a command, which is divided into a main upper processor 100 used as a main and a floating level processor 110 used as an auxiliary, wherein the lower processor controls various devices according to a control command of the upper processor. As a processor, it is possible to increase the number of devices as the number of devices increases. In FIG. 1, six subprocessors, that is, the first, second, third, fourth, fifth, and sixth subprocessors 200, 210, 220, 230, 240, and 250 are illustrated.

FIG. 2 is a view showing a route for checking a first bus by a method for automatically checking a global bus in an exchange according to an embodiment of the present invention, and FIG. 3 is a diagram showing a global bus in an exchange according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a route for checking a second bus by an automatic inspection method, and FIG. 4 is a diagram illustrating a route for checking a third bus by a global bus automatic inspection method in an exchange according to an embodiment of the present invention. 5 is a diagram illustrating a path for inspecting a fourth bus by a global bus automatic checking method in an exchange according to an embodiment of the present invention.

The paths to be checked by the automatic check method of the global bus according to the present invention are the paths of the first bus to the fourth bus as shown in FIGS. 2 to 5, and the checked order is first, second, third and fourth. Bus order.

Next, a method for automatically checking a global bus in an exchange according to an embodiment of the present invention will be described with reference to the accompanying drawings.

6A to 6D are operational flowcharts illustrating a method for automatically checking a global bus in an exchange according to an embodiment of the present invention, where S represents a step.

The global bus automatic checking method according to the present invention comprises a step of checking the first bus, the second bus, the third bus and the fourth bus of FIGS. 2 to 5, wherein the software for automatic checking is interfaced with an exchange. It may be stored in the user environment or in memory within the host processor.

First, it is determined whether the main upper processor 100 is executed (S1), and if the main upper processor 100 is executed (YES), it is determined whether the buffer in the main upper processor 100 is opened. (S2).

In step S2, if the buffer of the main upper processor 100 is opened (YES), it is determined whether the first bus is executed (S3), and if the first bus is executed (YES). , Test the first bus for a predetermined time (S4), and outputs the test results of the first bus through any output means (S5).

Subsequently, it is determined whether the main upper processor 100 is executed (S6). If the main upper processor 100 is executed (YES), it is determined whether the buffer of the main upper processor 100 is opened. It is determined (S7).

In step S7, when the buffer of the main upper processor 100 is opened (YES), it is determined whether the second bus is executed (S8), and if the second bus is executed (YES), for a predetermined time. While testing the second bus (S9), and outputs the test results of the second bus through any output means (S10).

Subsequently, it is determined whether the floating processor 110 is executed (S11), and when the floating processor 110 is executed (YES), it is determined whether the buffer of the floating processor 110 is opened ( S12).

In step S12, if the buffer of the floating processor 110 is opened (YES), it is determined whether or not the third bus is executed (S13), and if the third bus is executed (YES) The third bus is tested for a predetermined time (S14), and the test result of the third bus is output through an arbitrary output means (S15).

Next, it is determined whether the floating processor 110 is executed (S16), and if the floating processor 110 is executed (YES), it is determined whether the buffer of the floating processor 110 is opened. (S17).

If the buffer of the floating processor 110 is opened (YES) in step S17, it is determined whether the fourth bus is executed (S18), and if the fourth bus is executed (YES). , The fourth bus is tested for a predetermined time (S19), the test result of the fourth bus is output through an arbitrary output means (S20), and all the operations are terminated.

On the other hand, if the main processor 100 is not executed in step S1 (NO), the control command for executing the main processor 100 is output (S21), the main processor 100 is executed. It is determined whether or not (S22).

In step S22, if the main upper processor 100 is executed (YES), the process proceeds to the step S2, whereas if the main upper processor 100 is not executed (NO), correspondingly The abnormal message is output through an arbitrary output means (S23), and the flow proceeds to the step S4.

On the other hand, if the buffer of the main upper processor 100 is not opened in step S2 (NO), a control command for opening the buffer of the main upper processor 100 is output (S24), and the main upper processor ( It is determined whether or not the buffer of 100) is opened (S25).

When the buffer of the main upper processor 100 is opened (YES) in step S25, the process proceeds to the step S3, while the buffer of the main upper processor 100 is opened in the step S25. If not (NO), the corresponding abnormal message is output through any output means (S23), and the flow proceeds to the step S4.

On the other hand, if the first bus is not executed in step S3 (NO), a control command for executing the first bus is output (S26), and it is determined whether or not the first bus is executed (S27).

In step S27, if the first bus is executed (YES), the process proceeds to step S4, whereas if the first bus is not executed in the step S27 (NO), the corresponding The abnormal message is output through an arbitrary output means (S23), and the flow proceeds to the step S4.

On the other hand, if the main processor 100 is not executed in step S6 (NO), and outputs a control command for executing the main processor 100 (S28), the main processor 100 is executed It is determined whether or not (S29).

In step S29, if the main upper processor 100 is executed (YES), the process proceeds to the step S7, whereas if the main upper processor 100 is not executed (NO), correspondingly The abnormal message is output through an arbitrary output means (S30), and the flow proceeds to the step S9.

On the other hand, if the buffer of the main upper processor 100 is not opened in step S7 (NO), a control command for opening the buffer of the main upper processor 100 is output (S31), and the main upper processor ( It is determined whether or not the buffer of 100) is opened (S32).

When the buffer of the main upper processor 100 is opened (YES) in step S32, the process proceeds to the step S8, while the buffer of the main upper processor 100 is opened in the step S32. If not (NO), the corresponding abnormal message is output through any output means (S30), and the flow proceeds to the step S9.

On the other hand, if the second bus is not executed in step S8 (NO), a control command for executing the second bus is output (S33), and it is determined whether or not the second bus is executed (S34).

In step S34, if the second bus is executed (YES), the process proceeds to step S9, whereas if the second bus is not executed in the step S34 (NO), the corresponding The abnormal message is output through an arbitrary output means (S30), and the flow proceeds to the step S9.

On the other hand, if the floating processor 110 is not executed in step S11 (NO), and outputs a control command for executing the floating processor 110 (S35), the floating processor 110 is executed It is determined whether or not (S36).

In step S36, if the floating processor 110 is executed (YES), the process proceeds to the step S12, whereas if the floating processor 110 is not executed (NO), The abnormal message is output through an arbitrary output means (S37), and the flow proceeds to the step S14.

On the other hand, if the buffer of the floating processor 110 is not opened in step S12 (NO), and outputs a control command for opening the buffer of the floating processor 110 (S38), the floating processor ( It is determined whether or not the buffer of 110 is opened (S39).

If the buffer of the floating processor 110 is opened at the step S39 (YES), the process proceeds to the step S13, while the buffer of the floating processor 110 is opened at the step S39. If not (NO), the corresponding abnormal message is output through any output means (S37), and the flow proceeds to the step S14.

On the other hand, if the third bus is not executed in step S13 (NO), a control command for executing the third bus is output (S40), and it is determined whether or not the third bus is executed (S41).

In step S41, if the third bus is executed (YES), the process proceeds to step S14, whereas if the third bus is not executed in the step S41 (NO), the corresponding The abnormal message is output through an arbitrary output means (S37), and the flow proceeds to the step S14.

On the other hand, if the floating processor 110 is not executed in the step (S16) (NO), and outputs a control command for executing the floating processor 110 (S42), the floating processor 110 is executed It is determined whether or not (S43).

In step S43, if the floating processor 110 is executed (YES), the process proceeds to the step S17, whereas if the floating processor 110 is not executed (NO), The abnormal message is output through an arbitrary output means (S44), and the flow proceeds to the step S19.

On the other hand, if the buffer of the floating processor 110 is not opened in step S17 (NO), and outputs a control command for opening the buffer of the floating processor 110 (S45), the floating processor ( It is determined whether the buffer of 110 is opened (S46).

If the buffer of the floating processor 110 is opened at the step S46 (YES), the process proceeds to the step S18, while the buffer of the floating processor 110 is opened at the step S46. If not (NO), the corresponding abnormal message is output through any output means (S44), and the flow proceeds to step S19.

On the other hand, if the fourth bus is not executed in step S18 (NO), a control command for executing the fourth bus is output (S47), and it is determined whether or not the fourth bus is executed (S48).

In step S48, if the fourth bus is executed (YES), the process proceeds to step S19, whereas if the fourth bus is not executed in the step S48 (NO), the corresponding The abnormal message is output through any output means (S44), and the flow proceeds to the step S19.

Meanwhile, in the embodiment of the present invention, the number of the lower processors is 6 as an example. However, the number of the lower processors can be changed as many as the driving apparatus. Also, the upper processors are divided into main and minor examples. However, expansion is possible, and thus the global bus check software algorithm of the exchange can be easily solved if an addition of check steps corresponding to the additional path by the extended host processor is made.

As described above, according to the global bus automatic checking method of an exchange according to the present invention, the automatic checking method software is stored in a computer main body of a user interfaced with an upper processor of the exchange for checking the global bus in the exchange, or a higher level in the exchange. By storing and executing the above software in the memory of the processor, it is possible not only to check the entire path of the global bus but also to check the operation status of the various processors connected to the path. have.

Another effect is that you can check both the live and standby systems.

Claims (13)

In a method for checking a dual, global bus with a first, second, third, and fourth bus paths formed to mate a main, floating processor of a switch and a plurality of subprocessors, A first step of determining whether the main upper processor is executed; A second step of determining whether a buffer of the main upper processor is opened when the main upper processor is executed in the first step; A third step of determining whether the first bus is executed when the buffer of the main upper processor is opened in the second step; A fourth step of testing the first bus for a predetermined time and outputting a result when the first bus is executed in the third step; A fifth step of determining whether the main upper processor is executed; A sixth step of determining whether a buffer of the main upper processor is opened when the main upper processor is executed in the fifth step; A seventh step of determining whether the second bus is executed when the buffer of the main upper processor is opened in the sixth step; An eighth step of testing the second bus for a predetermined time and outputting a result when the second bus is executed in the seventh step; A ninth step of determining whether or not the floating level processor is executed; A tenth step of determining whether a buffer of the floating processor is opened when the floating processor is executed in the ninth step; An eleventh step of determining whether the third bus is executed when the buffer of the floating processor is opened in the tenth step; A twelfth step of testing the third bus for a predetermined time and outputting a result when the third bus is executed in the eleventh step; A thirteenth step of determining whether the secondary higher processor is executed; When the floating processor is executed in the thirteenth step, determining whether the buffer of the floating processor is opened; A fifteenth step of determining whether the fourth bus is executed when the buffer of the floating processor is opened in the fourteenth step; And a sixteenth step of testing the fourth bus for a predetermined time and outputting a result when the fourth bus is executed in the fifteenth step. The method of claim 1, If the main processor is not executed in the first step, outputting a command for executing the main processor and determining whether the main processor is running; If the main process is performed in the 17th step, the process proceeds to the second step. On the other hand, if the main process is not executed in the 17th step, an abnormal message corresponding thereto is outputted, and the process proceeds to the fourth step. The 18th step is further configured, the global bus automatic check method of the exchange. The method of claim 1, A 19th step of outputting a command to open a buffer of the main upper processor if the buffer of the main upper processor is not opened in the second step, and determining whether the buffer of the main upper processor is opened; If the buffer of the main upper processor is opened in step 19, the process proceeds to the third step. On the other hand, if the buffer of the main upper processor is not opened in step 19, a corresponding abnormal message is output. A global bus automatic checking method of an exchange, characterized in that the 20th step proceeds to the fourth step. The method of claim 1, If the first bus is not executed in the third step, outputting a command to execute the first bus and determining whether or not the first bus is executed; If the first bus is executed in the twenty-first step, the process proceeds to the fourth step. On the other hand, if the first bus is not executed, an abnormal message corresponding to the first bus is output and the fourth process proceeds to the fourth step. A global bus automatic check method of an exchange, characterized in that 22 steps are additionally configured. The method of claim 1, If the main processor is not executed in the fifth step, outputting a command for executing the main processor, and determining whether or not the main processor is running; If the host process is performed in the twenty-third step, the process proceeds to the sixth step. On the other hand, if the host processor is not executed in the twenty-third step, a corresponding abnormal message is output, and the eighth step is performed. A global bus automatic check method of an exchange characterized in that the twenty-fourth step is further configured. The method of claim 1, If the buffer of the main upper processor is not opened in the sixth step, outputting a command to open the buffer of the main upper processor, and determining whether the buffer of the main upper processor is opened; When the buffer of the main upper processor is opened in step 25, the process proceeds to the seventh step. On the other hand, when the buffer of the main upper processor does not open in step 25, an abnormal message corresponding to the main processor is output. And a twenty sixth step proceeding to the eighth step is further configured. The method of claim 1, If the second bus is not executed in the seventh step, outputting a command for executing the second bus and determining whether the second bus is executed; If the second bus is executed in the twenty-seventh step, the process proceeds to the eighth step. On the other hand, if the second bus is not executed, an abnormal message corresponding to the second bus is outputted. Global bus automatic check method of the exchange, characterized in that 28 additional steps. The method of claim 1, If the floating processor is not executed in the ninth step, outputting a command to execute the floating processor and determining whether the floating processor is executed; If the floating level process is executed in the 29th step, the process proceeds to the tenth step. On the other hand, if the floating level processor is not executed in the 29th step, an abnormal message corresponding to the floating level processor is outputted. The global bus automatic check method of the exchange, characterized in that the thirtieth step is further configured. The method of claim 1, If the buffer of the floating processor is not opened in the tenth step, outputting a command to open the buffer of the floating processor, and determining whether or not the buffer of the floating processor is opened; If the buffer of the floating processor is opened in the thirty-first step, the process proceeds to the eleventh step. On the other hand, if the buffer of the floating processor is not opened in the thirty-first step, a corresponding abnormal message is outputted. And a thirty-second step that proceeds to the twelfth step is further configured. The method of claim 1, A third step of outputting a command for executing the third bus if the third bus is not executed in the eleventh step, and determining whether the third bus is executed; If the third bus is executed in the thirty-third step, the process proceeds to the twelfth stage. On the other hand, if the third bus is not executed, an abnormal message corresponding to the third bus is outputted. A global bus auto-check method of an exchange comprising 34 additional steps. The method of claim 1, If the floating processor is not executed in the thirteenth step, outputting a command to execute the floating processor, and determining whether the floating processor is executed; If the floating level process is executed in the 35th step, the process proceeds to the 14th step. On the other hand, if the floating level processor is not executed in the 35th step, an abnormal message corresponding to the floating level processor is outputted. And wherein the 36th step is further configured. The method of claim 1, If the buffer of the floating processor is not opened in step 14, outputting a command to open the buffer of the floating processor and determining whether the buffer of the floating processor is opened; If the buffer of the floating processor is open in step 37, the process proceeds to the fifteenth step. On the other hand, if the buffer of the floating processor is not opened in step 37, the corresponding abnormal message is outputted. 38. The method according to claim 16, wherein the 38th step proceeds to the 16th step. The method of claim 1, If the fourth bus is not executed in the fifteenth step, outputting a command for executing the fourth bus and determining whether or not the fourth bus is executed; If the fourth bus is executed in step 39, the process proceeds to the sixteenth step. On the other hand, if the fourth bus is not executed, an abnormal message corresponding to the fourth bus is output and the process proceeds to the sixteenth step. Global bus automatic check method of the exchange, characterized in that 40 additional steps.