KR20000014673A - Demultiplexer and liquid crystal panel using the demultiplexer - Google Patents

Abstract

PURPOSE: A demultiplexer and liquid crystal panel using the demultiplexer is provided, which simplifies a control wire and prevents a noise component signal. CONSTITUTION: The demultiplexer comprises: switching devices (MN1-MN3) to be commonly connected to input lines and output lines, for responding to selecting signals of control lines and outputting a signal of input line to the output line; control bypass means (AMN1-AMN3) to be connected between switching devices (MN1-MN3) and output lines, for responding to a redundancy selecting signal of a redundancy line and bypassing a noise component signal inputted from switching devices (MN1-MN3) to the output line, including a field effect transistor. Thereby, it is possible to simplifies the control wire.

Description

Demultiplexer and Liquid Crystal Panel using the Same

The present invention relates to a demultiplexer for demultiplexing signals from an input line toward a plurality of output lines, and more particularly to a demultiplexer with simplified control wiring. The present invention also relates to a liquid crystal panel in which signal input wiring is simplified by a demultiplexer. Furthermore, the present invention relates to a liquid crystal display device in which the configuration of the driving circuit of the liquid crystal panel by the demultiplexer and the signal wiring between the liquid crystal panel and the driving circuit are simplified.

A liquid crystal display (hereinafter referred to as "LCD") displays an image corresponding to the video signal by adjusting the light transmittance of the liquid crystal according to the video signal. Such LCDs include a liquid crystal panel in which liquid crystal cells are arranged in an active matrix form, and driving circuits for driving the liquid crystal panel. Furthermore, the LCD includes demultiplexers for simplifying the structure of the driving circuit and the signal input wiring of the liquid crystal panel. Each of these demultiplexers simplifies the configuration of the signal input wiring and the driving circuit of the liquid crystal panel by demultiplexing the data signal from the driving circuit toward the signal input lines on at least two liquid crystal panels.

LCD including such demultiplexers includes n demultiplexers DMUX1 to DMUXn connected between the data lines DL1 to DL3n and the data driving circuit 12 on the liquid crystal panel 10, as shown in FIG. The scan driver circuit 14 sequentially drives the m gate lines GL1 to GLm on the liquid crystal panel 10 in the horizontal scanning period. Each of the n demultiplexers DMUX1 to DMUXn receives three data lines DL3i-2 and DL3i-1 from the data driver circuit 12 via the signal lines SL1 to SLn at horizontal synchronization periods. , Demultiplexing to DL3i). To this end, each of the demultiplexers DMUX1 to DMUXn includes first to third thin film transistors (TNs) MN1 to MN3 commonly connected to the signal lines SL1 to SLn. It will be included. These first to third TFTs MN1 to MN3 are sequentially turned on one by one while the gate pulse GPS as shown in FIG. 2 is supplied to any one of the m gate lines GL1 to GLm. Turn-on). In detail, the first TFT MN1 moves from the signal lines SL1, SL2,..., SLn by the first selection clock MCLK1 as shown in FIG. 2 toward the gate terminal thereof from the first control line CL1. Is transmitted to the 3i-2th data lines DL1, DL4, ..., DL3n-2. The second TFT MN2 also transfers the data signals from the signal lines SL1, SL2, ..., SLn from the second control line CL2 to its gate terminal by the second selection clock MCLK2 as shown in FIG. The data is transferred to the 3i-1th data lines DL2, DL5, ..., DL3n-1. The third TFT MN3 receives the data signal from the signal lines SL1, SL2, ..., SLn from the third control line CL3 to its gate terminal by the third select clock MCLK3 as shown in FIG. The data is transferred to the 3i th data lines DL3, DL6, ..., DL3n. Each of the first to third TFTs MN1 to MN3 operating in this manner has charges charged in its own channel when turned off and the signal line SL and data as in the equivalent circuit of FIG. 3. The discharge is divided into two parts of the line DL. Thus, the amount of charge supplied to the data line DL depends on whether the TFT MN is turned on or turned off. In detail, when the TFT (MN) is turned on, the amount of charge Qon supplied to the data line DL is represented by Equation 1, whereas when the TFT (MN) is turned off, Equation 2 and Become together.

Qon = CdataVdata

In Equations 1 and 2, Rdata is the resistance value of the data line DL, Cdata is the capacitance value of the liquid crystal cell, Cmn is the capacitance value of the channel in the TFT, Vdata is the voltage of the data signal, and Vmclk is the selection signal. The voltage and Vth represent the threshold voltages of the TFTs, respectively. As such, since the charge is supplied to the data line DL when the TFT is turned on, the voltage on the data line DL is changed. As such, the voltage variation in the data line DL is commonly referred to as a " feed throw voltage ΔVp "

The feed throw voltage ΔVp is different in each of the data lines DL as the threshold voltage Vth of the TFTs is changed. In addition, the feed throw voltage ΔVp is differently displayed on each of the data lines DL depending on the voltage difference between the data signals supplied to the adjacent data lines DL. As the feed through voltage ΔVp is changed according to the data lines, the light transmittance of the liquid crystal cells on one line becomes uneven, and further, the image displayed on the liquid crystal panel 10 is distorted and / or degraded.

An LCD as shown in FIG. 4 is disclosed as a method for suppressing deterioration of image quality due to such a change in the feed trough voltage ΔVp. The LCD of FIG. 4 has a circuit configuration similar to that of the LCD of FIG. 1, but the first to third demultiplexers DMUX1 to DMUXn are connected in series between the first to third TFTs MN1 to MN3 and the data line DL, respectively. The difference is that the third auxiliary TFTs ANN1 to ANN3 are additionally provided. Each of the first to third auxiliary TFTs ANN1 to ANN3 forms an auxiliary capacitor for bypassing a noise signal on the data line DL. Each of the first to third auxiliary TFTs AMN1 to ANN3 is respectively applied to the same first to third selection signals MCLK1 to MCLK3 in FIG. 5 supplied from each of the first to third control lines CL1 to CL3. The first to third TFTs MN1 to MN3 respond to each other. In detail, the first auxiliary TFT ANN1 in response to the first inversion selection signal / MCLK1 as in the fifth from the fourth control line CL4 is turned off when the first TFT MN1 is turned off. The charge flowing into the data lines DN1, DN4, ..., DN3n-2 from the first TFT MN1 is absorbed. Similarly, the second auxiliary TFT AMN2 responsive to the second inversion selection signal / MCLK2 as in the fifth from the fifth control line CL5 is turned on when the second TFT MN2 is turned off. The charges flowing from the TFT MN1 toward the data lines DN2, DN5, ..., DN3n-1 are absorbed. Similarly, the third auxiliary TFT ANN3 in response to the third inversion selection signal / MCLK3 as in the fifth from the sixth control line CL6 is turned off when the third TFT MN3 is turned off. The charges flowing from the TFT MN3 toward the data lines DN3, DN6, ..., DN3n are absorbed. Accordingly, when the TFTs MN are turned off, the same amount of charge Qoff in Equation 2 supplied to the data line DL supplied from the TFTs MN is the same as in the equivalent circuit of FIG. 6. Bypass through (AMN). As a result, the voltage on the data line DL does not change even when the TFTs MN enter the turn-off state from the turned-on state. In addition, the voltage on the data line DL is a voltage on the data line DL because the TFT MN and the auxiliary TFT AMN are arranged adjacently even though the threshold voltage Vth of the TFTs and the auxiliary TFTs is different. Almost unchanged. The auxiliary TFT (AMN) has a capacitance value corresponding to 1/2 of the capacitance value of the channel of the TFT (MN) in order to sufficiently absorb the amount of charge from the TFT (MN) when the TFT (MN) is turned off. Is formed. In other words, the channel width of the auxiliary TFT (AMN) is half the channel width of the TFT (MN). As described above, in the LCD of FIG. 4, the bypass auxiliary TFT ANN is added to the demultiplexers DMUX1 to DMUXn so that the feed through voltage ΔVp is not generated in the data line DL. Accordingly, the light transmittance of the liquid crystal cells on the liquid crystal panel 10 becomes uniform, and further, the image displayed on the liquid crystal panel 10 is not distorted and / or degraded.

However, in the LCD as shown in FIG. 4, the number of control lines is doubled to drive the demultiplexers DMUX1 to DMUXn, and the intersection points between the control lines and the branch lines from the control lines are quadrupled. As a result, the defect rate of the liquid crystal panel in which the demultiplexers are integrally manufactured is increased, and the manufacturing yield of the liquid crystal panel is lowered. In addition, complicated control wiring for demultiplexers will reduce the manufacturing yield of LCDs.

It is therefore an object of the present invention to provide a demultiplexer suitable for simplifying control wiring.

Another object of the present invention is to provide a demultiplexer integrated liquid crystal panel suitable for simplifying control wiring.

It is still another object of the present invention to provide a demultiplexer integrated LCD suitable for simplifying control wiring.

1 is a view schematically showing a conventional liquid crystal display device.

FIG. 2 is a waveform diagram of signals supplied to the demultiplexers shown in FIG. 1. FIG.

FIG. 3 shows an electrical equivalent circuit of the data line shown in FIG. 1. FIG.

4 is a view schematically showing a conventional liquid crystal display device.

5 is a waveform diagram of signals supplied to the demultiplexers shown in FIG.

FIG. 6 shows an electrical equivalent circuit of the data line shown in FIG. 4. FIG.

4 is an enlarged view of FIG. 3.

5 is a view showing a mold for producing partition walls.

6 is a diagram showing the structure of a plasma display panel element according to a first embodiment of the present invention;

7 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a waveform diagram of signals supplied to the demultiplexers shown in FIG.

FIG. 9 shows an electrical equivalent circuit of the data line shown in FIG. 7. FIG.

FIG. 10 is a schematic view of a liquid crystal display according to another exemplary embodiment of the present invention. FIG.

In order to achieve the above object, the demultiplexer according to the present invention is commonly connected to an input line and is connected to at least two output lines, respectively, so that a signal from an input line is output in response to a selection signal from at least two control lines. At least two switching elements for outputting to any one of them, at least two switching elements and at least two output lines, respectively, connected to the output line from the switching element in response to a redundant selection signal from the redundant control line. At least two or more control bypass means for bypassing the noise component signal to be made.

A demultiplexer integrated liquid crystal panel according to the present invention includes a pixel matrix arranged at each of intersection points of at least two or more data lines and at least two gate lines, and for inputting two or more data signals to be supplied to at least two or more data lines. A signal line and a signal line, which are commonly connected to the signal line and are connected to at least two data lines, respectively, to output data signals from the signal lines to one of the data lines in response to a selection signal from at least two control lines. Bypasses a noise component signal, which is connected between at least two switching elements, at least two switching elements, and at least two data lines, respectively, and which is to flow from the switching element toward the data line in response to a redundant selection signal from the redundant control line. Write down 2 is provided with control over the bypass means.

A demultiplexer integrated liquid crystal display according to the present invention includes a liquid crystal panel having a pixel matrix arranged at each of intersections of at least two data lines and at least two gate lines, and at least two data lines to be supplied to at least two data lines. A data driving circuit for sequentially supplying signals to the signal lines and a data signal from the signal lines in common with the signal lines and connected to at least two data lines respectively in response to selection signals from at least two control lines, respectively. Data from the switching element in response to a redundant selection signal from the redundant control line, each connected between at least two or more switching elements and at least two switching elements and at least two data lines, respectively, for outputting the signal to one of the data lines. Line side A noise component introduced into the signal to be provided with at least two or more control by-pass means for by-pass.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 7 to 10.

Referring to FIG. 7, an LCD according to an embodiment of the present invention is schematically illustrated. The LCD of FIG. 7 includes n demultiplexers DMUX1 to DMUXn connected between the data lines DL1 to DL3n on the liquid crystal panel 20 and the data driving circuit 22, and m gates on the liquid crystal panel 20. FIG. And a scan driving circuit 24 for sequentially driving the lines GL1 to GLm by horizontal scanning periods. The liquid crystal panel 20 includes a pixel matrix in which pixels are arranged at intersections between 3n data lines DL1 to DL3n and m gate lines GL1 to GLm. Each of the pixels selectively connects the liquid crystal cell to adjust the amount of transmitted light in response to the data signal from the data line DL and to the liquid crystal cell and the data line DL in response to a scan pulse from the gate line GL. It is comprised by a switching TFT. The data driving circuit 22 generates 3n data signals to be supplied to each of the 3n data lines DL1 to DL3n per period of the horizontal synchronization signal. The 3n data signals generated in the data driving circuit 22 are output n times three times through n signal lines SL1 to SLn. Specifically, n data signals to be supplied to the 3i-2th data lines DL1, DL4, ..., DL3n-2 during the period in which the first selection signal MCLK1 in FIG. 8 maintains high logic. It is output from the drive circuit 22. N data signals to be supplied to the 3i-1 < th > data lines DL2, DL5, ..., DL3n-1 during the period in which the second selection signal MCLK2 in Fig. 8 maintains high logic. ) During the period in which the first selection signal MCLK1 in FIG. 8 maintains high logic, n data signals to be supplied to the 3i th data lines DL3, DL6, ..., DL3n are outputted from the data driving circuit 22. FIG. do. The gate driving circuit 24 sequentially drives the m gate lines GLm at intervals of the horizontal synchronization signal for one frame period. To this end, the gate driving circuit 24 generates m scan pulses (SPS) that maintain high logic sequentially in the period of the horizontal synchronization signal as shown in FIG. In Fig. 8, SPSi represents a scan pulse supplied to the j-th gate line GLj and SPSj + 1 represents a scan pulse supplied to the j + 1th gate line GLj + 1, respectively.

On the other hand, each of the n demultiplexers DMUX1 to DMUXn receives three data lines DL3i-2 and DL3i for data signals supplied from the data driving circuit 22 via the signal lines SL1 to SLn at horizontal synchronization periods. -1, DL3i) to be demultiplexed. To this end, each of the demultiplexers DMUX1 to DMUXn includes first to third thin film transistors MN1 to MN3 commonly connected to the signal lines SL1 to SLn. These first to third TFTs MN1 to MN3 are sequentially turned on one by one while the gate pulse GPS as shown in FIG. 9 is supplied to any one of the m gate lines GL1 to GLm. Turn-on). In detail, the first TFT MN1 has the signal lines SL1, SL2,..., During the period in which the first selection clock MCLK1 applied from the first control line CL1 toward its gate terminal maintains high logic. The data signal from SLn is transferred to the 3i-2th data lines DL1, DL4, ..., DL3n-2. The second TFT MN2 also receives the signal from the signal lines SL1, SL2, ..., SLn during the period in which the second select clock MCLK2 applied from the second control line CL2 toward its gate terminal maintains high logic. The data signal is transferred to the 3i-1th data lines DL2, DL5, ..., DL3n-1. In the third TFT MN3, the signal lines SL1, SL2,... Are maintained during the period in which the third select clock MCLK3, which is applied from the third control line CL3 toward its gate terminal, maintains high logic as shown in FIG. The data signal from SLn is transferred to the 3i th data lines DL3, DL6, ..., DL3n. Further, when each of the first to third TFTs MN1 to MN3 enters the turn-off state from the turn-on state, the charges charged in the channel of the first to third TFTs MN1 to MN3 are different from those of the equivalent circuit of FIG. 9. As described above, the discharge is divided into the signal line SL and the data line DL. When the first to third TFTs MN1 to MN3 are turned off, the amount of charge supplied to the data line DL serves as a noise component signal.

In order to bypass the noise component signal to be supplied to the data line DL as described above, each of the demultiplexers DMUX1 to DMUXn is serially connected between the first to third TFTs MN1 to MN3 and the data line DL, respectively. Further, the first to third auxiliary TFTs AMM1 to ANN3 connected to each other may be further provided. These first to third auxiliary TFTs ANN1 to ANN3 are turned on by all of the first to third TFTs MN1 to MN3 by the redundancy select signal MCLKx supplied from the fourth control line CL4. The turn-on in the off period absorbs (or bypasses) the noise component signals on the data lines DL. In other words, the first to third auxiliary TFTs AMN1 to AMN3 are connected between the data lines DL1 to DL3n and the fourth control line CL4 so as to generate a noise component signal on the data lines DL1 to DL3n. It functions as an auxiliary capacitor for bypassing them to the fourth control line CL4. In detail, the first auxiliary TFT AMN1 responding to the redundant select signal MCLKx as in the eighth from the fourth control line CL4 is the first TFT when the first TFT MN1 is turned off. The charge flowing from the MN1 toward the data lines DN1, DN4, ..., DN3n-2 is absorbed. Similarly, the second auxiliary TFT AMN2 responsive to the redundant selection signal MCLKx from the fourth control line CL4 also has a data line from the second TFT MN1 when the second TFT MN2 is turned off. It absorbs the charge flowing into DN2, DN5, ..., DN3n-1). Similarly, the third auxiliary TFT AMM3 in response to the redundant selection signal MCLKx from the fourth control line CL4 also has a data line (A) from the third TFT MN3 when the third TFT MN3 is turned off. It absorbs the charge flowing into DN3, DN6, ..., DN3n). Accordingly, when the TFTs MN are turned off, the same charge amount Qoff in Equation 2 supplied to the data line DL supplied from the TFTs MN is the same as in the equivalent circuit of FIG. 9. Bypass through (AMN). As a result, the voltage on the data line DL does not change even when the TFTs MN enter the turn-off state from the turned-on state. The auxiliary TFT (AMN) has a capacitance value corresponding to 1/2 of the capacitance value Cmn of the channel of the TFT (MN) in order to sufficiently absorb the amount of charge from the TFT (MN) when the TFT (MN) is turned off. It is formed to have (Camn). In other words, the channel width of the auxiliary TFT (AMN) is half the channel width of the TFT (MN). In addition, the redundancy select signal MCLKx is enabled once in a complementary manner every time the m scan pulses SPS maintain high logic together with the first to third select signals MCLK1 to MCLK3. The first to third selection signals MCLK1 to MCLK3 are sequentially enabled and finally enabled. Accordingly, the first to third auxiliary TFTs AMN1 to ANN3 may be turned on and turned off after the first to third TFTs MN1 to MN3 are sequentially turned on and off. Will be.

As described above, in the LCD of FIG. 7, the bypass auxiliary TFT AMN is added to the demultiplexers DMUX1 to DMUXn so that the feed through voltage ΔVp is not generated in the data line DL. Accordingly, the light transmittance of the liquid crystal cells on the liquid crystal panel 10 becomes uniform, and further, the image displayed on the liquid crystal panel 10 is not distorted and / or degraded. In addition, in the LCD of Fig. 7, all of the auxiliary TFTs AMN1 to ANN3 respond in common to the redundant selection signal MCLKx, so that the control wiring for the demultiplexers DMUX1 to DMUXn is significantly higher than that of the LCD shown in Fig.4. It will be simplified. Accordingly, even if the demultiplexers DMUX1 to DMUXn are formed on the liquid crystal panel 20, the defective rate of the liquid crystal panel is significantly reduced, and the manufacturing yield is significantly increased. Furthermore, the defective rate of the LCD is reduced and the manufacturing yield of the LCD is improved.

10 schematically illustrates an LCD according to another embodiment of the present invention. The LCD of FIG. 10 is similar to the LCD of FIG. 7, except that only the source terminals of the first to third auxiliary TFTs AMN1 to ANN3 are commonly connected to the base voltage line VSSL. In detail, the first auxiliary TFT AMN1 is disposed between the first TFT MN1 and the base voltage line VSSL, and the second auxiliary TFT AMN2 is connected to the second TFT MN2 and the base voltage line VSSL. The third auxiliary TFT ANN3 is connected between the third TFT MN3 and the ground voltage line VSSL, respectively. These first to third auxiliary TFTs ANN1 to ANN3 are turned on by all of the first to third TFTs MN1 to MN3 by the redundancy select signal MCLKx supplied from the fourth control line CL4. The turn-on period during the off period causes the noise component signals on the data lines DL to be bypassed toward the ground voltage line VSSL. In other words, the first to third auxiliary TFTs AMN1 to AMN3 are connected between the data lines DL1 to DL3n and the fourth control line CL4 so as to generate a noise component signal on the data lines DL1 to DL3n. It functions as an auxiliary capacitor that bypasses them to the ground voltage line VSSL. In detail, the first auxiliary TFT AMN1 responding to the redundant select signal MCLKx as in the eighth from the fourth control line CL4 is the first TFT when the first TFT MN1 is turned off. The charge flowing from the MN1 to the data lines DN1, DN4, ..., DN3n-2 is bypassed toward the base voltage line VSSL. Similarly, the second auxiliary TFT AMN2 responsive to the redundant selection signal MCLKx from the fourth control line CL4 also has a data line from the second TFT MN1 when the second TFT MN2 is turned off. The charge flowing into DN2, DN5, ..., DN3n-1) is bypassed toward the ground voltage line (VSSL). Similarly, the third auxiliary TFT AMM3 in response to the redundant selection signal MCLKx from the fourth control line CL4 also has a data line (A) from the third TFT MN3 when the third TFT MN3 is turned off. The charge flowing into DN3, DN6, ..., DN3n) is bypassed to the ground voltage line (VSSL). Accordingly, when the TFTs MN are turned off, the same amount of charge Qoff in Equation 2 supplied toward the data line DL supplied from the TFTs MN is bypassed through the auxiliary TFTs AMN. do. As a result, the voltage on the data line DL does not change even when the TFTs MN enter the turn-off state from the turned-on state. In addition, the redundancy select signal MCLKx is enabled once in a complementary manner every time the m scan pulses SPS maintain high logic together with the first to third select signals MCLK1 to MCLK3. The first to third selection signals MCLK1 to MCLK3 are sequentially enabled and finally enabled. Accordingly, the first to third auxiliary TFTs AMN1 to ANN3 are turned on and turned off after the first to third TFTs MN1 to MN3 are sequentially turned on and off. Will be.

As described above, in the LCD of FIG. 10, the bypass auxiliary TFT AMN is added to the demultiplexers DMUX1 to DMUXn so that the feed through voltage ΔVp is not generated in the data line DL. Accordingly, the light transmittance of the liquid crystal cells on the liquid crystal panel 10 becomes uniform, and further, the image displayed on the liquid crystal panel 10 is not distorted and / or degraded. Further, in the LCD of Fig. 10, all of the auxiliary TFTs AMN1 to ANN3 respond in common to the redundant selection signal MCLKx, so that the control wiring for the demultiplexers DMUX1 to DMUXn is significantly higher than that of the LCD shown in Fig. 4. It will be simplified. Accordingly, even if the demultiplexers DMUX1 to DMUXn are formed on the liquid crystal panel 20, the defective rate of the liquid crystal panel is significantly reduced, and the manufacturing yield is significantly increased. Furthermore, the defective rate of the LCD is reduced and the manufacturing yield of the LCD is improved.

As described above, in the demultiplexer according to the present invention, the auxiliary TFTs connected to each of the output lines commonly respond to the redundant selection signal, thereby simplifying the control wiring.

In addition, in the liquid crystal panel according to the present invention, the bypass auxiliary TFT AMN is added to the demultiplexers DMUX1 to DMUXn so that the feed through voltage ΔVp is not generated in the data line DL. Accordingly, the light transmittance of the liquid crystal cells on the liquid crystal panel 10 becomes uniform, and further, the image displayed on the liquid crystal panel 10 is not distorted and / or degraded. In addition, in the liquid crystal panel according to the present invention, the control TFTs for the demultiplexers DMUX1 to DMUXn are remarkably simplified by all of the auxiliary TFTs AMN1 to ANN3 responding in common to the redundant select signal MCLKx. Accordingly, even if formed on the liquid crystal panel 20 integrated with the demultiplexers DMUX1 to DMUXn, the defective rate of the liquid crystal panel is remarkably reduced as well as the manufacturing yield is significantly increased. Furthermore, the defective rate of the LCD is reduced and the manufacturing yield of the LCD is improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

At least two switching elements which are commonly connected to the input lines and which are respectively connected to at least two or more output lines so that a signal from the input line is output to any one of the output lines in response to a selection signal from at least two or more control lines, respectively. Wow, At least two or more connected respectively between said at least two switching elements and said at least two output lines and bypassing noise component signals to be introduced from said switching element toward said output line in response to a redundant selection signal from a redundant control line; A demultiplexer characterized by including a bypass control means. The method of claim 1, And the field bypass transistor for selectively performing a bypass operation in response to the redundant selection signal. The method of claim 2, And said switching element comprises a field effect transistor. The method of claim 1, And a field effect transistor included in the control bypass means having a smaller channel width than that of the field effect transistor included in the switching element. A pixel matrix arranged at each intersection of at least two data lines and at least two gate lines, A signal line for inputting two or more data signals to be supplied to the at least two data lines; At least two data lines commonly connected to the signal lines and respectively connected to the at least two data lines to respectively output data signals from the signal lines to one of the data lines in response to a selection signal from at least two control lines. Two or more switching elements, At least two or more connected respectively between said at least two switching elements and said at least two data lines and bypassing a noise component signal to be introduced from said switching element toward said data line in response to a redundant selection signal from a redundant control line; A demultiplexer integrated liquid crystal panel comprising a bypass means for control. The method of claim 5, And a field effect transistor configured to selectively perform a bypass operation in response to the redundant selection signal. The method of claim 6, And said switching element comprises a field effect transistor. The method of claim 5, And the field effect transistor included in the control bypass means has a smaller channel width than the field effect transistor included in the switching element. A liquid crystal panel having a pixel matrix arranged at each intersection of at least two data lines and at least two gate lines; A data driving circuit which sequentially supplies two or more data signals to be supplied to the at least two data lines to a signal line; At least two data lines commonly connected to the signal lines and respectively connected to the at least two data lines to respectively output data signals from the signal lines to one of the data lines in response to a selection signal from at least two control lines. Two or more switching elements, At least two or more connected respectively between said at least two switching elements and said at least two data lines and bypassing a noise component signal to be introduced from said switching element toward said data line in response to a redundant selection signal from a redundant control line; A demultiplexer integrated liquid crystal display device comprising control bypass means. The method of claim 9, And a field effect transistor for selectively performing bypass operation in response to the redundant selection signal. The method of claim 10, And said switching element comprises a field effect transistor. The method of claim 9, And the field effect transistor included in the control bypass means has a smaller channel width than the field effect transistor included in the switching element.