KR20000013740A - Bit line discharge circuit in a semiconductor memory device - Google Patents

Abstract

PURPOSE: A bit line discharge circuit is provided to make a big voltage difference between bit lines when reading data in a low voltage and high speed operation. CONSTITUTION: The bit line discharge circuit comprises: a memory cell array; a bit line discharge circuit for discharging a corresponding bit line of a pair of bit lines connected to a corresponding memory cell; and a sense amplifier for sensing a voltage difference between the bit lines and outputting data of the memory cell.

Description

BIT LINE DISCHARGE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to bit line discharge circuits.

Referring to FIG. 1, a semiconductor memory device includes a memory cell array 10, a row decoder 20, a column decoder 30, and a sense amplifier 40. The memory cell array 10 includes a plurality of memory cells and a plurality of word lines extending along the memory cells in a row direction and a plurality of bit line pairs extending along the memory cells in a column direction. The row decoder 20 receives a row address R_ADDR during a write and read operation to select a corresponding one of the word lines of the memory cell array 10.

The column decoder 30 receives a column address C_ADDR during the write and read operations to select a corresponding one of the bit line pairs of the bit line pairs of the memory cell array 10. The sense amplifier 40 supplies data DATA from outside during the write operation to the memory cell selected by the row address R_ADDR and the column address C_ADDR through the selected bit line pair and during the read operation. The data DATA output from the selected memory cell is sensed and output.

In a read operation of a semiconductor memory device according to the related art, one of the word lines is selected, and charges of one bit line of the selected pair of bit lines that have been precharged in advance are stored in the memory. It discharges through the discharge transistor provided in the cell. The sense amplifier 40 senses the voltage difference between the pair of bit lines selected during the read operation. At this time, in order for the sense amplifier to normally sense, the voltage difference between the pair of bit lines must be increased by a predetermined voltage level or more.

However, as the degree of integration of the semiconductor memory device increases, the capacitance formed in the bit lines is relatively increased, and the driving capability of the pull-down transistor in the memory cell is reduced. As the operating voltage is lowered, the voltage difference between the bit lines becomes smaller. When the voltage difference between the bit lines is small, a malfunction that outputs wrong data occurs.

Accordingly, an object of the present invention is to provide a bit line discharge circuit of a semiconductor memory device which generates a large voltage difference between bit lines in a read operation under low voltage and high speed operation.

1 is a block diagram of a general semiconductor memory device;

2 is a detailed circuit diagram of a discharge circuit of a semiconductor memory device according to the present invention; And

3 is an operational waveform diagram showing a read operation according to the present invention.

* Explanation of symbols on the main parts of the drawings

100: memory cell array 200: bit line discharge circuit

300: sense amplifier

(Configuration)

According to one aspect of the present invention for achieving the above object, an array of memory cells each connected to a plurality of word lines and a plurality of pair of bit lines; Sensing means for sensing data from a corresponding memory cell during a read operation; Charged in one bit line of a pair of bit lines corresponding to a first control signal activated simultaneously with the selected word line and a second control signal having a level complementary to the first control signal during the read operation; Bit line discharge means for discharging charges.

In this embodiment, the bit line discharging means includes a first node and charges charged in a first bit line among corresponding bit lines in response to the first and second control signals to the first node. A first transfer circuit for transferring, a second node, and a second transfer for transferring charges charged to a second bit line of corresponding bit lines in response to the first and second control signals to the second node; A circuit, a blocking circuit for blocking a conductive path between the first and second nodes, and a discharge circuit for selectively discharging charges charged in the first and second bit lines, respectively.

In this embodiment, the discharge circuit includes a first NMOS transistor having a current path formed between the first node and a ground voltage and a gate connected to the second node, and between the second node and the ground voltage. And second NMOS transistors having a current path formed in the gate and a gate connected to the first node.

(Action)

With such a device, the read operation speed can be improved by increasing the voltage difference generated between the bit lines during the read operation.

(Example)

Hereinafter, a detailed description will be made based on reference drawings 2 and 3 according to an embodiment of the present invention.

Referring to FIG. 2, the novel semiconductor memory device of the present invention provides a memory cell array 100, a bit line discharge circuit 200, and a sense amplifier 300. The bit line discharge circuit 200 discharges one bit line of a pair of bit lines connected to a corresponding memory cell of the memory cell array 100 when a read operation is started. The sense amplifier 300 senses a voltage difference between the bit lines and outputs data from the memory cell 100.

Referring to FIG. 2, a semiconductor memory device according to the present invention includes a memory cell array 100, a bit line discharge circuit 200, and a sense amplifier 300. The memory cell array 100 includes a plurality of word lines W / L0, W / L1, ... W / Ln-1, W / Ln that extend along the memory cells in a row direction. And a plurality of pairs of bit line pairs B / L0, B / L0b, ..., B / Ln, and B / Lnb extending along the memory cells in a column direction. The bit line discharge circuit 200 includes transfer gates 210 and 220 and NMOS transistors 230, 240 and 250. The transfer gate 210 has gates controlled by current paths and signals sig and sigb formed between one of the bit lines B / L and the node N1 of each pair of bit lines. . The transfer circuit 220 has a current path formed between the bit line B / Lb and the node N2 and gates controlled by the signals sig and sigb.

The NMOS transistor 230 has a current path formed between the nodes N1 and N2 and a gate controlled by the signal sigb. The NMOS transistor 240 has a current path formed between the node N1 and the ground voltage VSS and a gate connected to the node N2. The NMOS transistor 250 has a current path formed between the node N2 and the ground voltage VSS and a gate connected to the node N1. The sense amplifier 300 is connected between the pair of bit lines B / L0, B / L0b, ..., B / Ln, and B / Lnb and a data line.

Hereinafter, the operation of the bit line discharge circuit of the present invention will be described with reference to FIGS. 2 and 3.

2 and 3, a semiconductor memory device, in particular an SRAM, has a plurality of memory cells in the form of latch circuits connected to a pair of bit lines. The read operation of the SRAM is performed by using a voltage difference between the pair of bit lines connected to the selected memory cell. For example, the read operation of the SRAM is an operation of reading data stored in the memory cell C00 by selecting one memory cell C00 of the plurality of memory cells. When the read operation is started, a word line W / L0 and a bit line B / L0 corresponding to the memory cell are selected to select the memory cell C00 (not shown). When the read operation is started, the pair of bit lines B / L0 and B / L0b connected to the memory cell C00 may have a predetermined voltage level {eg (1) during the precharge operation performed before the read operation. / 2) precharged to VCC}.

If the memory cell C00 is selected and data of '1' is stored in the memory cell C00, the charges charged in the bit line B / L0 are maintained at the precharge voltage level. Charges charged in the line B / L0b are discharged to the ground voltage VSS through a pull-down transistor of the memory cell C00. As a result, a minute voltage difference is generated between the bit lines B / L0 and B / L0b. The sense amplifier 300 amplifies the minute voltage difference generated in the bit lines B / L0 and B / L0b and outputs the amplified voltage to the data line. The bit line discharge circuit 200 performs the bit lines when the read operation starts, that is, when the word line W / L0 and the bit lines B / L0 and B / L0b are selected. The charges charged in one of the bit lines B / L0 and B / L0b are selectively discharged.

When the word line W / L0 and the bit lines B / L0 and B / L0b are selected, since data of '1' is stored in the memory cell C00, the bit line B / L0 is stored. Is maintained at the precharge voltage level and the bit line B / L0b maintains a voltage level slightly lower than the precharge voltage level. In this case, the NMOS transistor 230 of the bit line discharge circuit 200 separates the bit lines B / L0 and B / L0b by controlling the signal sigb at a low level. The transfer gates 210 and 220 transfer charges charged in the bit lines B / L0 and B / L0b to the NMOS transistors 240 and 250 by controlling the signals sig and sigb. To pass. The NMOS transistor 240 discharges the charges charged in the node N2, that is, the charges charged in the node N1 according to the voltage level of the bit line B / L0b. The NMOS transistor 250 discharges charges charged in the node N1, that is, charges charged in the node N2 according to the voltage level of the bit line B / L0.

In this case, the bit lines B / L0b are discharged through the pull-down transistor of the memory cell C00 to be charged at a precharge voltage level, thereby lowering the voltage level. As a result, the amount of charges that the NMOS transistor 240 discharges from the node N1 to the ground voltage VSS gradually decreases so that the bit line B / L0 maintains the precharge voltage level. . As a result, the amount of charges discharged by the NMOS transistor 250 from the node N2 to the ground voltage VSS is kept constant. Due to the above operation, the voltage difference generated between the bit lines B / L0 and B / L0b becomes larger.

The discharged voltage of the bit line B / L0b according to the related art in the early stage of the read operation of FIG. 3 represents '0.8' volt. However, the discharged voltage of the bit line B / L0b according to the present invention remains constant between '0.457 and 0.5' volts. Recently, as the degree of integration of semiconductor memory devices increases and the operating speed becomes higher, the operating voltage also decreases. As the operating voltage is lowered and the operating speed is increased, the voltage applied to the bit line is lowered and the time given to the sensing operation of the sense amplifier 300 is reduced. When the voltage applied to the bit line is lowered, the capacitance of the bit lines is the same but the operating voltage is lowered, so that the time difference between the bit lines is generated. The bit line discharge circuit 200 of the present invention increases the voltage difference between the bit lines B / L0 and B / L0b in a short time. Thus, the read operation speed can be improved by increasing the voltage difference generated between the bit lines during the read operation under the low voltage and the high speed operation.

As described above, the read operation speed can be improved by increasing the voltage difference generated between the bit lines during the read operation under the low voltage and the high speed operation.

Claims (3)

An array of memory cells each connected to a plurality of word lines and a plurality of pairs of bit lines, respectively; Sensing means for sensing data from a corresponding memory cell during a read operation; Charged in one bit line of a pair of bit lines corresponding to a first control signal activated simultaneously with the selected word line and a second control signal having a level complementary to the first control signal during the read operation; And a bit line discharge means for discharging charges. The method of claim 1, The bit line discharge means, The first node, A first transfer circuit transferring charges charged to a first bit line among corresponding bit lines to the first node in response to the first and second control signals; The second node, A second transfer circuit transferring charges charged to a second bit line among corresponding bit lines to the second node in response to the first and second control signals; A blocking circuit for blocking a conductive path between the first and second nodes; And a discharge circuit for selectively discharging charges charged in the first and second bit lines, respectively. The method of claim 2, The discharge circuit, A first NMOS transistor having a current path formed between the first node and a ground voltage and a gate connected to the second node; And second NMOS transistors having a current path formed between the second node and the ground voltage and a gate connected to the first node.