KR20000012200U - Signal level balancing device of digital transmitter - Google Patents

Abstract

A signal level balancing device of a digital transmitter capable of automatically balancing signal levels in response to temperature or component characteristic tolerance fluctuations and preventing transmission characteristics deterioration. A first and second amplifiers for amplifying at an amplification rate, an attenuator for attenuating the output level of the second amplifier at a constant attenuation rate to maintain balancing of the I signal level and the Q signal level, and an output level of the first op amp and the attenuator. The first and second level detectors respectively detecting the first and second level detectors, and a comparator for calculating the difference between the first and second level detector output values and feeding them back to the attenuation rate of the attenuator. It is possible to improve the signal transmission efficiency by maintaining the balancing of.

Description

Signal level balancing device of digital transmitter

The present invention relates to a digital transmitter, and more particularly, to a signal strength balancing device of a digital transmitter.

In general, a transmission path of a code division multiple access (CDMA) base station, which is a digital transmission method, includes a baseband signal processing unit for processing a baseband signal, an upconverter for performing frequency upward adjustment, an amplifier, and a transmission. An antenna or the like.

At this time, the baseband signal processing unit converts the baseband signal I (Inphase) / Q (Quardrature) signal to IF signal, the I signal and Q signal level is a variety of characteristics such as temperature and characteristic tolerance of each component Unbalance occurs due to factors, and unbalance of two signal levels acts as an adverse effect on RF transmission characteristics.

Therefore, the digital transmitter is connected to a circuit for correcting the imbalance between the I signal and the Q signal level to achieve balancing.

As shown in FIG. 1, a signal level balancing device of a digital transmitter according to the related art uses an I / Q signal transmission logic output from a digital signal processor 11 and a digital signal processor 11 that perform digital signal processing. First and second op amps A1 and A2 for amplifying the I / Q signals output through the FPGA 12 and the amplification gains, respectively; I output from the variable resistor VR1 and the first and second op amps A1 and A2 for correcting the balance of the I / Q signal levels by adjusting the Q signal level in conjunction with the 2 op amps A2. And an I / Q modulator 13 for modulating the / Q signal into an IF signal in accordance with the local oscillation frequency.

Referring to the I / Q signal level balancing operation of the prior art configured as described above are as follows.

The I / Q signal digitally processed by the digital signal processor 11 is output to the first op amp A1 and the second op amp A2 through the FPGA 12, respectively.

The first and second op amps A1 and A2 amplify the I signal and the Q signal at respective amplification rates. In this case, the amplification ratio is adjusted by adjusting the variable resistance VR1 of the second op amp A2. By varying, the two signal levels are balanced.

The balanced I and Q signals are converted into IF signals by the I / Q modulator 13 and transmitted to the up converter described above for conversion into RF signals.

Therefore, the signal level balancing device according to the related art adjusts the signal level balancing in a state in which the variable resistance value is adjusted and fixed to a specific value, so that even if an imbalance in the signal level occurs due to temperature or component characteristic tolerance fluctuations Since this cannot be corrected, there is a problem in that the IF signal characteristic is degraded and the transmission characteristic itself is deteriorated.

The present invention has been made to solve the above-mentioned problems, and the signal of the digital transmitter to prevent the deterioration of transmission characteristics by automatically balancing the signal level in response to temperature or component characteristic tolerance variation, etc. The purpose is to provide a level balancing device.

The present invention provides a first amplifier and a second amplifier for amplifying the I signal and the Q signal at respective amplification rates, and an attenuator for maintaining the balancing of the I signal level and the Q signal level by attenuating the output level of the second amplifier at a predetermined attenuation rate. And first and second level detectors for detecting the output levels of the first op amp and the attenuator, respectively, and a comparator for calculating a difference between the first and second level detector output values and feeding them back to the attenuation rate values of the attenuator. It features.

1 is a block diagram showing the configuration of a signal level balancing device of a digital transmitter according to the prior art;

2 is a block diagram showing the configuration of a signal level balancing device of a digital transmitter according to the present invention.

Explanation of symbols for main parts of the drawings

11: digital signal processor 12: FPGA

13: I / Q modulator 21: first level detector

22: second level detector 23: comparator

24: Attenuator

Hereinafter, a signal level balancing device of a digital transmitter according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing the configuration of a signal level balancing device of a digital transmitter according to the present invention.

As shown in FIG. 2, the signal level balancing device of the digital transmitter according to the present invention forms an I / Q signal transmission logic output from the digital signal processor 11 and the digital signal processor 11 that perform digital signal processing. First and second op amps A1 and A2 for amplifying the I / Q signals output via the FPGA 12 and the FPGA 12 with amplification gains, respectively. An attenuator 24 which attenuates the output of the operational amplifier A2 at a constant attenuation rate to maintain the balance between the I signal level and the Q signal level, and detects output levels of the first operational amplifier A1 and the attenuator 24, respectively. A comparator 23 for calculating a difference between the first and second level detectors 21 and 22 and the output values of the first and second level detectors 21 and 22 and feeding it back to the attenuation rate value of the attenuator 24; The I / Q signal output from the first op amp A1 and the attenuator 24 is modulated into an IF signal according to the local oscillation frequency. It consists of an I / Q modulator 13.

Referring to the I / Q signal level balancing operation of the present invention configured as described above are as follows.

The I / Q signal digitally processed by the digital signal processor 11 is output to the first op amp A1 and the second op amp A2 through the FPGA 12, respectively.

The first and second op amps A1 and A2 amplify the I and Q signals at respective amplification rates, and the output of the second op amp A2 is attenuated by a predetermined level via the attenuator 24. do.

Subsequently, the outputs of the first op amp A1 and the attenuator 24 are calculated through the first level detector 21, the second level detector 22, and the comparator 23, respectively, and the difference between the two outputs is calculated. The I and Q signals are balanced because they are fed back to the attenuator 24 and used as an attenuation rate to attenuate the Q value.

For example, the amplification gain of the first op amp A1 is referred to as 'A' and the amplification gain of the second op amp A2 is referred to as 'A + B'. If the value is 'C', the Q signal has a level as high as 'B' compared to the I signal when the balance state is achieved, that is, when the imbalance value 'C' does not exist, the value is attenuation rate of the attenuator 24. The signal is inputted as and attenuates the Q signal by 'B', thereby balancing the I and Q signals.

At this time, A is set to be larger than B, and C is smaller than B because C is due to temperature or component characteristic tolerance variation.

In addition, if there is no balancing between the I and Q signals and an imbalance value 'C' exists and the 'C' value is positive, the attenuation rate of the attenuator 24 is increased by 'C' and becomes 'B + C'. When the Q signal is attenuated by 'B + C' and the 'C' value is negative, the attenuation rate of the attenuator 24 is reduced by 'C' to be 'B-C'. And the Q signal is balanced.

The balanced I and Q signals are converted into IF signals by the I / Q modulator 13 and transmitted to the up converter described above for conversion into RF signals.

The signal level balancing device of the digital transmitter according to the present invention calculates the difference between two signal levels whenever the signal level is unbalanced due to various factors such as temperature and component characteristic tolerance fluctuations, and applies the value as an attenuation rate. Since the attenuation operation is performed so that the signal level can be balanced, it is possible to maintain the balancing of the two signal levels at all times, thereby preventing the deterioration of the IF signal and deteriorating the RF transmission characteristic, thereby improving the signal transmission efficiency. have.

Claims (3)

In a digital transmitter, First and second amplifiers for amplifying the I and Q signals at respective amplification rates; An attenuator for attenuating the output level of the second amplifier at a constant attenuation rate to maintain balancing of the I signal level and the Q signal level; First and second level detectors respectively detecting output levels of the first op amp and the attenuator; And a comparator for calculating a difference between the first and second level detector output values and feeding it back to the attenuation rate value of the attenuator. The method of claim 1, And amplifying gain of the first amplifier is smaller than that of the second amplifier. The method of claim 2, And a difference value between the amplification gain of the first amplifier and the second amplifier is greater than the difference value of the signal level due to temperature and component characteristic tolerance variations.