KR20000010200A - Instruction decoder having reduced instruction decoding path - Google Patents

Abstract

PURPOSE: An instruction decoder is provided to reduce a instruction decoding path by remove a critical path for decoding the instruction in microprocessor operating at high speed. CONSTITUTION: The instruction decoder comprises a prefetch unit(210); an instruction que unit(220) and a decoding unit(230). In the instruction decoder, in response to cache hit signal or cache miss signal output from a cache unit(200), on cache hit, the prefetch unit receives a instruction line output from the cache unit, and on cache miss, the prefetch unit receives a instruction line which is accessed and input from external memory. From the received instruction lines, the prefetch checks whether the instruction to be executed in each pipeline can be executed in parallel or not, and predecodes the instruction. The instruction que unit stores the instruction which is output from the prefetch unit. The decoding unit finally decodes the instruction of each pipeline output from the instruction que unit, respectively. Thereby, it is possible to eliminate the critical decoding path so that it is can be executed a high speed operating stably.

Description

Instruction decoding device with reduced instruction decoding path

The present invention relates to a microprocessor, and more particularly to an instruction decoding apparatus for reducing the path of instruction decoding.

In general, high-performance microprocessors have a superscalar structure of multiple pipelines in order to increase instruction process throughput. That is, it consists of a structure that executes two or more instructions simultaneously in each pipeline consisting of a plurality of stages.

1 is a diagram illustrating a plurality of stages for processing instructions in a conventional superscalar high-performance microprocessor, in which instruction fetch stages, fetches, which prefetch instructions from a cache to be executed in the X pipeline and the Y pipeline, respectively. X pipeline and Y, consisting of an instruction decoding stage that decodes one instruction, an address generation stage that calculates the address of the data to retrieve from the data cache, an execution stage that executes the instruction, and a write back stage that writes the result to memory or a register. In the pipeline, two instructions are executed simultaneously for each stage.

2 is a block diagram of a conventional superscalar microprocessor, where 100 is a cache unit, 110 is an instruction queue unit, 120 is an instruction decoder unit, 130 is an execution unit, 140 is a bus interface unit, and 150 is a Multiplexer 160 denotes a data cache and 170 denotes a register file.

Referring to Figure 2, a conventional instruction processing method will be described.

The superscalar microprocessor configured as described above reads the instruction code from the cache unit 100 or the external memory 10 and stores the instruction code in the instruction queue unit 110 in order to support a high instruction request bandwidth. Export the command code to (120). In the parallelism check block 121 of the decoder unit 120, parallel execution of two consecutive instructions is checked. According to the parallelism, the instruction is allocated to the decoders 122 and 123 of the X pipeline and the Y pipeline, and the decoders 122 and 123 of each pipeline are determined after deciding whether or not to proceed with the lower priority Y pipeline. Decoding information about the size, the register address, and the processor dependant is output to the execution unit 130. The final result after executing the instruction in the execution unit 130 is written to the data cache 160 or the register file 170.

In the conventional superscalar microprocessor as described above, the longest decoding path may include: checking parallelism in the parallelism check block 121 of the decoder unit 120, assigning instructions to each pipeline, and each A sequential path consisting of decoding instructions at the decoders 122 and 123 of the pipeline, and reading a register file to access data in response to the decoding result. This limits the performance of the processor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an instruction decoding apparatus for reducing an instruction decoding path by removing a critical path during instruction decoding in a microprocessor operating at a high speed.

1 illustrates a number of stages for processing instructions in a high performance microprocessor of a conventional superscalar structure.

2 is a block diagram of a conventional superscalar microprocessor.

3 is a block diagram of a microprocessor in accordance with an embodiment of the present invention.

* Description of the main parts of the drawing

200: cache unit 210: prefetch unit

220: instruction queue unit 230: decoder unit

240: execution unit 250: memory resource unit

260 bus interface unit

213: parallelism check block 214: predecoder

The instruction decoding apparatus of the present invention for achieving the above object, the command line output from the cache unit when the cache hit in response to the cache hit / miss signal output from the cache unit, and is accessed by input from the external memory when the cache miss A prefetch unit which receives a command line and checks the parallel execution possibility of instructions to be executed in each pipeline, and performs predecoding for the instructions; An instruction queue unit configured to store an instruction to be executed currently output from the prefetch unit; And a decoder unit for finally decoding an instruction output for each pipeline from the instruction queue unit.

The present invention eliminates the critical path during instruction decoding of a high speed microprocessor by distributing the processing in the instruction fetch and decoding stages in a prefetch cycle to satisfy the high instruction request bandwidth of a high performance microprocessor. do.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

3 is a block diagram of a microprocessor according to an exemplary embodiment of the present invention. The coderam 203 stores instructions frequently used in the execution unit 240 in a row in succession, and supplies the instructions required during a cache hit. And a tag 202 that stores an instruction tag address that is compared with the common address high order bits of the instructions stored in one line of coderam 203 to determine a cache hit / miss of the instruction, and a cache hit of the required instruction. The cache unit 200 including a cache controller 201 for determining / missing and supplying instructions and fetching instructions external memory, a bus interface unit 240 for accessing external memory in case of a cache miss, and a cache Through the command line output from the code RAM 203 in response to the hit / miss signal and the cache miss bus interface unit 240. Each pipe receives a multiplexer 204 that selects and outputs one of the command lines to be newly stored in the code RAM 203 of the cache unit 200 from the secondary memory, and a command line output from the multiplexer 204. A command for checking the parallel execution possibility of an instruction to be executed in a line, and prefetching unit 210 performing initial decoding of the instruction, and storing a current execution instruction outputted from the prefetch unit 210. Input the queue unit 220, the decoder unit 230 for final decoding (postdecoding) instructions output from the instruction queue unit 220 for each pipeline, and the instructions output for each pipeline from the decoder unit 230 are inputted. An execution unit 240 that receives and performs an appropriate instruction operation and data that receives and stores a result of performing an instruction from the execution unit 240. When 251 and comprises a memory resource units (resource memory unit, 250) comprising a register file (252).

The prefetch unit 210 outputs the command buffer A 211 and the command buffer B 212 which alternately store the command lines output from the multiplexer 204 for each pipeline, and the command buffers 211 and 212. A parallelism check block 213 for checking the parallel execution possibility of two instructions, a predecoder 214 for predecoding the instructions output from the parallelism check block 213 to find an instruction length, a register file address, and the like. Pre-decoded instruction queues 215 and 216 for each pipeline that store pre-decoded instructions output from the decoder 214 and wait for actual execution of the instructions.

Next, a decoding operation of removing the critical decoding path in the microprocessor configured as described above will be described.

First, the cache controller 201 receives a cycle instruction fetch address from the address generation unit (not shown) and sends it to the tag / code RAM 202/203 to determine a cache hit / miss. In addition, the instruction code is received from the code RAM 203 at the cache hit and the external memory 10 at the cache miss, and is sequentially stored in the instruction buffer A / B 211/212 of the prefetch unit 210. Next, the parallelism check block 213 checks the parallelism of the instruction codes of the instruction buffers A / B 211/212, and after checking the parallelism, the instruction codes are stored in the instruction predecoder 214. It is passed and partial decoding of two instruction codes is performed. X-pipeline free if parallel processing is possible after decoding the instruction code, e.g. pairs of execution instructions executed in independent integer arithmetic units, or pairs of instructions executed in integer arithmetic units and floating point arithmetic units respectively. Both instruction codes are stored simultaneously in the decoded instruction queue 215 and the Y pipeline predecoded instruction queue 216. In the case of instruction pairs having dependencies, they are sequentially stored in the X-pipelined decoded instruction queue 215 having high priority, so that instructions can be processed without executing a resource conflict when executed in the execution unit 240. have.

Next, the predecoded instructions from the prefetch unit 210 are input to the corresponding pipeline instruction queues 221 and 222 of the instruction queue unit 220 and from the instruction queues 221 and 222 in the decoder unit 230. After performing the remaining decoding on the input instruction, the control unit and the operand are output to the execution unit 240 and the register block. The integer arithmetic unit A 241 of the execution unit 240 executes an instruction from the decoding result output from the X pipeline post decoder 231 and stores the result in the register file 252 or the data cache 251. Finish executing the command. The integer arithmetic unit B 242 or the floating point arithmetic unit 243 of the execution unit 240 executes an instruction from the decoding result output from the y pipeline post decoder 232 and returns the result to the register file 252 or the data. The execution of another instruction is completed by storing in the cache 251.

Accordingly, the instruction decoding operation of the present invention as described above uses the instruction prefetch method to perform the parallel execution check in the superscalar structure and the decoding operation for the instruction size, register file address, etc. in advance in the instruction prefetch cycle. Eliminates critical paths in decoding operations by relieving the workload of performing at the decoding stage.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the prefetch unit is newly configured to satisfy the high instruction request bandwidth of the superscalar structure, and whether the parallel execution of consecutive instructions and the predecoding operation for the instructions are performed in the instruction fetch cycle. It is effective to remove the critical decoding path from the operating superscalar microprocessor to enable stable high speed operation.

Claims (2)

In response to the cache hit / miss signal output from the cache unit, a parallel command is executed in each pipeline by receiving a command line output from the cache unit when the cache hit is performed, and a command line input by accessing from an external memory when the cache miss occurs. A prefetch unit that checks feasibility and performs predecoding for the instruction; An instruction queue unit configured to store an instruction to be executed currently output from the prefetch unit; And Decoder unit for finally decoding the command output for each pipeline from the command queue unit Instruction decoding apparatus comprising a. The method of claim 1, The prefetch unit, A plurality of instruction storage means for alternately storing instructions for the instruction line for each pipeline; Parallelism checking means for checking the parallel execution possibility of the instructions outputted from the instruction storing means; A predecoder for precoding an instruction output from the parallelism checking means; And A plurality of predecoded instruction storage means for storing the pre-decoded instructions output from the predecoder for each pipeline Instruction decoding apparatus comprising a.