KR20000009812A - Digital-analogue converter - Google Patents

Abstract

PURPOSE: A digital-analogue converter is provide to improve a operating speed and a performance. CONSTITUTION: The digital-analogue converter comprises a first terminal and a second terminal, a plurality of a first resistors and a second resistors, a plurality of capacitors(110), a selective control circuit(120) and a output circuit(130). A reference voltage(101) is applied to the first terminal. A plurality of the first resistors are connected in series between the first terminal and ground, and a plurality of the second resistors are connected between ground and the contact point of the first resistors including the first terminal. An electric charge corresponding to digital signal is transmitted to the second terminal. One end of the capacitors is connected in common with the second terminal. The selective control circuit is selectively connected with the contact point of the first resistors and the capacitors in response to the digital signal. The output circuit outputs a quantity of electric charge charged in the capacitor by the selective control circuit to analogue signal corresponding to the digital signal. The first resistors and the second resistors is arranged in the ratio of 1 to 2.

Description

DIGITAL TO ANALOG CONVERTER

The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having high performance.

Digital-to-analog converters have been implemented as circuits operating at low power. Among them, the R-2R ladder type digital-to-analog converter has been widely used. The digital-to-analog converter has the advantage that the difference between the resistors is small.

1 relates to a digital-to-analog converter of a general R-2R ladder method.

The R-2R ladder-type digital-to-analog converter includes 2R and R resistors as the name implies, and a switch S1 connected to the negative input terminal of the operational amplifier 10 and a switch S2 connected to ground are connected to the 2R. do. However, in the digital-to-analog converter as described above, since the current flows through the switches S1 and S2 from the connection point of the resistors, the switch-on resistance affects the output Vout. In the R-2R ladder, in the ideal case, the final resistance is 2R∥2R in parallel, so that R should be obtained. However, 2R (2R + Δ), that is, R + Δ is obtained by the switch on resistance. Δ is an error term. The error limit continues to accumulate in the resistors, leading to performance degradation beyond the acceptable range of output.

In the R-2R ladder method, the ratio of the resistance must be maintained at 1: 2 to obtain an accurate output value, and the R-2R resistance is not matched by the on resistance of the switches. As a result, it cannot be used as a digital-to-analog converter for 256 steps or more than 8 bits by not connecting resistors in multiple stages.

In addition, in order to minimize mismatching of the R-2R resistance caused by the switch-on resistor, the value of the R-2R resistance is greater than that of the switching-on resistor. As a result, the switch-on resistance is very small compared to the total resistance value and can be ignored. However, when the values of the resistors R and 2R are increased for the switch-on resistance, a parasitic capacitor in the switch and a time constant caused by the resistance may increase, resulting in a decrease in operating speed.

It is an object of the present invention to provide a digital-to-analog converter capable of high performance and speed improvement.

1 is a circuit diagram of a typical R-2R ladder digital-to-analog converter;

2A is a circuit diagram of a charge-sum circuit using capacitors;

FIG. 2B is an operation timing diagram of a signal for controlling the switches of FIG. 2A and FIG.

3 is a circuit diagram of a digital-to-analog converter according to the present invention.

* Explanation of symbols on main parts of the drawings

100: R-2R ladder 110: capacitor array

120: selection circuit 130: output circuit

(Configuration)

According to one aspect of the present invention, a converter for converting a digital signal into an analog signal includes a first terminal to which a reference voltage is applied, and a plurality of first resistors connected in series between the first terminal and ground. A plurality of second resistors each connected between a connection point of the first resistors and the ground, including the first terminal, a second terminal through which charge corresponding to the digital signal is transferred, and one end of the second terminal; A plurality of capacitors connected in common, a selection control circuit selectively connecting the connection points of the first resistors and the capacitors in response to the digital signal, and an amount of charge charged in the capacitors according to the selection control circuit corresponding to the digital signal An output circuit for outputting an analog signal, the first and second resistors having a ratio of 1: 2 It is.

In a preferred embodiment, the selection control circuit comprises first switches, a second level digital signal connected between the respective capacitors and a connection point of the first and second resistors in response to a first level digital signal. And in response, second switches connected between the respective capacitors and ground.

In an exemplary embodiment, the output circuit may include a negative input terminal connected to the second terminal, a positive input terminal connected to the ground, an output terminal outputting the analog signal, a switch connected between the negative input terminal and an output terminal, and the It includes a switch connected in parallel at both ends.

In a preferred embodiment, the first switches connect a capacitor to the connection point of the resistors and the second switches connect the capacitor to ground.

Such an arrangement results in a digital-to-analog converter implementation with high resolution performance.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 2 and 3 according to a preferred embodiment of the present invention.

2A is a circuit diagram illustrating a configuration of a charge-sum circuit using a capacitor.

Referring to FIG. 2A, a charge-summing circuit may include capacitors C1, C2, and one end of which is commonly connected to an operational amplifier 20 having a positive / negative input terminal and an output terminal. ..., Cn) Switching pairs S3 and S4 for connecting the capacitors to an input terminal or ground. In addition, a switch S3 'and a capacitor Cf connected in parallel between the negative input terminal and the output terminal of the operational amplifier 20 are included.

The operation of the digital-to-analog converter having the configuration as described above will be described in detail.

First assume that only one capacitor C1 and a pair of switches S3 and S4 are connected to the operational amplifier 20 as a digital-to-analog converter. At this time, the signals ψ1 and ψ2 applied to the switch pairs S3 and S4 have inverted levels as shown in FIG. 2B.

In the rising period of the signal ψ1 of the signals ψ1 and ψ2, the switch S3 is turned on to connect the input terminal and the capacitor C1. As a result, the charge amount as shown in the following equation is charged to the capacitor C1.

Q1 = C1 (V _IN1 -V1)

V1 is the voltage level of node (1). Next, in the rising period of the signal, the switch S4 is turned on to ground the capacitor C1. As a result, the amount of charge charged in the capacitor is transferred to the output terminal through the capacitor, which is expressed as follows.

The digital-to-analog converter is a case where only one capacitor is connected to one input signal. In addition, when a plurality of capacitors for a plurality of inputs (V _IN1 , ..., V _{IN (n)} ) is configured as shown in Figure 2, the output is obtained by the following equation.

Where C1 = C2 =... = Cn

As can be seen from the above equation, the analog output for the digital signal is obtained by the ratio of the capacitors by adding the input voltages (V _IN1 , ..., V _{IN (n)} ). Whether to add the plurality of input voltages is determined by a digital signal that controls on / off of the switching pairs S3 and S4.

3 is a circuit diagram showing in detail the configuration of the digital-to-analog converter according to the present invention, and has a configuration in which the circuit of FIG. 2 is connected to the R-2R ladder.

Referring to FIG. 3, the digital-analog converter includes an R-2R ladder 100, a capacitor array 110, a selection control circuit 120, and an output circuit 130. The R-2R ladder 100 includes a first group of resistors R1, R2, ..., Rn, 2R and a series of resistors R1 of the first group connected in series from the reference voltage Vref 101 to ground. And a second group of resistors 2R connected between the nodes N2, ..., N (n + 1), which are the connection points of R2, ..., Rn, 2R, and ground, respectively. The resistors R1, R2, ..., Rn, 2R of the first group have the same resistance value, and resistors R1, R2, ..., Rn connected from the reference voltage 101 and a resistor connected to the ground. (2R). The second group of resistors 2R have a resistance value twice that of the resistors R1, R2,..., Rn.

The capacitor array 110 is composed of capacitors C1, C2, ..., Cn having one end connected in common to the node 102 and having a parallel arrangement. The selection control circuit 120 includes switch pairs S11 and S12 having one end connected in common to the other end of each capacitor. The switch pairs S11 and S12 are nodes in which the other end of the capacitors and the resistors R1, R2, ..., Rn of the first group and the resistors 2R of the second group are connected in response to a digital signal. And a first switch S11 connected respectively to (N2, N3,, N (n + 1)) and a second switch S12 connected between the other end of each capacitor and ground.

The output circuit 130 is composed of an operational amplifier 30, a switch S11 'and a capacitor Cf. The operational amplifier 30 has a negative input terminal corresponding to the node 102, a positive input terminal grounded, and an output terminal 103 for outputting an analog signal Vout. The switch S11 is connected between the negative input terminal and the output terminal 103 of the operational amplifier 30, and the capacitor Cf is connected in parallel with the switch S11 '.

Hereinafter, the operation of the digital-to-analog converter according to the present invention will be described in detail.

In FIG. 1, as current flows through the resistors to the pairs of switches S1 and S2, errors due to the switch on resistance are accumulated and reflected to the output. However, in the present invention, only the resistors R1, R2, ..., Rn, 2R are connected to the R-2R ladder, and the switches (for the nodes N2, N3,, N (n + 1)) to which they are interconnected. As the capacitors C1, C2, ..., Cn are connected through S11 and S12, the influence of the switch on resistance may be reduced.

Referring to FIG. 3, the voltages of the nodes corresponding to both ends of the resistors R1, Rn except for the node N1 are from node N (n + 1) to Vref / 2, Vref / to node N2. 2 ² , Vref / 2 ³ ,. , Vref / 2 ⁿ . The voltages are charged with capacitors according to switch pairs S11 and S12 that are turned on and off in accordance with the digital signal. As a result, as shown in FIG. 2, the output voltage is determined by the ratio of the capacitor and the sum of the voltages of the nodes N2, N3,, N (n + 1) connected to the capacitors C1, C2,, and Cn. (Vout) is obtained.

In the present invention, the analog signal is output only by the voltage component, whereas the analog signal for the digital signal is output as the current (io) component in FIG. Therefore, the on-resistance of the switch can be ignored, and there is no error term for the on-resistance, thereby enabling the implementation of a digital-to-analog converter for high resolution.

In the past, the resistance value of the R-2R ladder was large enough to ignore the switch on resistance, which caused the time constant to be large, thereby reducing the speed. However, in the present invention, since there is no switch on resistance, the current can be increased by setting the resistance value of the R-2R ladder small. In this way, the increase in current results in a speedup of the digital-to-analog converter.

According to the present invention, the error of the digital-to-analog converter can be minimized, and the performance is improved.

Claims (4)

In the converter for converting a digital signal into an analog signal, A first terminal to which a reference voltage is applied; A plurality of first resistors connected in series between the first terminal and ground; A plurality of second resistors each connected between a connection point of the first resistors and the ground including the first terminal; A second terminal through which a charge corresponding to the digital signal is transferred; A plurality of capacitors having one end connected in common to the second terminal; A selection control circuit for selectively connecting the connection points of the first resistors and the capacitors in response to the digital signal; And An output circuit for outputting the charge amount charged to the capacitors according to the selection control circuit as an analog signal corresponding to the digital signal, And the first and second resistors are arranged with a ratio of 1: 2. The method of claim 1, The selection control circuit, First switches connected between the respective capacitors and a connection point of the first and second resistors in response to a first level of a digital signal; And second switches connected between the respective capacitors and ground in response to a second level of the digital signal. The method of claim 1, The output circuit, A sub-input terminal connected to the second terminal; A positive input terminal connected to the ground; An output terminal for outputting the analog signal; A switch connected between the negative input terminal and the output terminal; And And a switch connected in parallel to both ends of said switch. The method of claim 1, The first switches connect a capacitor to the connection point of the resistors; And the second switches connect the capacitor to ground.