KR20000009293A - Power factor improving circuit of ac input terminal for power supply - Google Patents

Abstract

PURPOSE: A power factor improving circuit is provided to improve power factor of an AC input terminal for a power supply, but yet to prevent an additional power loss by forming the circuit using only a reactor and a capacitor. CONSTITUTION: The power factor improving circuit has input terminals(L11, L12)) for inputting AC voltage and a reactor(USR) for outputting ground current by grounding current generated when the AC voltage is inputted through the input terminal(L11). The AC voltage transmitted from the reactor(USR) is rectified by a bridge diode(BD), then outputted as a DC voltage. The DC voltage is smoothed by smoothing capacitors(C1, C2) coupled to the bridge diode(BD) in parallel. The ground current is compensated by a compensating capacitor(C3) such that a phase of the ground current becomes the same as the DC voltage when the ground current flows along the smoothing capacitors(C1, C2). The compensating capacitor(C3) is disposed between the input terminals(L11, L12) and the smoothing capacitors(C1, C2).

Description

Power factor improvement circuit of AC input terminal of power supply

The present invention relates to a power supply, and more particularly to a circuit for improving the power factor of the AC input stage.

In general, the power supply unit rectifies a direct current (DC) voltage stabilized by full-wave rectification by using an AC (Alternative Current) voltage of 110V / 220V by using a bridge diode, and smoothing by using a capacitor. Refers to the output device. Such power supplies are indispensably used for various electrical, electronic and communication devices. At this time, the output DC voltage is boosted or stepped down depending on which device the power supply is used for. And in order for such a power supply to supply high quality power, a circuit for improving the power factor of the entire power supply is also indispensable on the AC input side.

A typical form of the power factor correction circuit of a power supply is realized by inserting an unsaturated reactor USR in series with an AC input terminal as shown in FIG. However, the method of improving the power factor of the power supply using an unsaturated reactor has a disadvantage in that the power factor of the power supply is generally improved by only about 75% as is well known to those skilled in the art. For reference, when no unsaturated reactor is used, the power factor of the power supply is only about 60%.

In order to solve this disadvantage, recently, most of the art uses an integrated circuit (IC) having a function of a power factor controller (PFC) as shown in FIG. 2. For example, the model "ML4812" manufactured and sold by Micor Linear is an IC having a function of a power factor control circuit.

However, since the PFC is a semiconductor device using a 5V or 12V power supply, it can be usefully used in a device supplying a small capacity of 300 to 500W, but is not suitable in a device supplying a medium and high capacity power of 500W or more. There are disadvantages. In addition, the PFC IC is weak to electrical shock, so it is easily damaged when an electrical shock such as a surge occurs at the AC input terminal.

As described above, the power factor improvement circuit according to the related art has a slight degree of improvement in power factor, and is not suitable for applying to medium and high capacity power supplies, and is also susceptible to electric shock. These disadvantages result in the power supply not providing good quality power.

It is therefore an object of the present invention to provide a circuit that enables the power supply to supply high quality power with improved power factor.

Another object of the present invention is to provide a circuit that enables the power supply device to supply power of medium and high capacity while having an improved power factor.

Another object of the present invention is to provide a circuit that is resistant to electric shock and can improve the power factor of a power supply.

The power factor improvement circuit of the power supply apparatus according to the first aspect of the present invention for achieving these objects is an input terminal for inputting an AC voltage, and is inserted in series with the input terminal and connected to the AC terminal. A reactor for grounding a current flowing as it is applied and outputting a ground current, a bridge diode for full-wave rectifying the AC voltage output through the reactor, and outputting a DC voltage, and the full-wave rectification is connected in parallel with the bridge diode. A smoothing capacitor for smoothing the output DC voltage, an output terminal for outputting the DC voltage smoothed and output by the smoothing capacitor to an external load, and connected between the input terminal and the smoothing capacitor, The liquid flows by advancing the current flowing through the capacitor to provide the smoothing capacitor. The ground when the current output by the flow through the smoothing capacitor so that the phase of the direct-current voltage is in phase with the phase of the current to be outputted to the output terminal is made to include at least a compensation capacitor for compensating for the earth current.

The power factor improving circuit of the power supply apparatus according to the second aspect of the present invention comprises: an input terminal for inputting an AC voltage through the first input terminal and the second input terminal; A reactor, one side of which is connected to the first input terminal in series and connected to the first input terminal, for outputting ground current by grounding a current flowing as the AC voltage is applied to the input terminal; An alternating current input through the reactor and the second input terminal, comprising a first input terminal connected to the other side of the reactor, a second input terminal connected to the second input terminal, and a first output terminal and a second output terminal; A bridge diode for full-wave rectifying the voltage and outputting the full-wave rectified voltage; A first capacitor and a second capacitor of a series connection connected in parallel between the first output terminal and the second output terminal of the bridge diode, and outputting a smoothed second DC voltage by smoothing the first DC voltage. A smoothing capacitor; A first output terminal connected to the first output terminal of the bridge diode, a second output terminal connected to the second output terminal of the bridge diode, and an output terminal for outputting the second DC voltage to an external load; ; A connection between a second input terminal of the input terminal and a connection point of the first capacitor and the second capacitor, each including at least a plurality of compensating capacitors of a parallel connection having a capacitance value proportional to the total capacity of the load; Each of the compensating capacitors advances the current flowing through the input terminal to provide the smoothing capacitor so that the ground current output after being grounded by the reactor flows through the smoothing capacitor. The ground current is compensated to be in phase with the phase of the DC voltage output to the output terminal.

1 and 2 are views showing the configuration of a power factor correction circuit according to the prior art.

3 is a diagram showing the configuration of a power factor correction circuit according to a first embodiment of the present invention.

4 is a diagram illustrating a configuration of a power factor improving circuit according to a second embodiment of the present invention.

5 is a diagram showing a voltage versus current waveform of the power factor correction circuit shown in FIG.

6 is a view showing a voltage versus power factor correction current waveform of the power factor correction circuit according to the present invention.

Figure 7 shows the voltage versus output current waveform of the power factor correction circuit according to the present invention.

Fig. 8A is a waveform diagram showing the relationship between load capacity and output current according to the first embodiment of the present invention.

8B is a waveform diagram showing a relationship between load capacity and output current according to a second embodiment of the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

3 is a diagram showing the configuration of a power factor correction circuit according to a first embodiment of the present invention, which includes an input stage, an unsaturated reactor USR, a bridge diode BD, a smoothing capacitor C1, C2, and an output stage. At least inclusive. These components are the general components of the power supply as shown in FIG. 1, in particular the unsaturated reactor USR is a component provided for the operation of the power factor correction. In addition, the power factor correction circuit according to the first embodiment of the present invention further includes a capacitor C3 for the operation of the power factor correction according to the present invention.

Referring to FIG. 3, an input terminal includes a first input terminal L11 and a second input terminal L12, and an AC voltage is input to the first input terminal L11 and the second input terminal L12. One side of the unsaturated reactor USR is connected to the first input terminal L11, and the other side of the unsaturated reactor USR is connected to the connection point of the diodes D1 and D3, which are the first input terminals of the bridge diode BD. Since the unsaturated reactor USR has an inductive component, the unsaturated reactor USR serves to output a ground current by grounding a current flowing as an AC voltage is applied to the input terminal. The second input terminal L12 is connected to the connection point of the diodes D2 and D4, which are the second input terminals of the bridge diode BD. The reactor USR may be connected to the first input terminal L11, may be connected to the second input terminal L12, or may be connected to both the first input terminal L11 and the second input terminal L12.

The bridge diode BD including the diodes D1 to D4 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The anode terminal of the diode D1 and the cathode terminal of the diode D3 are connected to the first input terminal. The anode terminal of diode D2 and the cathode terminal of diode D3 are connected to the second input terminal. The cathode terminals of the diodes D1 and D2 are connected to the first output terminal, and the anode terminals of the diodes D3 and D4 are connected to the second output terminal. The bridge diode BD performs full-wave rectification of the AC voltage applied through the unsaturated reactor USR and the second input terminal L 12 to output the full-wave rectified DC voltage.

The first and second output terminals of the bridge diode BD are connected to the first output terminal L21 and the second output terminal L22 of the output terminal, respectively. Accordingly, the full-wave rectified DC voltage by the bridge diode BD is output to the load connected to the outside through the first output terminal L21 and L22 of the output terminal. At this time, capacitors C1 and C2 in series connected in parallel to the bridge diode BD are connected between the first output terminals L21 and L22 of the output terminal. These capacitors C1 and C2 act as smoothing capacitors that smooth the DC voltage to be supplied to the load through the output stage after being full-wave rectified by the bridge diode BD. Therefore, after full-wave rectification by the bridge diode BD, the DC voltage smoothed by the smoothing capacitors C1 and C2 is supplied to the load connected to the outside through the output terminal.

In fact, it is common to use a boost converter or step-down converter instead of a load connected directly to the output terminal. This is because the step-up or step-down conversion circuit boosts or step-downs the DC voltage smoothed by the smoothing capacitors C1 and C2 to a DC voltage suitable for use in the load, and then supplies the converted DC voltage to the load. Because it is possible. As a boost or step-down conversion circuit, a transformer is usually used. Operation of the boost or step-down conversion circuit is not the main field of interest of the present invention, and a description thereof will be omitted. In addition, in describing the present invention, it should be noted that the DC voltage smoothed by the smoothing capacitors C1 and C2 is limited to being directly supplied to the load.

Referring back to FIG. 3, it can be seen that the circuit according to the present invention further includes a capacitor C3 for the operation of the power factor improvement according to the present invention, in addition to the components described above. The capacitor C3 is connected between the second input terminal L12 of the input terminal and the connection point of the smoothing capacitors C1 and C2. This capacitor C3 is provided with a circuit according to the invention for improving the power factor by 99%. In other words, capacitor C3 functions as a power factor correction capacitor that serves as a power factor correction. In contrast, when only the unsaturated reactor USR is provided at the input stage, the power factor is usually improved by only about 75%. However, when the capacitor C3 is provided together with the unsaturated reactor USR, the power factor is improved to about 99%. It is possible. It will be apparent from the following description that the power factor can be further improved when the capacitor C3 is provided.

FIG. 5 is a diagram illustrating waveforms of an input side voltage versus current in a power factor correction circuit according to the related art configured as shown in FIG. 1. As can be seen in Figure 5 it can be seen that the input voltage V1 and the current I1 is out of phase by "Θ". That is, the input current I1 has a phase later than "Θ" than the phase of the voltage V1. The phase difference between the voltage and the current affects the output stage as it is. This phase difference can be minimized by adjusting the capacity of the reactor USR, but it is very difficult to increase the power factor by 78% due to its limitation.

Referring to FIG. 5, since the current I1 has a phase difference of "Θ" with respect to the voltage V1, it can be seen that there is a space between the voltage V1 and the current I1 which is lagging with respect to the voltage V1. . That is, as indicated by the hatched line in FIG. 5, it can be seen that there is a space in the initial portion of the rising of the voltage V1. This gap can be resolved by supplementing the leading current corresponding to the phase difference of the current I1 to the part where the ground current flows. To this end, in the present invention, the fast current is supplied to the ground current IL flowing through the output terminal to the load side.

The inventors of the present application have focused on the fact that the current is positive when a voltage is applied to a capacitive element such as a capacitor, and the current flowing through the capacitive element is positive relative to the applied voltage. In accordance with this concept, the inventor of the present application connected the capacitor C3 between the second input terminal L12 of the input terminal and the connection point of the smoothing capacitors C1 and C2. When the voltage from the input terminal L12 is applied to the capacitor C3, as shown in FIG. Since the forward current IF is applied to the connection point of the smoothing capacitors C1 and C2, the smoothing capacitors C1 and C2, which previously flowed the ground current, are supplemented with the forward current IF. It will be in phase with. That is, since the current of the waveform as shown in FIGS. 5 and 6 is simultaneously present in the load stage, as a result, as shown in FIG. 7, the current IL with almost no phase difference with respect to the voltage V1 flows to the load stage. . As described above, the current flowing through the capacitor C3 is a current almost in phase with respect to the voltage output to the load terminal, and as a result, a power factor correction capacitor for compensating the power factor.

The power factor correction current IF flowing through the input current I1 flowing through the input of the power supply and the capacitor C3 flows in proportion to the deceleration of the current IL flowing through the output (load) of the power supply. The input current I1 flows less when the discharge current of the charging voltage of the smoothing capacitors C1 and C2 is small due to the low load current IL, and increases when the discharge amount of C1 and C2 increases due to the increase in the load current IL. However, the maximum current value of the power factor correction current IF is proportional to the capacity of the power factor correction capacitor C3.

Referring back to FIG. 3, when a positive AC voltage is applied to the input terminal L11 and a negative AC voltage is applied to the input terminal L12, the current IF for power factor correction is input terminal L11 → reactor USR → diode D1. → capacitor C1 → capacitor C3 → flows through input terminal L12. On the other hand, when the AC voltage of (-) is applied to the input terminal L11 and the (+) AC voltage is applied to the input terminal L11, the current IF for power factor correction is input terminal L12 → capacitor C3 → capacitor C2 → diode D3 → reactor USR → flows through input terminal L11. Thus, the power factor correction current IF is proportionally added to or subtracted from the change in the load current IL.

FIG. 8A illustrates the case where the power factor correction circuit according to the present invention is configured as shown in FIG. 3, that is, when one power factor correction capacitor C3 is connected between the input terminal L12 and the connection point of the smoothing capacitors C1 and C2. The figure shows the effect. For example, when the capacitance value of the power factor correction capacitor C3 is set to have a maximum power factor when the load capacity is 50% and the power factor is compensated from the load capacity when 30%, the current IL on the load side is shown in FIG. 8A. As described above, when the load capacity is 30% (IL = I1), the power factor is compensated to be compensated to show the maximum power factor when the load capacity is 50% (IL = I2).

On the other hand, when a plurality of power factor correction capacitors C3 and C4 are inserted between the input terminal L12 and the connection point of the smoothing capacitors C1 and C2, the power factor of the power supply can be maintained at 98% or more regardless of the load capacity. . This is because the power factor of the power supply which properly sets the capacitance values of the smoothing capacitors C1 and C2 in proportion to the load capacity can be maintained above a certain value. The circuit according to this embodiment is configured as shown in FIG.

Referring to Fig. 4, the power factor correction capacitors C3 and C4 connected in parallel are connected between the input terminal L12 and the connection point of the smoothing capacitors C1 and C2. The switch SW1 is connected between the capacitor C3 and the connection point of the capacitors C1, C2, and the switch SW2 is connected between the capacitor C4 and the connection point of the capacitors C1, C2. More specifically, one side of the capacitor C3 is connected to the input terminal L12, the other side is connected to one side of the switch SW1, and the other side of the switch SW1 is connected between the connection points of the capacitors C1 and C2. One side of the capacitor C4 is connected to the input terminal L12, the other side is connected to one side of the switch SW2, and the other side of the switch SW2 is connected between the connection points of the capacitors C1 and C2. The switches SW1 and SW2 are implemented as static switches such as triacs, and the switches SW1 and SW2 are controlled by the current detection circuit 20. The current detection circuit 20 supplies current flowing through the shunt resistor R connected between the second input terminal (one side of the smoothing capacitor C2) of the bridge diode BD and the second output terminal L22-the current flowing through the output terminal (load stage). And switches SW1 and SW2 are controlled according to the detection result.

For example, if the first switch SW1 is controlled to be switched on when the total load capacity is 30%, and then the second switch SW2 is also controlled to be switched on when the load capacity is 70%, as shown in FIG. 8B. As described above, the load current IL can be maintained at a constant size. Here, the first switch SW1 is switched on when the total load capacity is 30%, and the second switch SW2 is also switched on together with the first switch SW1 when the total load capacity is 70%. It means that the capacitance value of C4 is set to be about 3: 4. This is because, when the load current flows as much as the total load capacity, the power factor correction current flows by the amount corresponding thereto, so that the power factor may be compensated for the amount of current flowing therein. For example, the capacitance value of the capacitor C3 can be set to be 30 [kV], and the capacitance value of the capacitor C4 can be set to be 40 [kV].

FIG. 8B shows the load capacity versus the load current when the power factor correction capacitors C3 and C4 have a capacitance value of 3: 4 and a maximum power factor is shown when the load capacity is 50% or 100% in FIG. 4. Figure showing the waveforms of

Referring to FIG. 8B, all switches SW1 and SW2 are switched off until the load capacity reaches 30% (before T1), and the switch SW1 switches when the load capacity reaches 30% (from T1 to T2). When the load capacity is 70% (after T2), all the switches SW1 and SW2 are switched on. By the switching operation of the switches SW1 and SW2, the discharge amount of the charging voltage by the smoothing capacitors C1 and C2 increases, and as a result, the current amount of the load current IL increases. As described above, the increase in the amount of current of the load current IL corresponding to the crushing capacity results in improving the power factor. This operation is performed by the current detection circuit 20 detecting the current flowing through the resistor R as described above and switching control of the switches SW1 and SW2 using the detection result.

Referring again to FIG. 4, when a positive AC voltage is applied to the input terminal L11 and a negative AC voltage is applied to the input terminal L12, the current IF for power factor correction is input terminal L11 → reactor USR → diode D1. → capacitor C1 → switch SW1 (or switches SW1, SW2) → capacitor C3 (or capacitors C3, C4) → flows through input terminal L12. On the other hand, when an AC voltage of (-) is applied to the input terminal L11 and an AC voltage of (+) is applied to the input terminal L11, the current IF for power factor correction is input terminal L12 → capacitor C3 (or capacitors C3, C4) → Flow through switch SW1 (or switch SW1, SW2) → capacitor C2 → diode D3 → reactor USR → input terminal L11. Thus, the power factor correction current IF is proportionally added to or subtracted from the change in the load current IL.

<Table 1> and <Table 2>, respectively, show the power factor in the power supply device shown in FIGS. The result of having measured the effect of improvement is shown. This measurement result shows the result measured by the inventor of the present application using a clamp on power high tester (CLAMP ON POWER HI-TESTER).

Input voltage [V] Input current [A] Electric power [VA] Input power [WATT] Power factor (PF) 220.6V / 60Hz 16.92A 3.734KVA 2.851KW 0.764

Input voltage [V] Input current [A] Electric power [VA] Input power [WATT] Power factor (PF) 221.7 V / 60 Hz 13.31A 2.952KVA 2.899KW 0.982

As shown in <Table 1> and <Table 2>, the power factor improvement circuit according to the related art can improve the power factor up to about 76% under almost the same conditions, but the power factor improvement circuit according to the present invention is about 98%. It can be seen that it is possible to improve the power factor to a degree.

As described above, the present invention simply provides a power factor correction circuit configured using only a reactor and a capacitor. These components are highly reliable because of the low risk of failure and have a strong advantage against electrical shock (surge) from the input stage. In addition, the power factor correction circuit of the present invention is applicable to both low and large capacity, there is an advantage that there is no additional power loss due to the power factor correction circuit. As described above, since the power factor improvement circuit according to the present invention has a power factor improvement characteristic which is much improved than the conventional methods, there is an energy efficiency increase and an import replacement effect of the PFC IC.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (10)

In the power factor correction circuit of the power supply, An input terminal for inputting an AC voltage, A reactor inserted in series with the input terminal and connected to the input terminal and outputting a ground current by grounding a current flowing as the AC voltage is applied to the input terminal; A bridge diode for full-wave rectifying the AC voltage output through the reactor and outputting a DC voltage; A smoothing capacitor connected in parallel with the bridge diode to smoothly output the full-wave rectified DC voltage; An output terminal for outputting a DC voltage smoothed and output by the smoothing capacitor to an external load; The phase of the current is connected between the input terminal and the smoothing capacitor and advances the current flowing through the input terminal to provide the smoothing capacitor so that the ground current output by the reactor flows through the smoothing capacitor. And at least a compensation capacitor for compensating the ground current to be in phase with the phase of the DC voltage output to the output terminal. The method of claim 1, wherein the input terminal comprises a first input terminal and a second input terminal, The first input terminal is connected to one side of the reactor, the other side of the reactor is connected to one side of the bridge diode, And the second input terminal is connected to the other side of the bridge diode and one side of the ground current compensating capacitor. The method of claim 2, wherein the output terminal comprises a first output terminal and a second output terminal, The smoothing capacitor of the first capacitor and the second capacitor connected in series is connected in parallel between the first output terminal and the second output terminal, And the other side of the compensation capacitor is connected to a connection point of the first capacitor and the second capacitor. In the power factor correction circuit of the power supply: An input terminal comprising an first input terminal and a second input terminal for inputting an AC voltage through the input terminals; A reactor, one side of which is connected to the first input terminal in series and connected to the first input terminal, for outputting ground current by grounding a current flowing as the AC voltage is applied to the input terminal; An alternating current input through the reactor and the second input terminal, comprising a first input terminal connected to the other side of the reactor, a second input terminal connected to the second input terminal, and a first output terminal and a second output terminal; A bridge diode for full-wave rectifying the voltage and outputting the full-wave rectified voltage; A first capacitor and a second capacitor of a series connection connected in parallel between the first output terminal and the second output terminal of the bridge diode, and outputting a smoothed second DC voltage by smoothing the first DC voltage. A smoothing capacitor; A first output terminal connected to the first output terminal of the bridge diode, a second output terminal connected to the second output terminal of the bridge diode, and an output terminal for outputting the second DC voltage to an external load; ; A connection between a second input terminal of the input terminal and a connection point of the first capacitor and the second capacitor, each including at least a plurality of compensating capacitors of a parallel connection having a capacitance value proportional to the total capacity of the load; Done, The compensating capacitors advance current flowing through the input terminal to provide the smoothing capacitor so that when the ground current outputted by the reactor flows through the smoothing capacitor, the phase of the current flows to the output terminal. The power factor correction circuit, characterized in that for compensating the ground current to be in phase with the output DC voltage. 5. The power factor correction circuit according to claim 4, further comprising a resistor connected between the second output terminal of the output terminal and one side of the smoothing capacitor. The power factor correction circuit of claim 5, further comprising a plurality of switching elements connected between the connection point of the first capacitor and the second capacitor and the compensation capacitors. The power factor correction circuit of claim 6, further comprising a current detection circuit configured to detect an amount of current flowing through the resistor, and to control switching of the respective switching elements according to the detection result. The power factor correction circuit of claim 7, wherein each switching element is implemented as a triac that is controlled to be controlled by the current detection circuit. The method of claim 8, wherein the compensation capacitor is composed of two third capacitor and the fourth capacitor, the switching element is composed of two first switching element and the second switching element corresponding to the compensation capacitor. Power factor improvement circuit. 10. The apparatus of claim 9, wherein the current detection circuit switches and controls the first switching element when a current corresponding to 30% of the total capacity of the load flows through the resistor, and corresponds to 70% of the total capacity of the load. And a switching control of said first switching element and switching control of said second switching element when a current flows.