KR20000008964A - Method for manufacturing printed circuit board - Google Patents

Abstract

PURPOSE: A method for manufacturing a printed circuit board(PCB) adjusts a clearance size formed in a via hole. CONSTITUTION: The method prepares a substrate which forms a clearance metal layer having a selective etching ability on a specific metal layer of a specific unit substrate forming a clearance, penetrates the clearance metal layer, forms a via hole for electrically connecting the metal layer, selectively etches the clearance metal layer about the metal layer, forms a clearance via to an inner wall of the hole, forms a clearance by filling the clearance via with an insulation resin, plates the inner wall of the via hole for electrically insulating the metal layer exposed to the inner wall of the via hole, and forms a plating layer. The clearance electrically insulates between the specific metal layer and the plating layer. Thereby, a clearance size formed in a via hole is easily adjusted.

Description

Method for manufacturing PCB

The present invention relates to a method of manufacturing a printed circuit board, and more particularly, to a method of manufacturing a printed circuit board that can adjust the size of the clearance formed in the via hole.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the important technologies that enables the accomplishment of such a product design goal is a package assembly technology. Accordingly, one of the recently developed packages is a ball grid array (BGA) package. The BGA package has advantages in that the mounting area on the mother board can be reduced and the electrical characteristics are excellent, compared to the conventional plastic package.

Unlike conventional plastic packages, BGA packages use a printed circuit board (PCB) instead of a lead frame. The printed circuit board is advantageous in terms of mounting density on the parent substrate because the printed circuit board can provide the entire surface opposite to the surface where the semiconductor chip is bonded to the area where solder balls can be placed.

On the other hand, the printed circuit board is widely used as various boards of the electronic system (electronic system) and plays an important role in configuring the electrical system with the semiconductor device. On the other hand, integrated circuits, which are rapidly becoming high speed and highly integrated, have increased the number of input / output terminals in the packaging of semiconductor devices, thereby increasing the number of balls of BGA type packages and increasing the number of printed circuit boards used as packaging substrates. The density of circuit wiring continues to increase.

As shown in FIG. 1, a conventional printed circuit board 10 has a structure in which a multilayer metal layer 21 is formed on a substrate body 14, and typically, wiring layers 23, 25, 27, and ground layer 29 are formed. And a unit substrate on which the metal layer 21 including the power layer (not shown) is formed, is laminated. Copper (Cu) is used as a constituent material of the metal layer. In addition, electrical connection between the upper and lower metal layers 21 is made through via holes 12. In the case of forming the via hole 12 which is not connected to the ground layer 29 among the via holes, the via hole 12 is etched by etching the ground layer 29 on which the via hole 12 is to be formed. Larger diameter clearance vias 16 are preformed.

The clearance via 16 is formed two to three times larger than the size a of the hole lands 23a and 27a of the via holes. The reason for this formation is the limitation of the accuracy of the drilling process for drilling the via hole 12 in manufacturing the printed circuit board 10, and the ground layer 29 and the via which are not electrically connected to the via hole 12. This is to ensure a certain degree of insulation resistance reliability between the holes 12. That is, when the via holes 12 are formed through the hole lands 23a and 27a formed in the opposite direction of the upper and lower surfaces of the substrate body 14, the clearance vias may be removed even if the center of the via holes 12 deviates from the reference point to some extent. Since the width 16 is larger than the via hole 12, an insulation resistance can be secured by maintaining a constant distance between the via hole 12 and the ground layer 29. Meanwhile, the clearance via 16 is filled with the material of the substrate body 14 in the manufacturing of the printed circuit board 10. In the description according to the present embodiment, the clearance via 16 is formed in the ground layer 29. Although the structure has been described, clearance vias are formed in the power layer even when a specific via hole is not connected to the power layer. Reference numeral b denotes the size of the clearance 16.

However, since clearance vias 16 should be formed two to three times wider than via lands 23, the gap between via holes 12 becomes narrow, i.e., as shown in FIG. 2, hole lands 23a. , 27a) may be narrowed, resulting in overlapping portions 17 between adjacent clearance vias 16. In particular, printed circuit boards are used in fine pitch PGA BGA package types with narrow spacing between balls. Reference numerals 10a, 10b, and 10c denote unit boards constituting the printed circuit board, and the unit board 10a in the center is the unit board 10a on which the ground layer 49 is formed.

In the portion 17 where the clearance via 16 overlaps, an empty space in which the ground layer 29 does not exist is formed. Therefore, in the portion 17 where the clearance via 16 overlaps, the ground region cannot be formed, and thus the adjacent wiring layer is not formed. The impedance value of deviates from the original value, and a large variation in the impedance value may occur depending on the frequency at which the clearance vias 16 overlap.

In addition, when the clearance via is formed as in the related art, the overlapping frequency of the clearance via in the portion where the via holes are concentrated is expected to increase due to the fine pitch of the wiring of the printed circuit board. In this case, since there is no ground layer in the dense via hole region, the effectiveness of the ground layer is lost.

Accordingly, it is an object of the present invention to provide a method of manufacturing a printed circuit board in which clearance vias may be suppressed from overlapping, and a metal layer spaced apart from a via hole may exist between the via holes.

Another object of the present invention is to provide a method of manufacturing a printed circuit board that can adjust the size of the clearance via.

1 is a cross-sectional view showing a printed circuit board according to the prior art,

2 is a schematic view of a printed circuit board having clearance vias overlapped;

3 is a process flowchart showing an embodiment of a method of manufacturing a printed circuit board according to the present invention;

4 to 13 show the steps of the manufacturing method shown in FIG.

4 to 8 are cross-sectional views illustrating a manufacturing step of a unit substrate on which a clearance metal layer is formed;

9 is a cross-sectional view illustrating a state in which a plurality of unit substrates are stacked;

10 is a cross-sectional view illustrating a step of forming a via hole;

11 is a cross-sectional view showing a step of selectively etching a clearance metal layer to form a clearance via;

12 is a cross-sectional view illustrating a step of forming a clearance by filling an insulating material with an selectively etched portion;

FIG. 13 is a cross-sectional view illustrating plating of an inside of a via hole. FIG.

Description of the main parts of the drawing

30: printed circuit board 32: via hole

34: substrate body 38: plating layer

41 metal layer 43 upper wiring layer

45: internal wiring layer 47: lower wiring layer

49: ground layer 50: clearance metal layer

59: clearance 61: photoresist

In order to achieve the above object, the present invention is a manufacturing method of a printed circuit board having a clearance, (a) a substrate formed by laminating a plurality of unit substrates with a metal layer formed on the substrate body, a specific unit to form a clearance among the unit substrate Preparing a substrate having a clearance metal layer having a selective etching ability with a specific metal layer on the specific metal layer of the substrate; (b) forming a via hole through the clearance metal layer and for electrically connecting the metal layer; (c) selectively etching the clearance metal layer with respect to the metal layer to form a clearance via into the inner wall of the via hole; (d) filling the clearance vias with an insulating resin to form a clearance; And (e) plating the via hole inner wall to form a plating layer to electrically connect the exposed metal layer to the via hole inner wall, wherein the clearance electrically insulates the specific metal layer and the plating layer formed in the via hole. Provided is a method of manufacturing a printed circuit board.

The metal layer according to the present invention includes a circuit wiring layer including an upper wiring layer formed on the substrate body, an internal wiring layer formed inside the substrate body, and a lower wiring layer formed under the substrate body, and a ground layer formed inside the substrate body. It is characterized in that the ground layer is a specific metal layer.

In the manufacturing method according to the present invention, the step of forming a clearance metal layer in step (a) comprises (a1) preparing a unit substrate having a ground layer formed on the substrate body, and (a2) applying a photoresist on the ground layer And developing a photoresist on the ground layer to be formed with a clearance via to form a window, (a3) etching the ground layer exposed to the window to form a groove, and (a4) the ground layer in the groove. Forming a clearance metal layer with selective etching capability and (a5) removing the photoresist.

Step (a4) according to the manufacturing method of the present invention includes the steps of forming an intermediate metal layer of nickel in the groove by an electroless plating method, and forming a clearance metal layer of nickel filling the groove by the electrolytic plating method on the intermediate metal layer. Include.

In step (c) according to the manufacturing method of the present invention, the clearance via is preferably formed inside the clearance metal layer.

The insulating resin of step (d) according to the manufacturing method of the present invention is an epoxy-based plastic resin, and fills the clearance via the plastic resin in a fluid state using a capillary phenomenon. After step (d), it is preferable to proceed with the step of removing the insulating resin formed on the inner wall of the via hole using permanganic acid.

In addition, the metal layer according to the present invention further comprises a power layer, characterized in that the power layer is a specific metal layer formed with a clearance.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a process flowchart showing an embodiment of a method of manufacturing a printed circuit board according to the present invention. 4 to 13 are cross-sectional views showing respective steps of the manufacturing method shown in FIG. 3. An embodiment of a manufacturing method according to the present invention will be described with reference to FIGS. 3 to 13. On the other hand, the same reference numerals throughout the drawings represent the same components.

The manufacturing process of this embodiment starts with the step of forming the unit substrate (30a in FIG. 8). The unit substrate is composed of a substrate body and a metal layer formed on the substrate body, and the metal layer is formed of a wiring layer using a photolithography on a thin metal film thermally compressed on the upper portion of the substrate body. Cu foil is mainly used as the metal thin film, and FR-4 based prepreg that serves as an interlayer insulating layer between the metal layers is used as the material of the substrate body.

4 to 8 illustrate a manufacturing process 71 of the unit substrate 30a in which the ground layer 49 is formed among the unit substrates.

As shown in FIG. 4, in a state in which a semi-finished unit substrate having a ground layer 49 formed on the substrate body 34 is prepared, the ground layer 49 is etched to etch the ground layer 49 to be formed as clearance vias. A photoresist 61 is applied on the upper surface of the photoresist, and the photoresist 61 on the ground layer 49 to be formed as a clearance via is developed to form a window 63.

Next, as shown in FIG. 5, the ground layer 49 exposed on the window 63 is etched to form a groove 48 so that the top surface of the substrate body 34 is exposed. The groove 48 is preferably formed to have an area of about 2 to 3 times the area c of the via land (43a, 47a in FIG. 10).

Next, in order to form the clearance metal layer 50 in the groove 48 formed in the ground layer 49, as shown in FIG. 6, the metal 53 forming the clearance metal layer 50 in the groove 48 is well formed. The intermediate metal layer 51 is formed so as to be possible, and the clearance metal layer 50 is formed by filling the groove 48 with the metal 53 as shown in FIG. 7. On the other hand, as the material of the clearance metal layer 50, it is preferable to use a metal, for example, nickel (Ni), having a high selectivity compared to copper, which is a peripheral wiring layer, in the chemical etching process. Therefore, in the embodiment of the present invention, the intermediate metal layer 51 is formed of nickel (Ni) by the electroless plating method, and the clearance metal layer 50 is formed of nickel (Ni) by the electroplating method.

Next, the photoresist 61 on the ground layer 49 is removed to complete the manufacturing of the unit substrate 30a as shown in FIG. 8.

Meanwhile, in the embodiment of the present invention, the process of forming the clearance metal layer 50 in the ground layer 49 has been described, but the process of forming the clearance metal layer in the power layer is the same as the above-described process.

The unit substrate 30a manufactured by the above-described process and the unit substrate on which the metal layer 41 is formed are laminated to form a substrate on which a multi-layer metal layer 41 in a semi-finished state as shown in FIG. 9 is formed. The substrate is composed of a substrate body 34 and a multilayer metal layer 41. The metal layer 41 is composed of circuit wiring layers 43, 45, and 47 serving as electrical passages, a ground layer 49 forming a ground region, and a power layer (not shown) for supplying power. The circuit wiring layers 43, 45, and 47 are formed of an upper wiring layer 43 on the substrate body 34, an internal wiring layer 45 formed inside the substrate body 34, and a lower wiring layer 47 below the substrate body. do. The ground layer 49 is formed inside the substrate body 34. In addition, the upper wiring layer 43 and the lower wiring layer 47 are formed in the disk-shaped hole lands 43a and 47a through which via holes can be symmetrical to each other.

Next, as shown in FIG. 10, the upper and lower wiring layers 43 are drilled to form a via hole 32 that electrically connects the upper wiring layer 43, the inner wiring layer 45, and the lower wiring layer 47. Holes 47a and 47a which are symmetrical to each other, 47. The inner wiring layer 45 formed inside the substrate body 34 is exposed on the inner wall of the via hole 32. Since the via hole 32 is formed through the clearance metal layer 50 of the ground layer, the clearance metal layer 50 is also exposed to the inner wall of the via hole 32.

Meanwhile, although a clearance via is conventionally formed in the step of manufacturing a unit substrate, in the present invention, a clearance via (57 in FIG. 11) is formed after the via hole 32 is formed. Therefore, when exposing the ground layer exposed to the inner wall of the via hole as it is, it is not easy to form a clearance via by etching only the ground layer having the same material as the other wiring layer into the inner wall of the via hole. The clearance metal layer 50 having the selective etching capability is formed. That is, as shown in FIG. 11, the clearance metal layer 50 has a higher selectivity than copper, so that the clearance metal layer 50 is exposed to the wiring layer 41 exposed to the inner wall of the via hole 32 in the etching process. In comparison, the metal layer 50 is quickly etched to form a clearance via 57 in the inner wall of the via hole 32. (74) The degree of etching of the clearance metal layer 50 changes the conditions of the etching environment. The clearance via 57 is preferably formed in the clearance metal layer 50 between the ground layer 49 at the inner wall of the via hole 32. More preferably, the clearance via 57 is formed close to the diameter of the via lands 43a and 47a formed on the upper and lower portions of the via hole 32.

Next, as shown in FIG. 12, the clearance via (57 in FIG. 11) is filled with an insulating resin having a high insulation resistance to form a clearance 59. That is, the insulating resin in the liquid state is formed through the via hole 32. ), The insulating resin entering the via hole 32 by capillary action fills the clearance via (57 in FIG. 11). It is preferable to use an epoxy-based plastic resin as the insulating resin. In addition, the insulating resin formed on the inner wall of the via hole 32 is removed in order to proceed with the plating process. In an embodiment of the present invention, the insulating resin formed on the inner wall of the via hole 32 is removed using permanganic acid.

Next, as illustrated in FIG. 13, the inner wall of the via hole 32 is plated with a conductive metal such as copper to form the plating layer 38, thereby completing the manufacturing process of the printed circuit board 30. It is preferable to use an electroless plating method as the plating method, and the plating layer 38 formed in the via hole 32 electrically connects the upper wiring layer 43, the inner wiring layer 45, and the lower wiring layer 49.

Accordingly, a clearance 59, which is an insulating layer, is formed between the ground layer 49 and the plating layer 38 so that the ground layer 49 is electrically insulated from the via hole 32. In addition, a clearance metal layer 50 connected to the ground layer 49 is formed around the via hole 32 to suppress generation of noise in a signal transmitted through the via hole 32. The clearance metal layer 50 outside the clearance 59 is electrically connected to the ground layer 49 to establish a ground region.

In the embodiment of the present invention, the process of forming the clearance in the ground layer has been described. However, since the process of forming the clearance in the power layer is also the same as the above-described process, a detailed description thereof will be omitted.

Meanwhile, in the present invention, the clearance metal layer 50 is formed in correspondence to the via holes 32, but if the via holes are densely packed, the wiring layer is etched in the entire area where the via holes are densely formed to form the clearance metal layer. It does not fall outside the scope of the technical idea of the invention.

Therefore, according to the structure of the present invention, by overlapping the clearance vias in the ground / power layer by preventing the size of the clearance vias between the adjacent via holes small, the ground area between the via holes in the ground layer can be prevented. The power layer may be electrically insulated from the via hole to maintain a uniform impedance value at each point of the printed circuit board.

Since the clearance via is formed after the via hole is formed, the size of the clearance via may be easily adjusted by adjusting the etching condition of the clearance metal layer.

Claims (9)

As a method of manufacturing a printed circuit board having a clearance, (A) a substrate formed by stacking a plurality of unit substrates having a metal layer on the substrate body, wherein a clearance metal layer having a selective etching ability with the specific metal layer is formed on a specific metal layer of a specific unit substrate to form a clearance among the unit substrates; Preparing a substrate; (b) forming a via hole through the clearance metal layer and for electrically connecting the metal layer; (c) selectively etching the clearance metal layer with respect to the metal layer to form a clearance via inside the inner wall of the via hole; (d) filling the clearance vias with an insulating resin to form a clearance; And (e) plating an inner wall of the via hole to form a plating layer to electrically connect the metal layer exposed to the inner wall of the via hole; And the clearance is electrically insulated from the specific metal layer and the plating layer formed in the via hole. The method of claim 1, wherein the metal layer, A circuit wiring layer including an upper wiring layer formed on the substrate body, an internal wiring layer formed inside the substrate body, and a lower wiring layer formed under the substrate body; And A ground layer formed inside the substrate body; And said ground layer is said specific metal layer. The method of claim 2, wherein the forming of the clearance metal layer in the step (a) (a1) preparing a unit substrate having the ground layer formed on the substrate body; (a2) applying a photoresist on the ground layer and developing the photoresist on the ground layer to be formed with clearance vias to form a window; (a3) etching the ground layer exposed to the window to form a groove; (a4) forming a clearance metal layer in the groove having a selective etching ability with respect to the ground layer; And (a5) removing the photoresist; manufacturing method of a printed circuit board comprising a. The method of claim 3, wherein step (a4) comprises: Forming an intermediate metal layer of nickel in the groove by an electroless plating method, and forming a clearance metal layer of nickel filling the groove on the intermediate metal layer by an electrolytic plating method. Manufacturing method. The method of claim 2, wherein the metal layer further comprises a power layer, wherein the power layer is the specific metal layer on which the clearance is formed. The method of claim 1, wherein in the step (c), a clearance via is formed in the clearance metal layer. The method of claim 1, wherein the insulating resin of step (d) is an epoxy-based plastic resin and fills the clearance via using the capillary action of the plastic resin in a fluid state. The method of claim 1, wherein after the step (d), the insulating resin formed on the inner wall of the via hole is removed using permanganic acid. The method of claim 1, wherein the step (e) comprises forming a copper plating layer on an inner wall of the via hole by an electroless plating method.