KR20000008122A - Method for forming via contact of semiconductor device - Google Patents

Method for forming via contact of semiconductor device Download PDF

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Publication number
KR20000008122A
KR20000008122A KR1019980027804A KR19980027804A KR20000008122A KR 20000008122 A KR20000008122 A KR 20000008122A KR 1019980027804 A KR1019980027804 A KR 1019980027804A KR 19980027804 A KR19980027804 A KR 19980027804A KR 20000008122 A KR20000008122 A KR 20000008122A
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South Korea
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interlayer insulating
insulating film
forming
etching
via contact
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KR1019980027804A
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Korean (ko)
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이수근
김선래
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윤종용
삼성전자 주식회사
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Priority to KR1019980027804A priority Critical patent/KR20000008122A/en
Publication of KR20000008122A publication Critical patent/KR20000008122A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A forming method of a via contact is provided to prevent an interlayer insulating film from being overetched along a lower metal wire side. CONSTITUTION: The method comprises the steps of forming a metal wire on a semiconductor substrate in which an insulating layer is formed; sequentially forming a first interlayer insulating film and a second interlayer insulating film on the above resultant using a deposition process and a sputtering etching process, wherein characteristics of the first and the second interlayer insulating films are different each other; forming a third interlayer insulating film on the above resultant and planarly etching a surface thereof; and sequentially etching the third, the second, and the first interlayer insulating films to form a via contact hole exposing the metal wire.

Description

반도체 장치의 비어 콘택 형성방법Method of forming via contact in semiconductor device

본 발명은 반도체 장치의 제조 방법에 관한 것으로, 보다 상세하게는 다층 배선 구조에서 금속 배선들 간을 절연시키기 위한 층간 절연막(intermetal dielectric film; IMD)을 식각하여 비어 콘택(via contact)을 형성할 때 하부의 금속 배선 측면을 따라 상기 층간 절연막이 과도 식각되는 것을 방지할 수 있는 반도체 장치의 비어 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to forming a via contact by etching an intermetal dielectric film (IMD) for insulating metal wires in a multilayer wiring structure. A method of forming a via contact in a semiconductor device capable of preventing over-etching of the interlayer insulating layer along a lower side of a metal wiring.

반도체 제품이 소형화 및 경량화되는 추세에 따라 소자의 디자인-룰이 감소하면서 배선에 의한 RC 지연이 소자의 동작 속도를 결정하는 중요한 요인으로 등장하고 있다. 이에 따라, 다층 배선 구조가 실용화되고 있는데, 이러한 다층 배선 구조에서는 금속 배선과 금속 배선을 연결하기 위한 비어 콘택의 특성이 더욱 중요해진다.As semiconductor products become smaller and lighter, the design-rule of the device decreases, and the RC delay caused by the wiring has emerged as an important factor determining the operation speed of the device. Accordingly, the multilayer wiring structure has been put into practical use. In this multilayer wiring structure, the characteristics of the via contact for connecting the metal wiring and the metal wiring become more important.

도 1은 종래 방법에 의한 반도체 장치의 비어 콘택 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a via contact forming method of a semiconductor device according to a conventional method.

도 1을 참조하면, 소정의 회로 패턴들이 형성되어 있는 반도체 기판(도시하지 않음)의 상부에 절연층(12)을 형성한 후, 상기 절연층(12)의 상부에 예컨대 알루미늄막을 스퍼터링하고 이를 사진식각 공정으로 패터닝하여 하부 금속 배선(14)을 형성한다. 상기 하부 금속 배선(14)이 형성된 결과물의 상부에 층간 절연막(16)으로서, 예컨대 산화막을 형성한 후, 사진식각 공정으로 상기 층간 절연막(16)을 식각하여 하부 금속 배선(14)을 노출시키는 비어 콘택(18)을 형성한다. 이어서, 결과물의 상부에 예컨대 텅스텐막을 증착하고 상기 층간 절연막(16)의 표면이 노출될 때까지 화학 물리적 연마(chemical mechanical polishing; CMP) 방법으로 상기 텅스텐막을 식각함으로써 상기 비어 콘택(18)의 내부에 비어 플러그(도시하지 않음)를 형성한다. 다음에, 결과물의 상부에 알루미늄막을 스퍼터링하고 이를 사진식각 공정으로 패터닝함으로써, 상기 비어 콘택(18)을 통해 하부 금속 배선(14)에 연결되는 상부 금속 배선(도시하지 않음)을 형성한다.Referring to FIG. 1, after forming an insulating layer 12 on a semiconductor substrate (not shown) in which predetermined circuit patterns are formed, an aluminum film is sputtered on the insulating layer 12 and photographed. The lower metal wiring 14 is formed by patterning by an etching process. A via for forming the interlayer insulating film 16 as an interlayer insulating film 16 on the resultant on which the lower metal wiring 14 is formed, for example, and then etching the interlayer insulating film 16 by a photolithography process to expose the lower metal wiring 14. The contact 18 is formed. Subsequently, a tungsten film is deposited on top of the resultant material, and the tungsten film is etched by chemical mechanical polishing (CMP) until the surface of the interlayer insulating film 16 is exposed to the inside of the via contact 18. Form a via plug (not shown). Next, by sputtering the aluminum film on top of the resultant and patterning it by a photolithography process, an upper metal wiring (not shown) connected to the lower metal wiring 14 through the via contact 18 is formed.

통상적으로, 비어 콘택의 크기에 비해 금속 배선의 크기가 약간 크거나 거의 동일하기 때문에, 비어 콘택(18)과 하부 금속 배선(14) 간의 오버랩 마진이 거의 없다. 따라서, 비어 콘택(18)이 형성될 영역을 정의하기 위한 사진 공정시 하부 금속 배선(14)에 대한 미스얼라인이 발생하면, 상기 비어 콘택(18)을 형성하기 위한 식각 공정시 하부 금속 배선(14)의 측면을 따라 층간 절연막(16)이 과도 식각되어 콘택 불량을 유발하게 된다.Typically, there is little overlap margin between the via contact 18 and the lower metal interconnect 14 because the size of the metal interconnect is slightly larger or nearly the same as the via contact. Therefore, if a misalignment occurs in the photolithography process for defining the region where the via contact 18 is to be formed, the lower metal interconnection during the etching process for forming the via contact 18 may occur. The interlayer insulating layer 16 is excessively etched along the side surface of the substrate 14, causing contact failure.

따라서, 본 발명의 목적은 다층 배선 구조에서 금속 배선들 간을 절연시키기 위한 층간 절연막을 식각하여 비어 콘택을 형성할 때 하부의 금속 배선 측면을 따라 상기 층간 절연막이 과도 식각되는 것을 방지할 수 있는 반도체 장치의 비어 콘택 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a semiconductor capable of preventing over-etching of the insulating interlayer along the side of the lower metal wiring when the via contact is formed by etching the interlayer insulating film to insulate the metal wirings from the multilayer wiring structure. A method of forming a via contact in an apparatus is provided.

도 1은 종래 방법에 의한 반도체 장치의 비어 콘택 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a via contact forming method of a semiconductor device by a conventional method.

도 2 내지 도 4는 본 발명에 의한 반도체 장치의 비어 콘택 형성방법을 설명하기 위한 단면도.2 to 4 are cross-sectional views for explaining a via contact forming method of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

102 : 절연층 104 : 하부 금속 배선102: insulating layer 104: lower metal wiring

106 : 제1 층간 절연막 108 : 제2 층간 절연막106: first interlayer insulating film 108: second interlayer insulating film

110 : 제3 층간 절연막 112 : 비어 콘택110: third interlayer insulating film 112: via contact

상기 목적을 달성하기 위하여 본 발명은, 절연층이 형성되어 있는 반도체 기판의 상부에 금속 배선을 형성하는 단계; 상기 결과물의 상부에 서로 다른 성질을 갖는 제1 층간 절연막 및 제2 층간 절연막을 증착 및 스퍼터 식각 방식에 의해 순차적으로 형성하는 단계; 상기 결과물의 상부에 제3 층간 절연막을 형성하고 그 표면을 평탄화시키는 단계; 및 상기 제3, 제2 및 제1 층간 절연막들을 식각하여 상기 금속 배선을 노출시키는 비어 콘택을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a metal wiring on top of the semiconductor substrate on which the insulating layer is formed; Sequentially forming a first interlayer insulating film and a second interlayer insulating film having different properties on the result by deposition and sputter etching; Forming a third interlayer insulating film on top of the resultant and planarizing the surface thereof; And forming a via contact exposing the metal line by etching the third, second and first interlayer insulating layers.

바람직하게는, 상기 제1 층간 절연막은 화학기상증착(chemical vapor deposition; 이하 "CVD"라 한다)-산화막으로 형성하고 상기 제2 층간 절연막은 실리콘(Si)이 많은 CVD막으로 형성한다. 더욱 바람직하게는, 상기 제2 층간 절연막은 SiON 또는 SiN으로 형성한다.Preferably, the first interlayer insulating film is formed of a chemical vapor deposition (hereinafter referred to as "CVD")-oxide film, and the second interlayer insulating film is formed of a CVD film rich in silicon (Si). More preferably, the second interlayer insulating film is formed of SiON or SiN.

바람직하게는, 상기 제3 층간 절연막을 평탄화시키는 단계는 화학 물리적 연마(CMP) 공정으로 수행한다.Preferably, the step of planarizing the third interlayer insulating film is performed by a chemical physical polishing (CMP) process.

바람직하게는, 상기 비어 콘택을 형성하는 단계에서, 상기 제1 층간 절연막과 제2 층간 절연막에 대한 식각 선택비를 크게 하여 식각을 진행한다.Preferably, in the forming of the via contact, etching is performed by increasing an etching selectivity of the first interlayer insulating film and the second interlayer insulating film.

또한, 상기 목적을 달성하기 위하여 본 발명은, 다층 배선 구조를 갖는 반도체 장치의 제조 방법에 있어서, 배선들 간을 절연시키기 위한 층간 절연막은 서로 다른 성질을 갖는 2층 이상의 막을 증착 및 스퍼터 식각 방식으로 증착하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.In addition, in order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device having a multi-layered wiring structure, the interlayer insulating film for insulating between the wirings by depositing and sputter etching the two or more layers having different properties Provided are a method of manufacturing a semiconductor device, which is formed by vapor deposition.

바람직하게는, 상기 서로 다른 성질을 갖는 2층 이상의 막은 CVD 막으로 형성한다. 상기 서로 다른 성질을 갖는 2층 이상의 막은 그 조성을 다르게 하는 방법 또는 화학 구조를 다르게 하는 방법으로 증착한다.Preferably, the two or more layers having different properties are formed of a CVD film. The two or more layers having different properties may be deposited by different compositions or different chemical structures.

상술한 바와 같이 본 발명에 의하면, 서로 다른 성질을 가지며 증착 및 스퍼터 식각 방식으로 증착하는 2층 이상의 막으로 층간 절연막을 형성하고, 비어 콘택을 형성하기 위한 식각 공정시 상기 2층 이상의 막에 대한 식각 선택비를 크게 하여 식각한다. 따라서, 비어 콘택 영역을 정의하기 위한 사진 공정시 하부의 금속 배선에 대한 미스얼라인이 발생하더라도, 비어 콘택을 형성하기 위한 식각 공정시 상기 2층 이상의 막들이 서로에 대해 높은 식각 선택비를 가지므로 하부의 금속 배선 측면을 따라 층간 절연막이 과도 식각되는 것을 방지할 수 있다.As described above, according to the present invention, an interlayer insulating film is formed of two or more layers having different properties and deposited by deposition and sputter etching, and the etching of the two or more layers during an etching process for forming a via contact. Etch with a high selection ratio. Therefore, even if a misalignment occurs on the underlying metal wiring during the photolithography process for defining the via contact region, the two or more layers have a high etching selectivity with respect to each other during the etching process for forming the via contact. It is possible to prevent excessive etching of the interlayer insulating film along the lower metal wiring side surface.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2 내지 도 4는 본 발명에 의한 반도체 장치의 비어 콘택 형성방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of forming a via contact of a semiconductor device according to the present invention.

도 2는 제1 층간 절연막(106) 및 제2 층간 절연막(108)을 형성하는 단계를 도시한다. 소정의 회로 패턴들(도시하지 않음)이 형성되어 있는 반도체 기판(100)의 상부에 절연층(102)을 형성한 후, 그 상부에 금속층으로서, 예컨대 알루미늄(Al)층을 스퍼터링 방법으로 형성한다.2 illustrates the steps of forming a first interlayer insulating film 106 and a second interlayer insulating film 108. After the insulating layer 102 is formed on the semiconductor substrate 100 on which predetermined circuit patterns (not shown) are formed, an aluminum (Al) layer is formed as a metal layer thereon, for example, by a sputtering method. .

이어서, 사진식각 공정으로 상기 알루미늄층을 패터닝하여 하부 금속 배선들(104)을 형성한 후, 결과물의 상부에 고밀도 플라즈마(high density plasma; 이하 "HDP"라 한다) CVD 방식으로 산화막을 증착하여 제1 층간 절연막(106)을 형성한다. 상기 HDPCVD-산화막은 증착 및 스퍼터 식각으로 증착되는 특성을 가지므로, 하부 구조물의 단차에 따라 증착되는 양이 달라진다. 즉, 하부 금속 배선(104)과 하부 금속 배선(104) 사이의 평평한 공간에서는 일정한 속도로 증착되지만, 하부 금속 배선(104)의 크기가 작은 영역에서는 식각되면서 증착되므로 일정 두께까지 증착된 후 증착 속도와 스퍼터 식각 속도가 동일하게 되어 더 이상 증착되지 않는다.Subsequently, the aluminum layer is patterned by a photolithography process to form lower metal interconnections 104, and then an oxide film is deposited by a high density plasma (CVD) method on top of the resultant. One interlayer insulating film 106 is formed. Since the HDPCVD-oxide film has a property of being deposited by deposition and sputter etching, the amount of deposition depends on the level of the lower structure. That is, it is deposited at a constant speed in the flat space between the lower metal wiring 104 and the lower metal wiring 104, but is deposited by etching in a region where the size of the lower metal wiring 104 is small, so that the deposition rate after deposition to a certain thickness The and sputter etch rates are the same and are no longer deposited.

상기와 같이 제1 층간 절연막(104)을 증착한 후, 결과물의 상부에 상기 제1 층간 절연막(104)과는 성질이 다른 제2 층간 절연막(106), 예컨대 실리콘(Si)이 많은 HDPCVD-막을 증착 및 스퍼터 식각 방식으로 얇게 증착한다. 바람직하게는, 상기 제2 층간 절연막(106)은 SiON 또는 SiN으로 형성하며, 후속하는 비어 콘택 형성을 위한 식각 공정시 과도 식각을 견딜 수 있을 정도의 두께로 형성한다. 상기 제2 층간 절연막(106)은 하부 금속 배선(104)의 크기가 작은 영역, 즉 제1 층간 절연막(106)이 모서리를 이룬 영역에서는 증착되지 않으며, 하부 금속 배선(104)과 하부 금속 배선(104) 사이의 평평한 공간 및 하부 금속 배선(104)의 크기가 큰 영역에서만 증착된다.After the first interlayer insulating film 104 is deposited as described above, a second interlayer insulating film 106 having different properties from the first interlayer insulating film 104, for example, an HDPCVD-rich film having a large amount of silicon (Si), is formed on the resultant. Thin deposition is performed by deposition and sputter etching. Preferably, the second interlayer insulating film 106 is formed of SiON or SiN, and is formed to a thickness sufficient to withstand the excessive etching during the etching process for subsequent via contact formation. The second interlayer insulating layer 106 is not deposited in a region where the size of the lower metal interconnection 104 is small, that is, a region where the first interlayer insulation layer 106 forms a corner, and the lower metal interconnection 104 and the lower metal interconnection ( It is deposited only in the flat space between the 104 and the region where the size of the lower metal wiring 104 is large.

도 3은 제3 층간 절연막(110)을 형성하는 단계를 도시한다. 상술한 바와 같이 서로 다른 성질을 갖는 제1 층간 절연막(106) 및 제2 층간 절연막(108)을 증착 및 스퍼터 식각 방식에 의해 순차적으로 증착한 후, 결과물의 상부에 제3 층간 절연막(110)으로서, 예컨대 CVD-산화막을 약 14000Å의 두께로 증착한다. 바람직하게는 상기 제3 층간 절연막(110)은 PE-TEOS막으로 형성한다.3 illustrates a step of forming a third interlayer insulating film 110. As described above, the first interlayer insulating film 106 and the second interlayer insulating film 108 having different properties are sequentially deposited by the deposition and sputter etching method, and then, as the third interlayer insulating film 110 on the resultant. For example, a CVD-oxide film is deposited to a thickness of about 14000 GPa. Preferably, the third interlayer insulating film 110 is formed of a PE-TEOS film.

이어서, CMP 공정을 실시하여 상기 제3 층간 절연막(110)의 표면을 평탄화시킨다. 상기 CMP 공정은 제3 층간 절연막(110)이 5000Å ∼ 7000Å 정도의 두께가 될 때까지 진행한다.Subsequently, a CMP process is performed to planarize the surface of the third interlayer insulating layer 110. The CMP process proceeds until the third interlayer insulating film 110 has a thickness of about 5000 kPa to 7000 kPa.

도 4는 비어 콘택(112)을 형성하는 단계를 도시한다. 상기와 같이 제3 층간 절연막(110)을 평탄화시킨 후, 사진식각 공정으로 상기 층간 절연막들(110, 108, 106)을 식각하여 하부 금속 배선(104)을 노출시키는 비어 콘택(112)을 형성한다. 상기 식각 공정은 제1 층간 절연막(106)과 제2 층간 절연막(108)에 대한 식각 선택비를 4:1 이상으로 하여 진행한다. 예를 들어, 상기 식각 공정은 챔버 내의 압력은 약 40mT, RF 전력은 약 1500WS, C4F8가스의 유속은 약 18 sccm(standard cubic centimeter perminute), 아르곤(Ar) 가스의 유속은 약 500 sccm, 그리고 산소(O2) 가스의 유속은 약 10 sccm의 조건 하에서 60초 동안 실시한다.4 illustrates forming via contact 112. After the planarization of the third interlayer insulating layer 110 as described above, the via insulating layers 110, 108, and 106 are etched by a photolithography process to form a via contact 112 exposing the lower metal wiring 104. . The etching process proceeds with an etching selectivity of 4: 1 or more for the first interlayer insulating film 106 and the second interlayer insulating film 108. For example, in the etching process, the pressure in the chamber is about 40 mT, the RF power is about 1500 WS, the flow rate of C 4 F 8 gas is about 18 sccm (standard cubic centimeter perminute), and the flow rate of argon (Ar) gas is about 500 sccm. And a flow rate of oxygen (O 2 ) gas for 60 seconds under conditions of about 10 sccm.

또한, 상기 식각 공정은 넓은 패턴 상에서의 제2 층간 절연막(108)을 식각할 때는 제1 층간 절연막(106)과 제2 층간 절연막(108)의 식각 선택비를 작게 하고, 상기 영역의 제2 층간 절연막(180)을 식각한 후에는 식각 선택비를 크게 하여 진행하는 것이 바람직하다.In the etching process, when the second interlayer insulating layer 108 is etched on a wide pattern, the etching selectivity of the first interlayer insulating layer 106 and the second interlayer insulating layer 108 is reduced, and the second interlayer of the region is reduced. After the insulating layer 180 is etched, it is preferable to increase the etching selectivity.

이어서, 결과물의 상부에 금속층으로서, 예컨대 텅스텐층을 CVD 방법으로 증착하고 상기 제3 층간 절연막(110)의 표면이 노출될 때까지 CMP 방법으로 상기 텅스텐층을 식각함으로써 상기 비어 콘택(112)의 내부에 비어 플러그(도시하지 않음)를 형성한다. 다음에, 결과물의 상부에 금속층으로서, 예컨대 알루미늄층을 스퍼터링 방법으로 형성하고 상기 알루미늄층을 사진식각 공정으로 패터닝함으로써, 상기 비어 콘택(112)을 통해 하부 금속 배선(104)에 연결되는 상부 금속 배선(도시하지 않음)을 형성한다.The interior of the via contact 112 is then deposited by depositing a tungsten layer as a metal layer on top of the resultant, for example, by a CVD method and etching the tungsten layer by CMP until the surface of the third interlayer insulating film 110 is exposed. A via plug (not shown) is formed in the groove. Next, an upper metal wiring connected to the lower metal wiring 104 through the via contact 112 by forming a metal layer on top of the resultant, for example, an aluminum layer by a sputtering method and patterning the aluminum layer by a photolithography process. (Not shown).

상술한 바와 같이 본 발명에 의하면, 서로 다른 성질을 가지며 증착 및 스퍼터 식각 방식으로 증착하는 2층 이상의 막으로 층간 절연막을 형성하고, 비어 콘택을 형성하기 위한 식각 공정시 상기 2층 이상의 막에 대한 식각 선택비를 크게 하여 식각한다. 따라서, 비어 콘택 영역을 정의하기 위한 사진 공정시 하부의 금속 배선에 대한 미스얼라인이 발생하더라도, 비어 콘택을 형성하기 위한 식각 공정시 상기 2층 이상의 막들이 서로에 대해 높은 식각 선택비를 가지므로 하부의 금속 배선 측면을 따라 층간 절연막이 과도 식각되는 것을 방지할 수 있다.As described above, according to the present invention, an interlayer insulating film is formed of two or more layers having different properties and deposited by deposition and sputter etching, and the etching of the two or more layers during an etching process for forming a via contact. Etch with a high selection ratio. Therefore, even if a misalignment occurs on the underlying metal wiring during the photolithography process for defining the via contact region, the two or more layers have a high etching selectivity with respect to each other during the etching process for forming the via contact. It is possible to prevent excessive etching of the interlayer insulating film along the lower metal wiring side surface.

상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (8)

절연층이 형성되어 있는 반도체 기판의 상부에 금속 배선을 형성하는 단계;Forming a metal wiring on the semiconductor substrate on which the insulating layer is formed; 상기 결과물의 상부에 서로 다른 성질을 갖는 제1 층간 절연막 및 제2 층간 절연막을 증착 및 스퍼터 식각 방식에 의해 순차적으로 형성하는 단계;Sequentially forming a first interlayer insulating film and a second interlayer insulating film having different properties on the result by deposition and sputter etching; 상기 결과물의 상부에 제3 층간 절연막을 형성하고 그 표면을 평탄화시키는 단계; 및Forming a third interlayer insulating film on top of the resultant and planarizing the surface thereof; And 상기 제3, 제2 및 제1 층간 절연막들을 식각하여 상기 금속 배선을 노출시키는 비어 콘택을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법.And forming a via contact to expose the metal line by etching the third, second and first interlayer insulating films. 제1항에 있어서, 상기 제1 층간 절연막은 화학기상증착(CVD)-산화막으로 형성하고 상기 제2 층간 절연막은 실리콘(Si)이 많은 CVD막으로 형성하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법.2. The via contact formation of claim 1, wherein the first interlayer insulating film is formed of a chemical vapor deposition (CVD) -oxide film and the second interlayer insulating film is formed of a CVD film rich in silicon (Si). Way. 제2항에 있어서, 상기 제2 층간 절연막은 SiON 또는 SiN으로 형성하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법.3. The method of claim 2, wherein the second interlayer insulating film is formed of SiON or SiN. 제1항에 있어서, 상기 제3 층간 절연막의 표면을 평탄화시키는 단계는 화학 물리적 연마(CMP) 공정으로 수행하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법.The method of claim 1, wherein the planarization of the surface of the third interlayer insulating layer is performed by a chemical physical polishing (CMP) process. 제1항에 있어서, 상기 비어 콘택을 형성하는 단계에서, 상기 제1 층간 절연막과 제2 층간 절연막에 대한 식각 선택비를 크게 하여 식각을 진행하는 것을 특징으로 하는 반도체 장치의 비어 콘택 형성방법.The method of claim 1, wherein in the forming of the via contact, etching is performed by increasing an etching selectivity of the first interlayer insulating layer and the second interlayer insulating layer. 다층 배선 구조를 갖는 반도체 장치의 제조 방법에 있어서,In the manufacturing method of the semiconductor device which has a multilayer wiring structure, 배선들 간을 절연시키기 위한 층간 절연막은 서로 다른 성질을 갖는 2층 이상의 막을 증착 및 스퍼터 식각 방식으로 증착하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.A method for manufacturing a semiconductor device, characterized in that the interlayer insulating film for insulating the wirings is formed by depositing two or more layers having different properties by deposition and sputter etching. 제6항에 있어서, 상기 서로 다른 성질을 갖는 2층 이상의 막은 CVD 막으로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 6, wherein the two or more layers having different properties are formed of a CVD film. 제7항에 있어서, 상기 서로 다른 성질을 갖는 2층 이상의 막은 그 조성을 다르게 하는 방법 또는 화학 구조를 다르게 하는 방법으로 증착하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 7, wherein the two or more layers having different properties are deposited by a method having a different composition or a method having a different chemical structure.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7871829B2 (en) 2006-01-02 2011-01-18 Samsung Electronics Co., Ltd. Metal wiring of semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7871829B2 (en) 2006-01-02 2011-01-18 Samsung Electronics Co., Ltd. Metal wiring of semiconductor device and method of fabricating the same

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