KR20000005819U - Automatic Gain Control Circuit of Tuner for Digital Broadcast Reception - Google Patents

Abstract

The present invention relates to an automatic gain control circuit for a digital broadcast reception tuner, and more particularly, to an automatic gain control circuit for improving the reduction of gain due to the capacitive component of the diode toward the high frequency side.

The automatic gain control circuit of the digital broadcast reception tuner of the present invention for realizing this includes at least two diodes connected in series to compensate for the amount of gain reduction of the high frequency side, and is formed in a pattern formed by the capacitance component and the pattern of the diode. The inductance component is characterized in that the gain can be adjusted to configure the trap on the high frequency side.

Description

Automatic Gain Control Circuit of Tuner for Digital Broadcast Reception

The present invention relates to an automatic gain control (AGC) circuit of a digital broadcast reception tuner (TUNER), and more particularly, to an automatic gain control circuit that improves the reduction in gain due to the capacitive component of the diode toward higher frequencies.

In general, a tuner is a device that selects only one desired channel from among a plurality of TV channels being broadcast, converts it into an intermediate frequency IF, and supplies the set to an image intermediate amplifier.

Hereinafter, a conventional general digital broadcast tuner will be briefly described.

A conventional digital satellite broadcasting tuner (not shown) includes an automatic gain control (AGC) circuit that automatically adjusts gain so that the output of a video signal is always constant even when the magnitude of the high frequency signal induced by the antenna changes. A high frequency amplifying circuit for amplifying a high frequency signal passing through the automatic gain control (AGC) circuit, a high frequency tuning circuit for selecting a desired high frequency signal from the amplified high frequency signal by the high frequency amplifying circuit, and a microcom (external to the tuner) A local oscillation circuit interlocked by a frequency synthesizer controlled by a frequency synthesizer to output an oscillation frequency, a PLL clock circuit generating a clock signal of a predetermined period, a reference frequency output from the PLL clock circuit, and a local oscillation circuit; Compare the oscillation frequency with and determine whether it is higher or lower than the reference frequency It is composed of PLL (Phase Locked Loop) IC which controls the oscillation frequency of the true circuit to be lowered and, if it is low, controls it to the higher side.

And a first mixer circuit for outputting an intermediate frequency by mixing the high frequency signal selected through the high frequency tuning circuit and the oscillation frequency of the local oscillation circuit, and a first intermediate frequency amplifier circuit for amplifying the intermediate frequency of the first mixer circuit. And an intermediate frequency filter for filtering the intermediate frequency amplified by the first intermediate frequency amplifier circuit, and a second intermediate frequency amplifier circuit for amplifying the intermediate frequency filtered through the intermediate frequency filter.

And an intermediate frequency oscillator circuit controlled by an AFT (Automatic Fine Tunning) signal outside the tuner to generate an oscillation frequency shifted in phases of 0 ° and 90 °, and an intermediate frequency amplified by the second intermediate frequency amplifier circuit. A second mixer circuit for mixing the 0 ° phase shifted oscillation frequency output from the intermediate frequency oscillator circuit and outputting a demodulated baseband signal I, the intermediate frequency amplified by the second intermediate frequency amplifier circuit and the intermediate frequency; And a third mixer circuit for outputting a demodulated baseband signal Q by mixing the 90 ° phase shifted oscillation frequency output from the frequency oscillation circuit.

1 shows an automatic gain control (AGC) circuit of a tuner according to the prior art, comprising a capacitor C1 connected between an antenna and a node N1, and an input terminal between the node N1 and an automatic gain control voltage AGC. A resistor connected in series between the connected coil L1, the capacitor C2 connected between the node N1 and the DC power supply voltage B ⁺ , and the DC power supply voltage B ⁺ and the node N2. R1 and diode D2, and capacitor C3 connected between node N2 and ground terminal Vss. The diode D1 connected between the node N1 and the node N3, the diode D3 and the resistor R2 connected in series between the node N3 and the node N4, and the node A capacitor C4 connected between the N4 and the ground terminal Vss, a coil L2 connected between the node N2 and the node N4, and a connection between the node N3 and the ground terminal. Resistor R3 and a capacitor C5 connected between the node N3 and the output terminal out.

In the conventional automatic gain control circuit of the tuner having the above configuration, the impedance decreases as the frequency increases with X _c = 1 / (jwc) due to the capacitance component of the series diode, thereby reducing the gain reduction amount.

The output waveform thereof is shown in FIG. 2.

In the figure, it can be seen that the gain reduction amount of the 800 MHz side is much smaller than 50 MHz in the high frequency frequency of 50-800 MHz.

In order to solve this problem, in the conventional terrestrial digital TV tuner, as shown in FIG. 3, a capacitor C6 connected between an antenna and a node N5 and a space between the node N5 and a DC power supply voltage B ^{+ are} shown. Connected coil L3, resistor R4 and diode D4 connected in series between node N5 and node N6, patterned mutual inductance 10, node N6 and ground terminal Capacitors C9 and C10 connected in parallel to Vss. The capacitor C7 and the diode D5 connected in series between the node N5 and the node N7, the node in which the capacitor C7 and the diode D5 are jointly connected, and the automatic gain control voltage ( A coil L5 connected between an input terminal of an AGC, a resistor R5 and a diode D6 connected in series between the node N7 and the node N8, and a patterned mutual inductance 20; Resistor R7 connected between N6 and node N8, capacitors C11 and C12 connected in parallel between node N8 and ground terminal Vss, and node N7 and ground terminal. It consists of a coil L4 and a resistor R6 connected in series between Vss, and a capacitor C8 connected between the node N7 and the output terminal out.

The automatic gain control circuit of the conventional terrestrial digital TV tuner shown in FIG. 3 comprises a parallel trap circuit with mutual inductances 10 and 20 in which a coil is formed in a pattern, and a capacitance component of a diode, thereby providing a parallel trap at a high frequency side. Position to compensate for the gain reduction.

However, in the conventional automatic gain control circuit of the tuner for digital broadcast reception configured as described above, applying a full voltage to the automatic gain control voltage results in a full gain and outputs a high frequency signal input to the antenna as it is. In the case of high frequency input of the strong electric field, the automatic gain control voltage is lowered to reduce the force of the high frequency signal and output to the next stage. In this case, in the case of the high frequency signal of the high frequency side, the gain reduction amount is small compared to the high frequency signal of the low frequency side, and the controllable gain is small. To solve this problem, a parallel trap is formed using the patterned mutual inductances 10 and 20. The gain reduction on the high frequency side was increased. However, this method also had a problem that the space of the pattern was enlarged and the gain reduction amount was still not satisfactory.

Accordingly, the present invention has been devised to solve the above problems, and an object of the present invention is to provide an automatic gain control circuit which improves a decrease in gain by a capacitive component of a diode toward higher frequencies.

1 is an automatic gain control circuit diagram of a conventional tuner.

2 is an output waveform diagram of a frequency and a gain of the automatic gain control circuit shown in FIG.

3 is another automatic gain control circuit diagram of a conventional tuner.

4 is an output waveform diagram of a frequency and a gain of the automatic gain control circuit shown in FIG.

5 is an automatic gain control circuit diagram of a tuner according to the present invention.

6a and 6b is an output waveform diagram of the frequency and gain of the automatic gain control circuit according to the present invention

* Explanation of symbols for the main parts of the drawings

10, 20: mutual inductance 30: diode circuit

C1 to C12: condenser D1 to D7: diode

R1 to R6: resistors L1 to L5: coils

In order to achieve the above object, the automatic gain control circuit of the digital broadcast reception tuner according to the present invention,

In a tuner comprising an automatic gain control circuit,

The automatic gain control circuit,

Includes at least two diodes connected in series to compensate for gain reduction on the high frequency side,

A mutual inductance component formed in a pattern with the capacitive component of the diode is characterized in that the gain can be configured to adjust the gain in the trap configuration on the high frequency side.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

5 is an automatic gain control circuit diagram of a tuner according to the present invention, and FIGS. 6A and 6B are output waveform diagrams of frequencies and gains of the automatic gain control circuit according to the present invention.

Referring to FIG. 5, the automatic gain control circuit of the present invention includes a capacitor C6 connected between an antenna and a node N5, and a coil L3 connected between the node N5 and a DC power supply voltage B ⁺ . ), A resistor R4, a diode D4, and a patterned mutual inductance 10 connected in series between the node N5 and the node N6, and parallel to the node N6 and the ground terminal Vss. It consists of connected capacitors C9 and C10. Then, the capacitor C7 and the diodes D5 and D7 connected in series between the node N5 and the node N7, the node C7 and the diode D5, and the automatic gain control A coil L5 connected between the input terminals of the voltage AGC, a resistor R5 and a diode D6 connected in series between the node N7 and the node N8, and a patterned mutual inductance 20; The resistor R7 connected between the node N6 and the node N8, the capacitors C11 and C12 connected in parallel between the node N8 and the ground terminal Vss, and the node N7 It consists of a coil L4 and a resistor R6 connected in series between the ground terminal Vss, and a capacitor C8 connected between the node N7 and the output terminal out.

The present invention by the above arrangement improves the reduction of the gain reduction on the high frequency side by X _c = 1 / (jwc) by connecting two diodes D5 and D7 30 connected in series. That is, by connecting two diodes in series, the capacitance component of the diode is prevented from decreasing the impedance at the high frequency side.

Therefore, the two series diodes can reduce the capacitance component of the diode by half (1/2) to increase the gain reduction on the high frequency side, and the space area according to the pattern even when the trap is formed by the patterned mutual inductances 10 and 20. Can be effectively reduced.

The automatic gain control circuit of the present invention outputs a high frequency signal input to the antenna as it is to the next stage as in the automatic gain control circuit of a general tuner at full gain. However, for the strong field signal, the gain is controlled by increasing the amount of gain reduction by using the DC power supply voltage B ⁺ and the automatic gain control voltage.

At this time, by using the two series diodes 30, the capacitance component value by the diode can be reduced by half (1/2) to prevent the reduction of the gain reduction amount due to X _c = 1 / (jwc) at high frequency. When the trap frequency is positioned at the high frequency side when the trap is formed using the mutual inductances 10 and 20 by the pattern and the diode capacitance component, the capacitance component value becomes smaller, so that the inductance value formed by the pattern may be relatively large and the space may be reduced. .

As described above, according to the automatic gain control circuit of the digital broadcast reception tuner according to the present invention, when the automatic gain control voltage is 0V, the gain reduction amount on the high frequency side is significantly improved compared to the low frequency side, and thus the large gain reduction amount is increased. In the trap circuit configuration using the mutual tuning pattern and the capacitance component, the inductance value of the pattern can be increased, thereby reducing the space occupied by the pattern. Further, the Q value is increased even at the same frequency by the mutual inductance having a relatively large inductance value and the smaller capacitance component value, so that the trap attenuation becomes larger.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be possible to various modifications, changes, substitutions and additions through the spirit and scope of the present invention disclosed in the appended utility model registration claims.

Claims (1)

In a tuner comprising an automatic gain control circuit, The automatic gain control circuit, Includes at least two diodes connected in series to compensate for gain reduction on the high frequency side, An automatic gain control circuit for a digital broadcast reception tuner, comprising a mutual inductance component formed of a capacitance component and a pattern of the diode so that gain can be adjusted when a trap is configured at a high frequency side.