KR20000004421A - Thin film transistor liquid crystal display - Google Patents

Abstract

PURPOSE: A thin film transistor liquid crystal display is provided, which can basically prevent a Shot Mura. CONSTITUTION: A thin film transistor liquid crystal display comprises: a gate bus line (12) and a data bus line (14) to be vertically and crossly formed on a glass substrate; a first and second gate electrodes (13a, 13b) to be installed in the gate bus line (12) adjacent to a cross portion of the data bus line (14) and to be installed at a certain distance with the small width than the width of the gate bus line (12); a drain electrode (16) outputted from the data bus line (14) to be overlapped with a certain portion of the first and second gate electrodes (13a, 13b); a first and second source electrodes (15a, 15b) to be overlapped with a certain portion of the first and second gate electrodes (13a, 13b); and a pixel electrode (18) to be symmetrically formed centering around the gate bus line (12), overlapped with the gate bus line (12), and contacted with the first and second source electrodes (15a, 15b). Therefore, since the Shot Mura can to be basically prevented, the picture of the TFT LCD can to be increased.

Description

Thin film transistor liquid crystal display device

The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a thin film transistor liquid crystal display device capable of preventing shot muura.

In general, liquid crystal displays (hereinafter, LCDs) are used in display devices such as televisions and graphic displays.

In particular, TFT LCDs in which switching elements such as thin film transistors (TFTs) are arranged for each pixel arranged in a matrix form have high-speed response characteristics and are suitable for high pixel number, so that they are suitable for high pixel count. It is greatly contributing to the realization of screen quality and colorization comparable to this.

FIG. 1 is a plan view schematically illustrating a lower substrate of a conventional TFT LCD, and as illustrated, the gate bus lines 2 and the data bus lines 4 are vertically intersected on the glass substrate 1. The TFT 10 is formed at the intersection of the gate bus line 2 and the data bus line 4. A pixel electrode 6 made of ITO metal is formed in the unit pixel Pixel defined by the gate bus line 2 and the data bus line 4.

At this time, although not shown, the storage capacitor bus line is formed between the gate bus lines 2, and the glass substrate 1 on which the gate bus lines 2 and the storage capacitor bus line are formed is formed by a gate insulating film. Is covered.

Further, the TFT 10 is formed together with the gate electrode 2a which is a part of the gate bus line 2, the semiconductor layer 3 formed thereon, and the data bus line at the time of formation of the semiconductor layer 3 The source / drain electrodes 4a and 4b are disposed to overlap one side and the other side of the N-side with a predetermined portion, and the drain electrode 4b is in contact with the pixel electrode 6.

On the other hand, the gate bus line, data bus line and other patterns in the TFT LCD are formed through an exposure process using a stepping type photo equipment, which is generally composed of a 6-inch photo mask.

However, since the mask used in the above exposure process is considerably smaller in size than the substrate area, in order to form any kind of pattern in the cell array region, it is necessary to divide the cell array region into predetermined portions and perform partial exposure.

That is, as shown in FIG. 2, when forming a gate bus line, the cell array area of the liquid crystal display is divided into, for example, six spaces, and then a mask for forming the gate bus line (not shown). Is placed on the a1 area and then exposed, and the mask is sequentially moved to the a2, a3, a4, a5 and a6 areas to perform the exposure process.

At this time, each of the a1 to a6 regions is called one shot.

However, in the divided exposure method of exposing the a1 region and then sequentially exposing other regions to form any one kind of pattern as described above, as shown in FIGS. 3A and 3B due to misalignment of the mask, The overlapping degree between the gate electrode and the source 4a may be different for each shot with the semiconductor layer 3 interposed therebetween. The unevenness of brightness between the shots is caused by the influence on the screen, and this unevenness of brightness reduces the image quality of the TFT LCD, that is, the shot muura phenomenon in which black lines appear on the screen. There was a problem to generate.

------- (Equation 1)

ΔVp: Voltage drop across unit pixels

Cgs: parasitic capacitance between gate electrode and source electrode

Clc: liquid crystal capacity in unit pixels

Cst: subcapacity in unit pixels

Vgh: Voltage at Gate On

Vgl: Voltage at Gate Off

Meanwhile, in order to prevent the shot muura, a saw pattern technique is conventionally implemented such that the boundary surface A between shots has an irregular sawtooth shape. There is no solution.

Therefore, it is an object of the present invention to provide a TFT LCD structure that can fundamentally solve shot muura.

1 is a plan view schematically illustrating a lower substrate of a conventional thin film transistor liquid crystal display device;

2 is a view for explaining an exposure method for a conventional cell array region.

3A and 3B illustrate a problem of a conventional thin film transistor liquid crystal display device;

4 is a plan view illustrating a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

5 and 6 are plan views illustrating a thin film transistor liquid crystal display device having a storage capacitor electrode line according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

12: gate bus line 13a: first gate electrode

13b: second gate electrode 14: data bus line

15a: first source electrode 15b: second source electrode

16 drain electrode 20 auxiliary capacitor electrode line

20a, 20b: thin film transistor

TFT LCD of the present invention for achieving the above object, a glass substrate; A gate bus line and a data bus line arranged vertically and crosswise on the glass substrate; First and second gate electrodes disposed in the gate bus line adjacent to the intersection with the data bus line and disposed to be spaced apart from each other by a predetermined width less than the width of the gate bus line; A drain electrode drawn from the data bus line and disposed such that a predetermined area overlaps each of the opposing surfaces of the first and second gate electrodes; First and second source electrodes disposed to overlap a predetermined area with each of the non-facing surfaces of the first and second gate electrodes; And a pixel electrode formed symmetrically about the gate bus line and overlapping with the gate bus line and partially contacting the gate bus line and contacting the first and second source electrodes.

According to the present invention, even if the misalignment of the mask occurs, the overall fluctuation of the Cgs value does not occur, so that the shot mula that the fluctuation of the Cgs is a fundamental cause can be prevented.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view illustrating a TFT LCD according to an embodiment of the present invention. As shown, a gate bus line 12 and a data bus line 14 are vertically intersected on a glass substrate (not shown), and the gate bus line 12 intersects the data bus line 14. The TFT 20 is formed in the portion adjacent to the portion.

Here, a sub pixel is an area that extends between a pair of data lines 14 and a predetermined area on both sides of a gate bus line 14, and includes two TFTs 20a in the unit pixel. 20b) is formed.

In detail, two gate electrodes 13a and 13b are disposed at a portion of the gate bus line 12 adjacent to the intersection with the data bus line 14, and at this time, the gate electrodes 13a and 13b are disposed at the gate. It has a width smaller than that of the bus line 12 and is spaced apart by a predetermined interval in the longitudinal direction of the gate bus line, and the drain electrode 16 withdrawn from the data bus line 14 has the first and second gates. Each of the non-facing surfaces of the first and second gate electrodes 13a and 13b is disposed to overlap the opposite surfaces of the electrodes 13a and 13b, and each of them in the form of an independent pattern. First and second source electrodes 15a and 15b having a predetermined area overlap are formed.

Accordingly, two TFTs 20a and 20b are formed in a portion adjacent to the intersection of the gate bus line 12 and the data bus line 14.

Subsequently, the unit pixel overlaps a predetermined portion of the gate bus line 12, for example, a portion where the TFTs 20a and 20b are not formed, and simultaneously with the first and second source electrodes 15a and 15b, respectively. A “c” shaped pixel electrode 18 is formed.

Although not shown, a gate insulating film is coated on the entire surface of the glass substrate on which the gate bus line 12 and the first and second gate electrodes 13a and 13b are formed, and the first and second gate electrodes ( A semiconductor layer having a size and shape similar to those of the gate electrodes 13a and 13b is formed on the gate insulating layer on the upper portion 13a and 13b, respectively, and the source and drain electrodes 15a and 15b and the drain electrode are formed on one side and the other side of the semiconductor layer. An ohmic contact layer for contact with (16) is formed.

In the TFT LCD of the present invention having the structure as described above, the parasitic capacitance between the first gate electrode 13a and the first source electrode 15a and the second due to mismatch of the pattern due to divided exposure, that is, misalignment of the mask, Although the parasitic capacitances between the gate electrode 13b and the second source electrode 15b are varied, the overall parasitic capacitance does not change.

That is, since each of the two TFTs 20a and 20b has a configuration in which source and drain electrodes are opposite to each other, overlap between the first gate electrode 13a and the first source electrode 15a due to misalignment of a mask. When the degree is reduced, the degree of overlap between the second gate electrode 13b and the second source electrode 15b increases, and conversely, the degree of overlap between the first gate electrode 13a and the first source electrode 15a is increased. When it is increased, the degree of overlap between the second gate electrode 13b and the second source electrode 15b is reduced.

Therefore, in any case, since the value of the overall Cgs can be kept constant at all times, it is possible to fundamentally prevent the fluctuation of the Cgs value acting as a cause of the shot mura.

On the other hand, when the auxiliary capacitance electrode line 20 is provided in order to improve the screen quality of the TFT LCD, as shown in FIG. 5, or provided so as to overlap one edge surface of the pixel electrode 18, or As shown in FIG. 6, a gap is provided between two adjacent pixel electrodes 18.

Accordingly, the unit pixel is partitioned by the storage capacitor electrode lines 20.

As described above, in the present invention, two TFTs are provided in a unit pixel, and the source electrode and the drain electrode are disposed at positions opposite to each other in the respective TFTs. Even if is fluctuated in each TFT, the overall Cgs value can be kept constant, thereby improving the screen quality of the TFT LCD since it is possible to fundamentally prevent the shot mu phenomenon.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (1)

Glass substrates; A gate bus line and a data bus line arranged vertically and crosswise on the glass substrate; First and second gate electrodes disposed in the gate bus line adjacent to the intersection with the data bus line and disposed to be spaced apart from each other by a predetermined width less than the width of the gate bus line; A drain electrode drawn from the data bus line and disposed such that a predetermined area overlaps each of the opposing surfaces of the first and second gate electrodes; First and second source electrodes disposed to overlap a predetermined area with each of the non-facing surfaces of the first and second gate electrodes; And And a pixel electrode formed symmetrically about the gate bus line and overlapping the gate bus line with a portion of the gate bus line, the pixel electrode being in contact with the first and second source electrodes. Liquid crystal display device.