KR20000003960A - Method for forming a polysilicon layer of semiconductor devices - Google Patents
Method for forming a polysilicon layer of semiconductor devices Download PDFInfo
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- KR20000003960A KR20000003960A KR1019980025268A KR19980025268A KR20000003960A KR 20000003960 A KR20000003960 A KR 20000003960A KR 1019980025268 A KR1019980025268 A KR 1019980025268A KR 19980025268 A KR19980025268 A KR 19980025268A KR 20000003960 A KR20000003960 A KR 20000003960A
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- amorphous silicon
- silicon layer
- ion implantation
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims abstract description 25
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- -1 BF2 ions Chemical class 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 15
- 229910052796 boron Inorganic materials 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 230000005465 channeling Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 p형 폴리실리콘층(polysilicon layer) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of forming a p-type polysilicon layer of a semiconductor device.
일반적으로 반도체 소자의 제조 공정에서 p+폴리실리콘층은 불순물이 도핑되지 않은 폴리실리콘(undoped-polysilicon)의 증착 및 이온주입 공정을 통해 전극으로 이용된다. 이온주입 공정은 증착된 도핑되지 않은 폴리실리콘에 p형 도펀트(예를 들어, B 또는 BF2)를 주입하여 도핑된 폴리실리콘(doped polysilicon)을 형성하며, 도펀트를 활성화하고 그레인(grain)의 크기를 조대화하며, 면저항(sheet resistance)을 낮추기 위한 후속 열처리 공정을 필요로 한다.In general, p + polysilicon layer in the manufacturing process of the semiconductor device is used as an electrode through the deposition and ion implantation process of the undoped polysilicon (dope). The ion implantation process injects p-type dopants (e.g., B or BF 2 ) into the deposited undoped polysilicon to form doped polysilicon, activates the dopant and grain size Coarsen and require a subsequent heat treatment process to reduce sheet resistance.
그러나, 도 1에서 도시된 바와 같이 붕소(B)를 도펀트로 사용하는 경우, 채널링에 의한 폴리실리콘층에서의 불균일한 B의 농도 프로파일(profile)로 인하여 게이트 공핍(gate depletion) 현상이 나타나 유효 게이트 산화막(effective gate oxide) 두께를 증가시키게 되어 소자의 전기적 특성을 열화 시킨다. 특히, 짧은 채널 길이(short channel length)가 요구되고 있는 고집적 소자에서는 적합치 않은 공정이다.However, when boron (B) is used as a dopant, as shown in FIG. Increasing the effective gate oxide thickness deteriorates the electrical characteristics of the device. In particular, it is an unsuitable process for highly integrated devices in which short channel length is required.
또한, BF2를 도펀트로 사용하는 경우, 불소(F)의 게이트 산화막으로의 확산에 의해 게이트 산화막 특성을 열화시키는 문제점이 있었다.In addition, when BF 2 is used as a dopant, there is a problem of deterioration of gate oxide film characteristics due to diffusion of fluorine (F) into the gate oxide film.
따라서, 이러한 B의 채널링과 확산을 조절하는 이온주입 공정이 요구되고 있는 실정이다.Therefore, there is a demand for an ion implantation process that controls the channeling and diffusion of B.
본 발명은 소자의 특성 저하를 방지하고, 균일한 도펀트 농도 프로파일을 가지는 반도체 소자의 p형 폴리실리콘층 형성방법을 제공하고자 한다.The present invention is to provide a method for forming a p-type polysilicon layer of a semiconductor device to prevent deterioration of device characteristics and to have a uniform dopant concentration profile.
도 1은 종래기술에 따른 붕소 이온주입시 붕소(B)의 농도 프로파일을 나타낸 그래프.1 is a graph showing a concentration profile of boron (B) during boron ion implantation according to the prior art.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체 소자의 p+폴리실리콘 게이트 전극 형성 공정도.2a to 2d are p + polysilicon gate electrode forming process diagram of a semiconductor device according to an embodiment of the present invention.
도 3a는 본 발명의 일 실시예에 따라 비정질 실리콘에 BF2및 B 이온주입을 차례로 실시한 직후의 비정질 실리콘층에서의 붕소(B) 농도 프로파일을 나타낸 그래프.3A is a graph showing a boron (B) concentration profile in an amorphous silicon layer immediately after sequentially performing BF 2 and B ion implantation into amorphous silicon according to an embodiment of the present invention.
도 3b는 본 발명의 일 실시예에 따라 실리콘 결정립계 성장 및 열처리 공정후 폴리실리콘층에서의 붕소의 농도 프로파일을 나타낸 그래프.Figure 3b is a graph showing the concentration profile of boron in the polysilicon layer after the silicon grain boundary growth and heat treatment process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 필드 산화막10 silicon substrate 11: field oxide film
12 : 게이트 산화막 13 : 비정질 실리콘층12 gate oxide film 13 amorphous silicon layer
14 : p+폴리 마스크14: p + poly mask
상기의 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 특징적인 반도체 소자의 p형 폴리실리콘층 형성방법은 소정의 하부층 상에 비정질 실리콘층을 형성하는 제1 단계; 상기 비정질 실리콘층에 BF2이온주입을 실시하는 제2 단계; 상기 제2 단계 수행후, 상기 비정질 실리콘층에 B 이온주입을 실시하는 제3 단계; 및 열처리를 실시하여 상기 비정질 실리콘층을 다결정화하는 제4 단계를 포함하여 이루어진다.In order to achieve the above technical problem, a method of forming a p-type polysilicon layer of a characteristic semiconductor device provided by the present invention includes a first step of forming an amorphous silicon layer on a predetermined lower layer; Performing a second implantation of BF 2 ions into the amorphous silicon layer; A third step of performing B ion implantation into the amorphous silicon layer after performing the second step; And a fourth step of performing heat treatment to polycrystallize the amorphous silicon layer.
본 발명은 비정질 실리콘 증착후 BF2및 B 이온주입을 실시하여 문턱전압의 변동이나 게이트 공핍과 같은 소자의 전기적 특성의 열화를 방지하는 기술이다. 즉, 본 발명은 붕소(B) 이온주입만을 실시한 경우에 비해 BF2이온주입한 경우 불소에 의해 B의 확산이 촉진된다는 것에 착안하여 B만을 이온주입하지 않고 BF2및 B 이온주입을 실시함으로써 폴리실리콘층에서 일정한 B 농도 프로파일을 가지도록 한다. 여기서, B를 먼저 주입하게 되면, 채널링 현상이 우려되므로, 일차적으로 BF2를 이온주입하고 이차로 불소가 배제된 붕소(B)를 주입한다. 결국 2 단계의 이온주입을 통한 막내의 B의 농도는 변화가 없으나, B의 채널링 현상과 불소의 과도한 확산에 의한 게이트 특성 저하를 방지할 수 있다. 또한, 불소에 의한 붕소의 확산 촉진성을 이용하여 낮은 에너지(low energy)로 이온주입할 수 있어 붕소가 게이트의 산화막 내로 침투하여 게이트의 산화막의 특성을 열화시키는 것을 방지할 수 있다.The present invention is a technique for preventing deterioration of the electrical characteristics of the device, such as fluctuations in threshold voltage or gate depletion by performing BF 2 and B ion implantation after amorphous silicon deposition. That is, the present invention is a boron (B) ion implantation rather than only the ion implantation only B in view of that being the case the diffusion of B by fluorine if a BF 2 ion implantation to promote than subjected polyester by carrying out BF 2 and B-ion injection Have a constant B concentration profile in the silicon layer. In this case, when B is first injected, the channeling phenomenon is concerned, and thus, BF 2 is first implanted and boron (B) in which fluorine is removed second is injected. As a result, the concentration of B in the film through the two-step ion implantation does not change, but it is possible to prevent the deterioration of gate characteristics due to the channeling phenomenon of B and excessive diffusion of fluorine. In addition, ion diffusion can be performed at low energy by utilizing the diffusion promoting property of boron by fluorine, thereby preventing boron from penetrating into the oxide film of the gate and deteriorating the characteristics of the oxide film of the gate.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있도록 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art may easily implement the present invention.
첨부된 도면 도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체 소자의 p+폴리실리콘 게이트 전극 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.2A to 2D illustrate a process of forming a p + polysilicon gate electrode of a semiconductor device according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the accompanying drawings.
우선, 도 2a에 도시된 바와 같이 실리콘 기판(10) 상에 필드 산화막(11)을 형성하고, 활성 영역 상부에 45∼70Å 두께의 게이트 산화막(12)을 성장시킨다. 이어서, 게이트 산화막(12) 상부에 100∼200SCCM의 SiH4가스를 사용하여 500∼1500Å 두께의 비정질 실리콘층(13)을 형성한다.First, as shown in FIG. 2A, a field oxide film 11 is formed on the silicon substrate 10, and a gate oxide film 12 having a thickness of 45 to 70 Å is grown on the active region. Subsequently, an amorphous silicon layer 13 having a thickness of 500 to 1500 Å is formed on the gate oxide film 12 using SiH 4 gas of 100 to 200 SCCM.
다음으로, 도 2b에 도시된 바와 같이 비정질 실리콘층(13) 상에 p+폴리 마스크(14)를 형성하고, 이를 이온주입 마스크로 사용하여 BF2이온주입 공정을 실시한다. 이때, 이온주입 에너지는 비정질 실리콘층(13)의 두께를 고려하여 10keV∼100keV 정도로 하고, 도즈는 1×1012ions/cm2∼1×1014/cm2정도로 한다.Next, as shown in FIG. 2B, a p + poly mask 14 is formed on the amorphous silicon layer 13, and the BF 2 ion implantation process is performed using the p + poly mask 14 as an ion implantation mask. At this time, the ion implantation energy is about 10keV to 100keV in consideration of the thickness of the amorphous silicon layer 13, and the dose is about 1x10 12 ions / cm 2 to 1x10 14 / cm 2 .
이어서, 도 2c에 도시된 바와 같이 역시 p+폴리 마스크(14)를 이온주입 마스크로 사용하여 B 이온주입 공정을 실시한다. 이때, 이온주입 에너지는 비정질 실리콘층(13)의 두께 및 BF2이온주입 공정을 고려하여 2keV∼20keV 정도로 하고, 도즈는 1×1012ions/cm2∼1×1014ions/cm2정도로 한다.Subsequently, a B ion implantation process is performed using p + poly mask 14 as an ion implantation mask as shown in FIG. 2C. At this time, the ion implantation energy is about 2keV to 20keV in consideration of the thickness of the amorphous silicon layer 13 and the BF 2 ion implantation process, and the dose is about 1 × 10 12 ions / cm 2 to 1 × 10 14 ions / cm 2 . .
이어서, 도 2d에 도시된 바와 같이 p+폴리 마스크(14)를 제거하고, 비정질 실리콘층(13) 상에 게이트 전극 마스크를 형성하고, 이를 식각 마스크로 사용하여 비정질 실리콘층(13) 및 게이트 산화막(12)을 선택 식각함으로써 게이트를 패터닝한다. 이때, 실리콘 기판(10)의 손상(damage)을 방지하기 위해 게이트 산화막(12)의 일정 두께를 잔류시킨다. 이후, 열처리를 실시하여 실리콘(Si)의 결정립계 성장을 유도함으로써 비정질 실리콘층(13)을 폴리실리콘으로 상변환시키고, 불순물 분포를 안정화한다. 이때, 열처리를 별도로 실시하지 않고, 후속 공정시의 고온 공정을 이용할 수 있다.Subsequently, as shown in FIG. 2D, the p + poly mask 14 is removed, the gate electrode mask is formed on the amorphous silicon layer 13, and the amorphous silicon layer 13 and the gate oxide film are used as an etching mask. The gate is patterned by selective etching of (12). At this time, in order to prevent damage of the silicon substrate 10, a predetermined thickness of the gate oxide layer 12 is left. Thereafter, heat treatment is performed to induce grain growth of silicon (Si), thereby converting the amorphous silicon layer 13 into polysilicon and stabilizing the impurity distribution. At this time, the high temperature process at the time of a subsequent process can be used, without performing heat processing separately.
첨부된 도면 도 3a는 전술한 본 발명의 일 실시예에 따라 비정질 실리콘에 BF2및 B 이온주입을 차례로 실시한 직후의 비정질 실리콘층에서의 붕소(B) 농도 프로파일을 도시한 그래프로서, 도시된 바와 같이 비정질 상태에서 붕소는 비정질 실리콘층의 중간 깊이 부분에서 그 농도가 가장 높게 나타났고, 하단부로 갈수록 그 농도가 줄어들게 된다.3A is a graph showing a boron (B) concentration profile in an amorphous silicon layer immediately after sequentially performing BF 2 and B ion implantation into amorphous silicon according to one embodiment of the present invention described above. In the amorphous state, the concentration of boron is highest in the middle portion of the amorphous silicon layer, and the concentration decreases toward the lower portion.
첨부된 도면 도 3b는 전술한 본 발명의 일 실시예에 따라 실리콘 결정립계 성장 및 열처리 공정후 폴리실리콘층에서의 붕소의 농도 프로파일을 도시한 그래프로서, 도시된 바와 같이 BF2에 포함된 불소 원자에 의해 붕소의 확산이 증진되고, 붕소(B)가 일정 농도의 기울기를 가지다가 결국 확산 원리에 의해 균일한 분포를 가지게 된다.Figure 3b is a graph showing the concentration profile of boron in the polysilicon layer after the silicon grain growth and heat treatment process according to an embodiment of the present invention described above, as shown in the fluorine atoms contained in BF 2 As a result, the diffusion of boron is promoted, and boron (B) has a constant concentration gradient, and eventually has a uniform distribution by the diffusion principle.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
전술한 본 발명은 비정질 폴리실리콘층을 증착한 상태에서 BF2및 B 이온주입을 차례로 수행함으로써 종래와 같이 붕소만을 이온주입한 경우보다 폴리실리콘층에서의 균일한 농도 프로파일을 얻을 수 있으며, 이로 인하여 게이트 공핍에 의한 유효 게이트 산화막의 두께 증가를 방지할 수 있다. 또한 본 발명은 종래 BF2만을 주입하는 경우에 비해 상대적으로 BF2의 도즈량을 줄임으로써 불소가 게이트 산화막 내로 유입되는 양을 현격히 감소시킬 수 있으므로 게이트 산화막의 특성을 열화시키는 것을 방지할 수 있다.In the present invention described above, by uniformly performing BF 2 and B ion implantation in the state of depositing the amorphous polysilicon layer, a uniform concentration profile in the polysilicon layer can be obtained than in the case where only boron is ion implanted as in the related art. The increase in the thickness of the effective gate oxide film due to the gate depletion can be prevented. In addition, the present invention can significantly reduce the amount of fluorine introduced into the gate oxide film by reducing the dose of BF 2 relative to the case where only the conventional BF 2 is injected, thereby preventing deterioration of the characteristics of the gate oxide film.
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