KR20000003348A - Clock signal converting circuit - Google Patents

Abstract

PURPOSE: A clock signal converting circuit is provided to originally prevent the narrow pulse generated when converting the movement frequency. CONSTITUTION: The clock signal converting circuit comprises: a D flip flop(FF3) accepting a frequency selecting signal(Freq_sel) by responding to a standard clock signal(Freq_B); a D flip flop(FF2) accepting the output(QB) of the D flip flop(FF3) by responding to a standard clock signal(Fre_A); and a D flip flop(FF1) accepting the output(Q) of the D flip flop(FF2) by responding to the standard clock signal(Freq_A).

Description

Clock signal switching circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing techniques, and more particularly to clock signal switching circuits used in various systems that support multiple operating frequencies, such as IC card readers / writers.

Currently, IC cards for storing, encrypting and processing electronic resident cards, prepaid cards and debit cards, and various information that are the basis of electronic money are mostly embedded with memory and central processing unit (CPU) blocks. There is no international standardization. Since there is a part that has not yet been standardized, latecomers have no choice but to focus on compatibility with existing products when developing new products. In particular, the operating frequency of the IC card is a representative example. The operating frequencies of the central processing unit block currently mounted inside the IC card are 4.9152 MHz and 3.579545 MHz. Therefore, all of these operating frequencies must be supplied to the IC card reader / writer. For this purpose, an additional clock signal switching circuit must be employed for the reader / writer of the IC card.

For this reason, IC card readers / writers are equipped with clock oscillator circuits for each operating frequency to provide different operating frequencies. Typically, when an IC card is inserted into a reader / writer, the reader / writer selects and provides a signal of a rated operating frequency of the inserted IC card.

Conventionally, a clock signal switching circuit as shown in FIG. 1 is used for the above-described operation.

The illustrated conventional clock signal switching circuit receives three frequency selection signals A and two reference clock signals B and C as inputs and outputs three reference clock signals O by the frequency selection signal A. NAND gate NAND1. It is designed using NAND2, NAND3 and one inverter Inv1. Looking at the output signal at the time when the frequency selection signal A changes to an appropriate value, since the frequencies of the two reference clock signals B and C are different, the reference clock is applied to the output signal in the period where the frequency selection signal A transitions. There are narrow pulses relative to the signal. Such narrow pulses can cause a malfunction of the central processing unit present in the IC card.

In order to solve this problem, a reset signal is generated in a section in which the frequency selection signal transitions to prevent a possible malfunction. However, it is not a method of eliminating the cause of the malfunction inherently, and the reset operation not only increases the load on the software of the IC card and the IC card reader / writer, but also increases the processing time.

It is an object of the present invention to provide a clock signal switching circuit that prevents a narrow pulse generated at the time of operating frequency switching in various systems supporting multiple operating frequencies.

1 is a conventional clock signal switching circuit.

2 is a clock signal switching circuit according to an embodiment of the present invention.

3 is a clock signal switching circuit according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

FF1, FF2, FF3: D flip flop

NAND21, NAND22, NAND23: NAND Gate

Inv21, Inv22: Inverter

Freq_A, Freq_B: Reference Clock Signal

Freq_sel: Frequency selection signal

Freq_sel_sync_A, Freq_sel_sync_B: Synchronized frequency selection signal

The present invention does not directly output one of a plurality of reference clock signals having different frequencies when the frequency selection signal transitions, but after a point in time at which the frequency selection signal is synchronized to each reference clock signal. The clock signal switching circuit is implemented to output the converted rated clock signal to eliminate the narrow pulse generation.

There is a characteristic clock signal switching circuit provided from the above-described technical principle of the present invention.

Hereinafter, embodiments of the present invention will be introduced for easy and preferred practice of the present invention.

2 is a view illustrating a clock signal switching circuit according to an exemplary embodiment of the present invention. Hereinafter, the circuit configuration and operation thereof will be described.

The illustrated clock signal switching circuit receives the frequency selection signal Freq_sel and two reference clock signals Freq_A (4.9152 MHz) and Freq_B (3.579545 MHz) as inputs and outputs the reference clock signal IC_ref of the IC card. The reference clock signals Freq_A and Freq_B are the outputs of the respective clock oscillators existing inside the IC card reader / writer.

The clock signal switching circuit includes a D flip-flop FF3 for receiving the frequency selection signal Freq_sel in response to the reference clock signal Freq_B, and a D flip-flop FF2 for receiving the output QB of the D flip-flop FF3 in response to the reference clock signal Freq_A. And a D flip-flop FF3 that receives the output Q of the D flip-flop FF2 in response to the reference clock signal Freq_A. The D flip-flops FF1 and FF2 use the power supply voltage Vdd and the frequency selection signal Freq_sel as a preset signal and a clear signal, respectively. The D flip-flop FF3 uses the power supply voltage Vdd as a preset signal and a clear signal.

In addition, the clock signal switching circuit includes the NAND gate NAND21 which inputs the output signal of the D flip-flop FF2 and the inverted signal of the reference clock signal Freq_A, and the inversion of the output QB of the D flip-flop FF3 and the reference clock signal Freq_B. A NAND gate NAND22 that takes a signal as an input, and a NAND gate NAND23 that takes an output of the NAND gates NAND21 and NAND22 as inputs, outputs the reference clock signal IC_ref of the IC card. Unexplained reference numerals Inv21 and InV22 represent inverters, respectively.

The detailed operation of this circuit is as follows.

First, when the frequency selection signal Freq_sel is at the logic level 'high' while the reference clock signals Freq_A and Freq_B are continuously input, the output QB of the D flip-flop FF3 becomes 'low' and the NAND inputting this value. The gate NAND22 outputs 'high' regardless of the reference clock signal Freq_B. That is, the NAND gate NAND22 is closed with respect to the reference clock signal Freq_B. In addition, the NAND gate NAND21 having the output QB 'high' of the D flip-flop FF2, which is a frequency selection signal Freq_sel_sync-A synchronized with the reference clock signal Freq_A, inverts the inverted signal of the remaining reference clock signal Freq_A again. As a result, the NAND gate NAND3 outputs the inverted signal of the reference clock signal Freq_A as the reference clock signal IC_ref of the IC card.

If the frequency selection signal Freq_sel is a logic level 'low', the output QB of the D flip-flop FF3 becomes 'high', and thus the output (QB) of the D flip-flop FF3 that is the frequency selection signal Freq_ref_sync_B synchronized with the reference clock signal Freq_B. 'High' is inputted to the D flip-flop FF1, and the output (QB) of the D flip-flop FF2, which has its output (Q) as the input, becomes 'low'. It will print 'high' regardless. In other words, the NAND gate NAND21 is closed with respect to the reference clock signal Freq_A. In addition, since the frequency selection signal Freq_ref_sync_B synchronized with the reference clock signal Freq_B maintains a high value, the NAND gate NAND22 inverts and outputs the inverted signal of the remaining reference clock signal Freq_B. Thus, the NAND gate NAND23 is an IC card. The inverted signal of the reference clock signal Freq_B is output as the reference clock signal IC_ref.

In the clock signal switching circuit as described above, even when the frequency selection signal Freq_sel transitions at any point in time, the rated clock signal which has been switched since being synchronized with the reference clock signal Freq_A or Freq_B is output, so that the reference clock signal IC_ref of the IC card is A narrow pulse that causes a malfunction of the internal CPU is delivered to the IC card with its source removed. This eliminates the need to perform an unnecessary reset operation on the IC card, thereby reducing the load and processing time of the software.

3 is a view illustrating a clock signal switching circuit according to another embodiment of the present invention, in which the clock signal switching circuit receives the frequency selection signal Freq_sel inverted by the inverter Inv31 in response to the reference clock signal Freq_A. D flip-flop FF4 and D flip-flop FF5 for receiving the frequency selection signal Freq_sel in response to the reference clock signal Freq_B. In addition, the clock signal switching circuit uses a NAND input signal having a frequency selection signal Freq_sel inverted signal, a reference clock signal Freq_A inverted signal, and a frequency selection signal Freq_sel_sync_A (output of D flip-flop FF4) synchronized with the reference clock signal Freq_A. NAND gate NAND32 to which the frequency selection signal Freq_sel, the reference clock signal Freq_B, and the frequency selection signal Freq_sel_sync_B (output Q of D flip-flop FF4) are input as the inputs of the gate NAND31, and the NAND gates NAND31 and NAND32. And a NAND gate NAND33 for receiving the output of the IC card and outputting the reference clock signal IC_ref of the IC card.

The operation of the clock signal switching circuit shown is as follows.

First, when the logic level 'high' is input to the frequency selection signal Freq_sel, the D flip-flop FF4 outputs (Q) the frequency selection signal Freq_sel_sync_A synchronized with the reference clock signal Freq_A as 'low', so that the NAND gate NAND31 has the reference clock signal Freq_A. D flip-flop FF5 outputs (Q) the frequency selection signal Freq_sel_sync_B synchronized to the reference clock signal Freq_B as 'high' so that the NAND gate NAND32 inverts the reference clock signal Freq_B and outputs the result, thus eventually NAND gate NAND33. Outputs the reference clock signal Freq_B as the reference clock signal IC_Ref of the IC card.

Similarly, when a logic level 'low' value is applied to the frequency selection signal Freq_sel, the reference clock signal Freq_A is output as the reference clock signal IC_Ref of the IC card.

This clock signal switching circuit also outputs the rated clock signal which has been switched since the synchronization with the reference clock signal Freq_A or Freq_B, even if the frequency selection signal Freq_sel transitions at any point. Therefore, the reference clock signal IC_ref of the IC card is The narrow pulse that causes the malfunction is delivered to the IC card with the original source removed.

In the above-described embodiment, the IC card reader / writer having two clock oscillators has been described as an example, but a clock signal switching circuit that outputs a rated clock signal among three or more reference clock signals can be implemented by simple modification of the circuit. The present invention can be applied to various systems supporting multiple operating frequencies other than the IC card reader / writer.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, since the present invention does not require an additional reset operation, the load of the driving software of the IC card can be reduced, and the processing time can be significantly reduced.

Claims (10)

A second plurality of reference clock signals having different frequencies and a first frequency selection signal for selecting a rated clock signal among the plurality of reference clock signals, the second frequency being selectively synchronized with any one of the plurality of reference clock signals; Frequency selection signal synchronizing means for outputting a frequency selection signal; And An output stage outputting any one of the plurality of reference clock signals as the rated clock signal in response to the plurality of reference clock signals and the second frequency selection signal; Clock signal switching circuit comprising a. The method of claim 1, The frequency selection signal synchronization means, And a plurality of synchronization circuits for outputting each of the second frequency selection signals synchronized with each of the plurality of reference clock signals. The method of claim 2, Each of the plurality of synchronization circuit units, And a flip-flop means for outputting the second frequency selection signal by using any one of the plurality of reference clock signals as a clock input and the first frequency selection signal as a data input. The method of claim 3, wherein And the flip-flop is a D flip-flop. The method according to claim 3 or 4, And the output terminal comprises negative logic means for inputting any one of the plurality of reference frequency selection signals and the second frequency selection signal synchronized with the signal. The method according to any one of claims 1 to 4, And said plurality of reference clock signals are signals respectively output from a plurality of clock oscillators in an IC card reader / writer. A first and second reference clock signals having different frequencies and a first frequency selection signal for selecting a rated clock signal among the first and second reference clock signals as inputs and outputting the rated clock signal; In the switching circuit, First synchronization means for receiving the first frequency selection signal in response to the first reference clock signal and outputting a second frequency selection signal synchronized with the first reference clock signal; Second synchronization means for receiving the second frequency selection signal in response to the second reference clock signal and outputting a third frequency selection signal synchronized with the second reference clock signal; An output stage configured to receive the second and third frequency selection signals and the first and second reference clock signals and output the rated clock signal; Clock signal switching circuit comprising a. The method of claim 7, wherein Each of the first and second synchronization means, A clock signal switching circuit comprising at least one flip-flop. The method of claim 8, The second synchronization means, A first D flip-flop that uses the second reference clock signal as a clock input and uses the second frequency selection signal as a data input; And a second D flip-flop having the second reference clock signal as a clock input and an output of the first D flip-flop as a data input. The method according to any one of claims 7 to 9, The output stage, First negative logical means for inputting the first reference clock signal and the second frequency selection signal; Second negative logical means for inputting the second reference clock signal and the third frequency selection signal; And And a third AND function for receiving the outputs of the first and second negative logical means.