KR20000003055A - Nonvolatile memory device having improved floating gate coupling ratio and its fabricating method - Google Patents

Abstract

PURPOSE: The device improves the coupling ratio of a floating gate and has an active region with flat surface to maintain the capacitance constantly between the floating gate and a channel. CONSTITUTION: The device is formed on a semiconductor substrate(100) in an active region and is formed continuously in one region, and comprises a gate insulation film(130a, 130b) having a different thickness in a center region and in an edge region of the active region. The gate insulation film in the edge region of the active region adjacent to a field oxide(120) is formed thickly to prevent tunneling and is formed so thick that tunneling can be occurred.

Description

Nonvolatile Memory Device With Improved Floating Gate Coupling Ratio And Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same, wherein the gate coupling ratio is improved by a simple manufacturing method and the surface of the active region where tunneling is generated is flat.

Nonvolatile memory, such as flash memory, generally includes a transistor comprising a gate electrode, a source, and a drain, each consisting of a floating gate and a control gate. Configure memory cells. Here, the floating gate serves to store data, and the control gate formed through the interlayer insulating layer on the floating gate controls the floating gate.

FIG. 1 is a plan view of a conventional nonvolatile memory cell as mentioned above, wherein reference numeral “P1” denotes a mask pattern for forming a field oxide film, “P2” denotes a mask pattern for forming a floating gate, and “P3” denotes a control gate. The mask pattern for formation is shown, respectively.

2A and 2B are cross-sectional views taken along line 2a-2a 'and 2b-2b' of FIG. 1.

2A and 2B, in a conventional nonvolatile memory cell, a gate insulating film 30 is formed on a surface of a semiconductor substrate 10, and a floating gate 40 is formed thereon. The control gate 60 is formed on the floating gate 40 via an interlayer insulating film 50, for example, an ONO (Oxide / Nitride / Oxide) film. The floating gate 40 is electrically floating, and the surroundings thereof are insulated by the field oxide film 20. Therefore, when charge is injected into the floating gate 40 through the gate insulating film 30 between the adjacent field oxide film 20, the charge remains semi-permanently in the floating gate 40.

The operation of a general nonvolatile memory cell as shown in FIGS. 2A and 2B is achieved by controlling the voltage of the control gate 60 to change the amount of charge in the floating gate 40. For example, an erase operation that draws electrons from the floating gate 40 to a source (not shown), drain (not shown), and bulk (channel) to lower the cell's threshold voltage (V _TH ), A program operation that increases the threshold voltage of the cell by injecting electrons into the floating gate using a gate potential higher than the source potential, and a read operation that reads the erase state and the program state of the cell. have.

In the operation of such a nonvolatile memory cell, the coupling ratio of the floating gate is an important parameter for determining the voltage applied to the control gate 60. The coupling ratio of the floating gate represents the voltage dependence induced on the floating gate with respect to the voltage applied to the control gate, and the larger the value, the larger the floating gate voltage induced by the lower control gate voltage is, thereby improving the program efficiency. do. That is, when the coupling ratio of the floating gate is large, even if the boosting voltage applied to the control gate is lowered, sufficient voltage for the program can be applied to the floating gate, thereby reducing the boosted voltage level. Reducing the boost voltage level reduces the breakdown voltage that an individual transistor must withstand and improves the reliability of the nonvolatile memory device. Therefore, it is desirable to make the coupling ratio of the floating gate as large as possible, and studies on this have been conducted.

The coupling ratio of the floating gate is generally determined by the capacitance generated by the control gate-interlayer insulating film-floating gate and the capacitance generated by the floating gate-gate insulating film-channel, and is proportional to the capacitance by the interlayer insulating film. It is known that it is inversely proportional to the capacitance caused by the gate insulating film.

In order to increase the floating gate coupling ratio, a method of reducing the thickness of the interlayer insulating film or increasing the thickness of the gate insulating film has been studied. However, reducing the thickness of the interlayer insulating film is a data retention, a program of a nonvolatile device. The insulation breakdown of the interlayer insulating film may be caused during the operation and the erase operation, and the increase in the thickness of the gate insulating film may reduce the efficiency of the program operation or the erase operation.

In addition, according to the related art, a problem may occur in that the reliability of the nonvolatile device is deteriorated by the surface bending of the active region as the device is highly integrated. For example, when a field oxide film is formed by a local oxidation (LOCal Oxidation of Silicon) process, the surface of the active region becomes uneven due to bird's beak penetrating into the active region, resulting in a gap between the floating gate and the channel. The capacitance of is not constant. This change in capacitance is more severe as the device is highly integrated, which is a factor that reduces the reliability of the nonvolatile memory device.

Accordingly, an object of the present invention is to provide a nonvolatile memory device having an improved coupling ratio of a floating gate.

Another object of the present invention is to provide a nonvolatile memory device having a flat surface of an active region so that the capacitance between the floating gate and the channel is kept constant.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the nonvolatile memory device.

1 is a plan view of a conventional nonvolatile memory cell.

2A and 2B are cross-sectional views taken along line 2a-2a 'and 2b-2b' of FIG. 1.

3 is a plan view of a main part of a nonvolatile memory device according to a preferred embodiment of the present invention.

4A and 4B are cross-sectional views illustrating 4a-4a 'and 4b-4b' of FIG. 3.

5 through 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention, according to a process sequence.

<Explanation of symbols for main parts of the drawings>

100: semiconductor substrate, 120: field oxide film

130a and 130b: gate insulating film, 150: floating gate

160: interlayer insulating film, 170: control gate

In accordance with another aspect of the present invention, a nonvolatile memory device includes a semiconductor substrate divided into an active region and an isolation region, a field oxide film repeatedly formed on one surface of the semiconductor substrate in the isolation region, and an active region A gate insulating film formed on the surface of the semiconductor substrate within the semiconductor substrate and continuously formed in a predetermined region and extending from a top surface of the gate insulating film to a partial region of the adjacent field oxide film, the gate insulating film having a different thickness at the center and the edge of the active region; And an interlayer insulating film formed on the field oxide film between the floating gate and the adjacent floating gate, and a control gate formed on the interlayer insulating film and controlling the floating gate.

The gate insulating layer is formed to have a thickness such that tunneling of electrons can occur in the center of the active region, and is thick enough to prevent tunneling of electrons at the edge of the active region, and the gate insulating layer is formed to have a thickness of 50 kPa to 1000 kPa.

When the device isolation layer is formed by a local oxidation (LOCOS) process, an edge portion of the active region includes a buzz big region of the device isolation layer.

The gate insulating film is also formed continuously in a string formed by connecting a plurality of memory cells in series, and the gate insulating film is composed of an oxide film or an oxynitride.

In accordance with another aspect of the present invention, a method of manufacturing a nonvolatile memory device includes forming an insulating film on a semiconductor substrate divided into an active region and an isolation region, and then forming a material layer pattern to be limited to a surface of the isolation layer. In addition, a spacer having a predetermined width is formed on sidewalls of the material layer pattern so that an edge portion of the active region adjacent to the isolation layer is covered and the center portion is exposed. The spacer is used as an etch mask, the insulating layer positioned at the center of the active region is etched, and the spacer and the material layer pattern are removed. Subsequently, a gate insulating film having a different thickness from the center and the edge of the active region is formed, and a gate pattern including a floating gate, an interlayer insulating layer, and a control gate is formed on the gate insulating film.

Here, the method of removing the central insulating film may use dry and wet etching in consideration of the pitting of the surface.

The insulating layer is formed by a thermal oxidation process, and the material layer pattern and the spacer are formed of silicon nitride.

As described above, in the nonvolatile memory device according to the preferred embodiment of the present invention, the thickness of the gate oxide layer is formed differently in the active region. That is, the edge portion of the active region adjacent to the field oxide film is formed to be thick enough so that tunneling does not occur, and the center portion is formed to have a thickness such that tunneling can occur.

As a result, according to the present invention, the coupling ratio of the floating gate can be increased by reducing the area of the tunneling oxide film in which tunneling is generated by a simple process, and the surface of the active region in which tunneling is generated can be kept flat, thereby making it nonvolatile. It is possible to improve the reliability of the memory device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and only the embodiments of the present invention may be completed by the present invention to those skilled in the art. It is provided to fully inform the category. In the embodiments disclosed below, when either film is referred to as being on another film or substrate, it is noted that it may be directly over the other film or substrate and an interlayer film may be present.

3 is a plan view of a main part of a nonvolatile memory device according to an exemplary embodiment of the present invention, in which reference numeral “M1” denotes a mask pattern for defining an active region and an isolation region, and “M3” denotes a floating gate formation. For example, "M4" shows a mask pattern for forming a control gate, and "M2" shows a region where a gate insulating film for tunneling is formed.

According to the mask patterns of FIG. 3, the gate insulating film in which the tunneling is generated is formed to be parallel to the field oxide film formed by the mask pattern M1 so as to intersect the floating gate and the control gate formed by the mask patterns M3 and M4. do. The gate insulating film in which tunneling is generated is also continuously formed in one string in which a plurality of cell transistors are connected in series, for example in the case of a NAND type nonvolatile device.

4A and 4B are cross-sectional views illustrating 4a-4a 'and 4b-4b' of FIG. 3.

4A and 4B, reference numeral 100 denotes a first oxide type, for example, P-type semiconductor substrate, and 120 denotes a field oxide film for dividing the semiconductor substrate into an active region and an isolation region. "130a and 130b" represent a gate insulating film, "150" a floating gate, "160" an interlayer insulating film, and "170" a control gate, respectively.

According to the cross-sectional view, the control gate 170 is sequentially stacked on the semiconductor substrate 100 with the floating gate 150 through which electrons can be injected and the interlayer insulating film 160 having a predetermined thickness interposed therebetween. Gate insulating layers 130a and 130b are formed between the floating gate 150 and the semiconductor substrate 100.

The interlayer insulating layer 160 may be, for example, an ONO structure stacked with an oxide film, a nitride film, and an oxide film, and the gate insulating films 130a and 130b may be formed of an oxide film or an oxynitride film, and the floating gate 150 may be formed. The control gate 170 may be formed of polysilicon doped with impurities as in the general case.

The gate insulating layers 130a and 130b may be formed by, for example, a thermal oxidation process, and may be formed not only below the floating gate 150 but also between adjacent floating gates 150. That is, the gate insulating layers 130a and 130b according to the embodiment of the present invention are formed to be parallel to the field oxide layer 120 in the active region 110 forming one string, as shown in the plan view of FIG. 3. It is formed continuously.

The gate insulating layers 130a and 130b according to the preferred embodiment of the present invention are also formed in different thicknesses at the center portion 130a and the edge portion 130b of the active region. The gate insulating layer 130a at the center of the active region is formed to have a thickness at which electron tunneling can occur, for example, a thickness of about 40 GPa to 100 GPa. The gate insulating film 130b at the edge of the active region does not generate electron tunneling. It is formed so thick that it is not thick, for example, about 150-1000 mm thick. Therefore, in the nonvolatile device according to the present invention, the gate insulating film in which tunneling is generated is limited to the gate insulating film 130a positioned at the center thereof. For convenience, in the following description, the gate insulating layer 130a positioned at the center and generating tunneling will be referred to as a tunneling oxide film.

In general, in the nonvolatile device, the coupling ratio γ of the floating gate is represented by Equation 1 below.

In the formula, γ denotes the coupling ratio of the floating gate, Cono denotes the capacitance due to the interlayer insulating film, and Ctun denotes the tunneling capacitance, each of which can be expressed as follows.

Cono = (εox / Tono) × Aono

Ctun = (εox / Ttun) × Atun

Where εox is the dielectric constant of the interlayer insulating film 160 and the tunneling oxide film 130a, Tono and Ttun are the thicknesses of the interlayer insulating film 160 and the tunneling oxide film 130a, respectively, and Aono and Atun are the interlayer insulating film 160 and The area of the tunneling oxide film 130a is shown.

According to Equation 1, it can be seen that the coupling ratio γ of the floating gate is affected by the tunneling capacitance Ctun expressed as a function of the thickness and area of the tunneling oxide film 130a. That is, as the area Atun of the tunneling oxide film is smaller, the tunneling capacitance Ctun is decreased and the coupling ratio γ of the floating gate is increased.

In the nonvolatile memory device configured as shown in FIGS. 3 to 4B, the tunneling oxide layer 130a is limited to a region where actual tunneling occurs, that is, an area that affects the tunneling capacitance Ctun. Therefore, since the area of the tunneling oxide film is reduced compared with the prior art, it is possible to obtain an effect of reducing the tunneling capacitance (Ctun) that directly affects the coupling ratio (γ) of the floating gate. That is, according to the present invention, the tunneling capacitance (Ctun) is reduced to increase the coupling ratio (γ) of the floating gate.

According to the present invention, the gate oxide film 130b formed on both sides of the tunneling oxide film 130a and including the buzz big is excluded during the actual tunneling operation. That is, since tunneling does not occur through the gate oxide layer 130b positioned at the edge of the active region, the conventional problem that the capacitance between the floating gate 150 and the channel is not constant due to buzz big is solved. Therefore, the surface of the active region where tunneling is generated can be obtained with a flat effect.

Meanwhile, in FIG. 4B, the surface of the field oxide layer 120 is etched when the control gate 170, the interlayer insulating layer 160, and the floating gate 150 are etched.

5 through 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention, according to a process sequence.

Referring to FIG. 5, a field oxide film 120 is formed on a surface of a first conductive semiconductor substrate 100, for example, a P-type silicon substrate, for example, by a local oxidation (LOCOS) process, thereby forming an active region and an isolation region. To qualify. Thereafter, an insulating film, for example, the first oxide film 125 obtained by the thermal oxidation process is formed to a thickness of about 500 kPa or less. The first oxide layer 125 is formed to prevent damage to the surface of the active region due to an etching process which is performed later.

Referring to FIG. 6, an insulating material, for example, silicon nitride, is deposited on the resultant on which the first oxide film 125 is formed, and then patterned to form an insulating film pattern 127 defined on the field oxide film 120.

Referring to FIG. 7, a second oxide film 129 obtained by, for example, a thermal oxidation process is formed on the resultant formed with the insulating film pattern 127 to a thickness of about 300 kPa to 500 kPa, and an insulating material such as silicon is formed on the entire surface of the resultant. The nitride is deposited and then anisotropically etched to form spacers 140 on sidewalls of the insulating film pattern 127. Thereafter, the spacer 140 is used as a mask to etch a portion of the second oxide layer 130 formed on the surface of the active region. Accordingly, the second oxide layer 129 remains thinner at the center of the active region than at the edge of the active region positioned below the spacer 140.

The spacers 140 formed at both edges of the active region reduce the area of the active region where tunneling occurs, that is, the area of the tunneling oxide layer. That is, since the width in one direction for determining the active area area is reduced by the spacer width x 2, the area of the tunneling oxide film is reduced.

In addition, the spacer 140 serves to planarize the surface of the active region where tunneling occurs. That is, by forming the spacer 140 to such an extent that the buzz big of the field oxide film formed by the local oxidation process is masked, the buzz big is removed from the tunneling oxide film, and is used for electron tunneling in the program operation or the erase operation of the nonvolatile memory device. Since there is no effect, the surface of the active region can be obtained with a flat effect.

In the present exemplary embodiment, the second oxide film 129 is formed in a state where the first oxide film 125 shown in FIG. 6 is not removed. However, the second oxide film 129 is completely removed after the first oxide film 125 is completely removed. It may be formed.

Referring to FIG. 8, the nitride layer pattern 127 and the spacer 140 are removed in a conventional manner, and then the semiconductor substrate 100 positioned at the center of the active region, that is, the portion where the tunneling is to be generated, is exposed. The oxide film 129 is etched. Thereafter, gate insulating films 130a and 130b obtained by, for example, a thermal oxidation process are formed on the surface of the active region, and then a conductive material such as polysilicon doped with impurities is deposited and patterned in one direction. The floating gate 150 is formed.

By etching the second oxide layer 129, the second oxide layer does not exist in the center of the active region where tunneling is to be generated, and the second oxide layer exists in a predetermined thickness only at the edge of the active region where the spacer is located. When the gate insulating film is formed in this state, the thickness of the gate insulating film formed at the center and the edge of the active region is different.

The gate insulating layer 130a at the center of the active region is thick enough to generate electron tunneling during programming and erasing operation of the nonvolatile memory device, for example, 50 μs to 100 μs, and the thickness of the gate insulating layer at the edge portion is tunneling. It is preferable to form it so thick that it does not generate | occur | produce it, for example in thickness of 150 micrometers-1000 micrometers.

In the present exemplary embodiment, a portion of the second oxide layer 130 located at the center of the active region is left in the etching process using the spacer 140 as an etching mask, and the spacer 140 is completely removed after the spacer 140 is removed. Before the removal, the second oxide layer 130 positioned at the center of the active region may be completely removed using only a dry etching process using the spacer 140 as a mask or a combination of a dry etching process and a wet etching process.

Referring to FIG. 9, for example, an oxide film / nitride film / oxide film is sequentially stacked on the entire surface of the resultant product in which the floating gate 150 is formed to form an interlayer insulating film 160 having an ONO structure. The control gate 170 is formed by depositing and patterning polysilicon doped with impurities, for example, on the entire surface of the resultant layer on which the interlayer insulating layer 160 is formed. When the control gate 170 is patterned, the interlayer insulating film and the floating gate in the word line direction are also patterned at the same time.

The subsequent process follows the usual process.

As described above, in the nonvolatile memory device according to the preferred embodiment of the present invention, the thickness of the gate oxide layer is formed differently in the active region. That is, the edge portion of the active region adjacent to the field oxide film is formed to be thick enough so that tunneling does not occur, and the center portion is formed to have a thickness such that tunneling can occur. Therefore, since the area of the tunneling oxide film is reduced as compared with the related art, the tunneling capacitance is reduced and the coupling ratio of the floating gate is increased. As a result, it is possible to apply a low voltage to the control gate, thereby reducing the breakdown voltage that the individual transistors have to withstand and improving the reliability of the nonvolatile memory device.

In addition, since the gate oxide film including the buzz big on both sides of the tunneling oxide film is excluded during the actual tunneling operation, the surface of the active region in which the tunneling occurs is flat, unlike the conventional case in which the capacitance between the floating gate and the channel is not constant due to the buzz big. The effect can be obtained.

The present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

Claims (13)

In a nonvolatile memory device capable of electrically erasing and storing data, A semiconductor substrate divided into an active region and an isolation region; An isolation layer formed repeatedly on one surface of the semiconductor substrate in the isolation region; A gate insulating film formed on the surface of the semiconductor substrate in the active region, continuously formed in the predetermined region, and having a different thickness at the center and the edge of the active region; A floating gate extending from an upper surface of the gate insulating film to a portion of a neighboring device isolation film; An interlayer insulating layer formed on the device isolation layer between the floating gate and the adjacent floating gate; And And a control gate formed on the interlayer insulating layer and controlling the floating gate. The nonvolatile memory device of claim 1, wherein the gate insulating layer has a thickness at which the electron tunneling occurs at the center of the active region, and is thick enough to prevent tunneling of the electron at the edge of the active region. The nonvolatile memory device of claim 1, wherein the device isolation layer is formed by local oxidation (LOCOS). The nonvolatile memory device of claim 3, wherein an edge portion of the active region includes a buzz big region of the device isolation layer. The nonvolatile memory device of claim 1, wherein the gate insulating layer has a thickness of about 50 μs to about 1000 μs. The nonvolatile memory device of claim 1, wherein the gate insulating layer is continuously formed in a string in which a plurality of memory cells are connected in series. The nonvolatile memory device of claim 1, wherein the gate insulating layer is formed of an oxide layer or an oxynitride layer. In the method of manufacturing a nonvolatile memory device capable of electrically erasing and storing data, Forming a material layer pattern so as to be limited to the surface of the device isolation layer of the semiconductor substrate divided into the active region and the device isolation region; Selectively forming an insulating film on the surface of the active region; Forming a spacer having a predetermined width on a sidewall of the material layer pattern to cover an edge of an active region adjacent to an isolation layer and expose a central portion thereof; A fourth step of using the spacer as an etching mask and etching only a predetermined thickness of the insulating layer positioned at the center of the active region; Removing the spacers and the material layer pattern; Etching the insulating layer until the surface of the semiconductor substrate positioned at the center of the active region is exposed; A seventh step of forming a gate insulating film having a different thickness from a center portion and an edge portion of the active region on the resultant product; And And forming an gate pattern including a floating gate, an interlayer insulating layer, and a control gate on the gate insulating layer. The method of claim 8, wherein in the seventh step, the gate insulating film is formed to a thickness such that tunneling of electrons can be generated in the center of the active region, and so thick that no tunneling of electrons occurs at the edge of the active region. Nonvolatile Memory Device. The method of claim 8, wherein the insulating layer is formed by a thermal oxidation process in a second step. The method of claim 8, wherein the material layer patterns and the spacers formed in the first and third steps are formed of silicon nitride. The method of claim 8, wherein in the fourth step, the insulating layer is etched so as to have a thickness of 500 μm or less. The method of claim 8, wherein before the first step of forming the material layer pattern, A method of manufacturing a nonvolatile memory device, the method further comprising: forming a thermal oxide film on a resultant device on which a device isolation film is formed so as to prevent damage to an active region surface.