KR20000001570U - Scan decoder with one input - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a scan decoder having one input.

2. The technical problem the invention is trying to solve

An object of the present invention is to provide a scan decoder having one input having an OR gate and a delay flip-flop therein to receive only one input and perform the same function as a conventional scan decoder.

3. Summary of the solution of the present invention

The present invention includes buffer means for buffering and outputting the scan enable signal input from the outside; Inverting means for inverting and outputting the scan enable signal; And clock generation means for outputting a clock corresponding to the input of the primary clock signal, the primary reset signal, and the scan enable signal received from the outside.

4. Important uses of the devise

This design is used for test ease design.

Description

Scan decoder with one input

The present invention relates to a scan decoder having a work input made at the generation of an internal scan chain in the system facilitation design field.

Design for Testability (DFT) is a design that facilitates the testing of logic circuits, which are becoming difficult due to the increase in the size of the target circuit resulting from the increased integration of ultra-large scale integrated circuits or the increase in the number of internal gates for the number of input / output terminals. Say it's designed for.

In the system facilitating design, the flip method in a circuit is a scan method or an internal scan insertion, which is configured as a series of shift registers for test purposes, and a shift pass (scan pass) during a test. It refers to the method of applying test data to the flip flop or observing the value of the flip flop through).

In other words, the test data generation of the combination circuit is automated, and the circuit system is provided with a mechanism for converting the combination data into a combination circuit during the sequential circuit test.

The purpose of this is to increase the testability of the chip.

By converting a sequential circuit of a chip into a combination circuit, each node can be given a certain value when performing ATPG (Automatic Test Pattern Generation).

That is, the input value that can test a specific part can be given through the primary input pin or the scan input pin, and then the output can be checked.

But you can't do that without flip-flops. Because flip flops change their values with a clock.

Thus, the flip flops or latches in the internal logic are turned into scan flip flops or scan latches and they are chained as one or the designer desires.

At this time, in order to control the scan chain, the clock of the flip-flop connected to the scan chain must be controllable from the outside of the chip. To this end, a mux logic is added to the clock generation block of each chip.

In order to enable the multiplexer in the scan flip-flop, another signal is generated at the scan decoder.

1 is a block diagram showing a conventional scan decoder.

As shown in the figure, a conventional scan decoder receives a first scan enable signal from an external source and passes the first buffer 101 to generate a scan synthesis enable signal, and then passes the inverter buffer 102. A scan synthesis inverse enable signal is generated, and a second scan enable signal is input to pass through the second buffer 103 to generate and output a scan synthesis clock.

In addition, the states of the first scan enable signal and the second scan enable signal when the scan is performed are shown in Table 1 below.

Table 1

condition Second scan enable signal First scan enable signal Steady state 0 0 Scan reset 0 0 Shift stat One One Hold stst One X (don't care) Capture stst One 0

The output is as follows (Table 2).

Table 2

condition Scan Synthesis Clock Scan Synthesis Enable Scan Synthesis Bus Enable Steady state 0 0 One Scan reset 0 0 One Shift state One One 0 Horde state One x (dontcare) X (dontcare) Capture status One 0 One

However, the above device has a problem in that the number of pin counts and the number of pads are increased in view of the trend of high pin count chips becoming more common.

Accordingly, the present invention devised to solve the above-described problem is to receive one scan enable signal provided from the outside using one flip-flop and an OR gate to be connected to the internal scan chain. It is an object of the present invention to provide a scan decoder for determining a clock signal of a flip flop and generating an enable signal for selecting an input of the flip flop.

1 is a block diagram showing a conventional scan decoder.

2 is a block diagram illustrating a chip in which a typical scan decoder and a scan flip flop are inserted.

3 is a configuration diagram of a synchronous loop circuit or a clock generation circuit of FIG.

4 is a configuration diagram of the scan flip flop of FIG. 2;

5 is a configuration diagram of the internal scan chain of FIG. 2.

6 is a block diagram showing a scan decoder having a one input according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

601 buffer 602 inverter

603: OR gate 604: delay flip flop

An apparatus of the present invention for achieving the above object, the buffer means for buffering the scan enable signal input from the outside; Inverting means for inverting and outputting the scan enable signal; And clock generation means for outputting a clock in response to the input of the primary clock signal, the primary reset signal, and the scan enable signal received from the outside.

Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to FIGS. 2 to 6.

2 is a block diagram illustrating a chip in which a typical scan decoder and a scan flip flop are inserted.

As shown in the drawing, a conventional scan decoder and a chip in which a scan flip-flop is inserted, receive two scan enable signals SCAN_EN1 and SCAN_EN2 from the outside and scan synthesized inverse enable signal SCANSYN_ENINV and scan synthesized in. A scan decoder 201 that generates and outputs a signal signal SCANSYN_EN and a scan synthesis clock signal SCANSYN_CLK, and a synchronous phase loop that receives an external clock signal to form an internal clock and outputs the internal clock. Phase Locked Loop or clock generation logic 202, a scan input signal and a primary input signal are received from an external source, an internal clock is received from a synchronous phase loop or clock generation logic circuit 202, The internal scan chain 203 is configured to receive a scan synthesis enable signal from the scan decoder 201 and perform an inspection of internal logic. It is raining.

The flip flop connected to the internal scan chain 203 is configured as a scan flip flop including a multiplexer mux.

In addition, each input stage and output stage include a pad so as to provide a buffering function against a signal input from the outside.

3 is a configuration diagram of a synchronous loop circuit or a clock generation circuit of FIG. 2.

As shown in the figure, the synchronous loop circuit or the clock generation circuit includes a synchronous circuit and a clock circuit generation circuit 301 which receive a primary clock from the outside before the internal scan insertion into the chip and generate and output the internal clock. ) Is provided with a multiplexer 302 which receives the output of the synchronization circuit and the clock generation circuit and the primary output, and selects and outputs according to the scan synthesis clock.

If the external system clock is directly connected to the scan flip flop without going through any logic circuit, then no multiplexer is added.

However, at present, almost all chips use a synchronous circuit loop 301 or some other clock generation logic circuit 301 to make the clock.

In this case, a multiplexer 302 is inserted to directly and externally control the clock entering the internal scan chain.

The select signal of this multiplexer 302 is also made at the scan decoder.

In case of normal, it has a value of '0', 'scan operation' or 'test operation'.

4 is a configuration diagram of the scan flip flop of FIG. 2.

As shown in the figure, the scan flip flop has a structure in which a multiplexer 402 is added to a general flip flop 401.

There are several ways to configure the scan flip flop, but generally the above configuration is used.

The scan flip flop performs a steady state operation and a check operation.

Data input (DI) is the data before performing the scan. When the scan input forms a scan chain, the output of the flip flop connected to the front end of the flip flop is now connected.

Q is outputted to the output signal of the scan decoder so that it can operate in a normal state, and at the same time, it is used as an input of the next scan flip flop in the scan chain during the scan operation.

In addition, the selection signal SE is a signal for selecting a normal operation and a scan operation and has a value of '0' in normal operation and '1' in scan operation.

This selection signal is made at the scan decoder.

Now look at the operation of the scan flip flop:

In normal state, the selection signal is '0' so that the normal output of the system enters through the data input port and goes out to the Q output. When performing the scan operation, it enters the scan input or data input and goes out to the Q output.

The operation of the scan flip flop is as described above, wherein the internal clock of the scan flip flop is made through a phase locked loop or a clock generating circuit.

FIG. 5 is a diagram illustrating an internal scan chain of FIG. 2.

As shown in the figure, each scan flip-flop 501, 502, 503, 504 receives data from the outside and scan inputs from the output of the flip-flop at the front end of the inner scan chain. Generate data output and scan output.

Meanwhile, the scan operation performed by the above apparatus will be described in detail as follows.

First, the scan operation is performed by adjusting the selection signal of the multiplexer of the synchronous loop circuit or the clock generation circuit stage and the selection signal of the scan flip flop.

A system reset is performed first, which is the same as a normal system reset.

At this time, the selection signals of the clock generation circuit and the scan chain block are '0' and '0' in the normal state.

Later, when performing a scan operation in the system reset state, the shift state shifts to supply the primary clock signal to the internal clock while continuing to provide the output signal of the scan chain to the input of the scan flip flop.

At this time, in the shift state, the selection signals of the clock generation circuit and the scan chain block are '1' and '1'.

This cycle of the number of scan flip flops tells us what state all the flip flops are in.

Subsequently, the transition from the shift state to the old state gives one cycle of holding the present value without giving a clock.

Finally, as a capture state, it clocks again for only one cycle, which causes the system's primary input to enter the flip flop.

Then all of the logic circuits on the chip behave like combinatorial circuits, passing in the values they enter.

Table 3 shows each state.

Table 3

condition Selection signal of clock generation circuit Select signal of scan chain block Steady state 0 0 Scan reset 0 0 Shift stat One One Hold stst One X (don't care) Capture stst One 0

6 is a block diagram illustrating a scan decoder having one input according to an embodiment of the present invention.

As shown in the drawing, a scan decoder having one input includes a buffer 601 for passing and outputting a scan enable signal input from the outside, and an inverter 602 for inverting and outputting a scan enable signal input from the outside. An OR gate 603 for adding the scan enable signal input from the outside and the signal input from the flip flop 604 and outputting the OR signal 603 and a primary clock signal from the outside And a delay flip-flop 604 that receives the primary reset signal and outputs the same to the OR gate 603.

The scan decoder having one input according to the present invention receives one scan enable signal when only one pin is used for the scan mode from the outside, thereby making the same operation as the conventional scan decoder.

In the present invention, when one scan enable signal becomes '0' to '1' in the scan mode, the scan synthesized clock signal becomes '0' to '1' by the flip-flop 604 and maintains it.

Therefore, the scan synthesis clock operates at 0, 1, 1 and the scan synthesis enable signal operates at 0, 1, X, 0.

The present invention described above is possible to those skilled in the art to which the present invention belongs, various substitutions, modifications and changes can be made within the scope without departing from the technical spirit of the present invention described above and It is not limited to the drawings.

As described above, the present invention reduces the number of pins and pads in a chip by receiving a single scan enable signal and having the same function as the conventional scan decoder method, which requires two enable signals in the entire chip. There is.

Claims (2)

Buffer means for buffering and outputting the scan enable signal input from the outside; Inverting means for inverting and outputting the scan enable signal; And Clock generation means for outputting a clock in response to an input of a primary clock signal, a primary reset signal, and the scan enable signal received from an external source; Scan decoder having a one input, including a. The method of claim 1, The clock generation means, A logical sum means for receiving the scan enable signal and the clock and performing a logical sum; And Second delay means for delaying the output of the OR in accordance with the primary clock signal and the primary reset signal to output to the OR Scan decoder having a one input, including a.