KR20000000631A - Layout structure of mask patterns - Google Patents

Abstract

PURPOSE: A mask pattern layout structure is provided to improve a margin of design rule by forming a pattern located at side surface more narrow width compared to the width of the desired patterns. CONSTITUTION: The layout structure of mask patterns comprises a first pattern region(310) having a plurality patterns arranged in parallel with each other; and a second pattern region(320) having a single pattern on the mask(300) and separating the first pattern region(310), wherein the outmost pattern in the first pattern regions(310) has narrow width than that of the different patterns and the single pattern of the second pattern regions(320) has same width to the outmost pattern.

Description

MASK PATTERN LAYOUT STRUCTURE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern layout structure, and more particularly, to a layout pattern of a mask pattern for a pattern having a width to be obtained.

As semiconductor integration increases, the process technology for realizing this becomes increasingly difficult. In the case of 64MDRAM or 16MDRAM, the process is performed with a design rule of 0.350 µm to 0.45 µm. At this time, in the case of the linear pattern has a width of about 0.04㎛. This has an error of ± 0.1㎛ when considering the process capability, but does not cause a big problem in the performance of the process according to the pattern. However, in recent years, the design rules of products being produced have become small, such as 0.15 µm to 0.25 µm, resulting in an error of 0.07 µm to 0.08 µm in process capability. Due to the increased density, the process capability cannot be followed, which leads to a lot of difficulties in the technology development of the product.

1 shows patterns with the same widths.

The first pattern region 110 in which the plurality of patterns 111a, 111b, and 112 are formed on the same mask 100, the second pattern region 120 in which one pattern 121 is formed, and two patterns The third pattern region 130 in which the fields 131 and 132 are formed is formed. The patterns 111a, 111b, 121, 131, and 132 have the same wiring width L. FIG.

FIG. 2 shows patterns formed on the photoresist after transferring to the mask of FIG. 1.

After performing the photo and etching process on the mask 100, the photoresist patterns on the silicon substrate are different from the width of the original pattern. Although not shown, patterns of the pattern regions are formed on the photoresist film by exposure of light, and the photoresist patterns are left on the silicon substrate through an etching process.

As a result of performing a photolithography process on the patterns 111a and 111b arranged at the outermost of the patterns 111a, 111b and 112 of the first pattern region 110 of FIG. 1, the first pattern region of FIG. As in 210, photoresist patterns 212a and 212b having L '(L'> L) larger than the original L are formed. The mask patterns 112 arranged between the outermost mask patterns 111a and 111b of the first pattern region 110 have the same size after the photolithography process and have a first pattern region 210 on the photoresist film 200. / 212).

As a result of performing a photolithography process on the mask pattern 121 of the second pattern region 120, photoresist patterns 221 having a wiring width greater than L are formed on the second pattern region 220. .

As a result of performing a photolithography process on the two patterns 131 and 132 of the third pattern region 130, a photoresist having a wiring width larger than L with respect to the third pattern region 230 of the photoresist film 200 is obtained. Patterns 231 and 232 are formed.

As described above, a pattern was formed by depoting a photoresist film to be used as a pattern to be formed on a silicon substrate and performing a photolithography process on a mask on which the pattern to be formed is drawn. However, this results in a difference in the width of the patterns after the photolithography process depending on the size and density of the patterns. That is, an etching loading effect in which patterns 211, 221, 231a, and 231b (photoresist patterns) having a wiring width different from the wiring widths of the mask patterns are formed after the photolithography process is performed. Therefore, a pattern different from the desired pattern is formed.

An object of the present invention is to provide a mask pattern layout structure capable of obtaining a photoresist pattern having a width originally intended to be obtained after a photolithography process of the mask patterns.

1 is a diagram of mask patterns;

2 is a diagram of photoresist patterns after a conventional photo process; And

3 illustrates mask patterns according to the present invention.

* Explanation of symbols on the main parts of the drawings

100, 300: mask 200: photoresist

310: first pattern region 320: second pattern region

330: third pattern region 311a. 311b, 312, 321, 331, 332; Mask patterns

According to one aspect of the present invention for achieving the above object, a mask pattern layout structure for use in the manufacture of a semiconductor device comprises a first pattern region having a plurality of patterns arranged in parallel with each other on a mask; A second pattern region having a single pattern on the mask and separated from the first pattern region, wherein outermost patterns of the patterns of the first pattern region have a narrower wiring width than the remaining patterns, and The single pattern of the two pattern region has the same wiring width as the outermost patterns of the patterns of the first region.

In a preferred embodiment, it further comprises a third pattern region separate from the first and second pattern regions and having two patterns.

In a preferred embodiment, each of the two patterns of the third pattern region has the same wiring width as the outermost patterns of the patterns of the first pattern region.

(Action)

By such a layout, patterns having a desired wiring width can be obtained after the photolithography process of the mask patterns.

(Example)

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, a plurality of patterns are formed on the same mask 300 in the same direction. The outermost patterns of the patterns are formed to be smaller than the width of the original pattern. Then, when the photolithography process is performed, the patterns positioned on the side may have a larger wiring width than the original to obtain desired patterns.

Hereinafter, a mask layout for forming mask patterns having a width of 0.08 μm will be described.

3 shows a mask pattern layout according to the present invention.

The mask 300 may include a first pattern region 310 having a plurality of mask patterns 311a, 311b, and 312, a second pattern region 320 having one mask pattern 321, and the same wiring width L ″. ) And a third pattern region having two mask patterns 331 and 321.

The wiring width of the patterns to be formed on the photoresist film by irradiating light to the mask patterns is 0.08 μm.

When the photolithography process is performed on a plurality of patterns having the same wiring width of 0.08 μm in the first pattern region 310 on the mask 300, the silicon substrate having a width larger than 0.08 μm of the outermost patterns is formed. Is formed on the phase. The present invention therefore allows the patterns formed on both sides to have a wiring width L ″ of less than 0.08 μm of the wiring width L of the pattern to be obtained.

A pattern 321 having a wiring width smaller than 0.08 μm is formed in the second pattern region 320, and a photoresist pattern having a width similar to 0.08 μm is formed as a result of performing a photolithography process.

Two patterns 331 and 332 having a wiring width L ″ of less than 0.08 μm are formed in the third pattern region 330 on the mask 300, and then a photolithography process is performed to produce the original pattern 311. A photoresist pattern having a width close to 0.08 mu m, which is larger than the width of N-T) can be obtained.

Referring back to FIG. 3, a plurality of patterns (at least two) 311a, 311b, and 312 are arranged in the same direction on the same mask 300. The mask patterns 311a and 311b arranged on the outermost side of the plurality of patterns have a wiring width L ″ smaller than 0.08 μm, and the patterns formed therebetween have a wiring width of 0.08 μm. Then, when the photolithography process is performed, the outermost mask patterns 311a and 311b and the patterns 312 arranged therebetween have the same wiring width of about 0.08 μm.

Two mask patterns 331 and 332 are arranged in the same direction in the third pattern region 330 on the mask 300. The patterns 331 and 332 have a wiring width L ″ <L less than 0.08 μm, similarly to the outermost patterns 311a and 311b of the first pattern region. Therefore, after the photolithography process, patterns 201 having a width of 0.08 μm are formed on the photoresist layer due to the etching loading phenomenon.

This is possible by forming a pattern having a wiring width smaller than the wiring width of the original pattern to be obtained on the mask since the pattern does not have the desired wiring width after the photo-etching process by the etching loading phenomenon.

As described above, patterns having the same width may be formed on the silicon substrate by forming the width of the pattern arranged on the side of the pattern arranged on the mask to be smaller than the width of the pattern to be obtained.

Claims (3)

In the mask pattern layout structure for use in the manufacture of a semiconductor device, A first pattern region having a plurality of patterns arranged in parallel with each other on a mask; A second pattern region having a single pattern on the mask and separated from the first pattern region, The outermost patterns of the patterns of the first pattern region have a narrower wiring width than the other patterns, and And the single pattern of the second pattern region has the same wiring width as the outermost patterns of the patterns of the first region. The method of claim 1, And a third pattern region separate from the first and second pattern regions and having two patterns. The method of claim 2, And each of the two patterns of the third pattern region has the same wiring width as the outermost patterns of the patterns of the first pattern region.