KR19990085749A - Bit deinterleaving method - Google Patents

Abstract

The present invention relates to a method of deinterleaving data interleaved and received in a DVB-T system to an original state, and more particularly, to a method of deinterleaving data received in a DVB- When the writing of the data is completed, the process of reading the written data according to the address sequentially shifted by the predetermined interval and writing the data inputted at the immediately address position where the data is read is repeated for each block, When implementing a bit interleaver / deinterleaver of an OFDM system using a carrier or implementing all kinds of interleavers / deinterleavers in which the order of input bits is shifted by a predetermined magnitude and output, the amount of memory corresponding to only one block size Interleaving / di Since emitter Living is possible, it is easily upset IC can reduce the amount of internal memory required when the actual design of these interleaver / deinterleaver to the IC.

Description

Bit deinterleaving method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital TV transmission in Europe and, more particularly, to a bit deinterleaving method for deinterleaving data received in interleaving in a DVB-T (Digital Video Broadcasting-Terrestrial) will be.

The transmission method of the digital TV can be largely classified into a single carrier modulation method using one single carrier and a multi-carrier transmission method using multiple carriers to transmit desired data as in the conventional transmission methods. In other words, it is divided into a VSB scheme using one single carrier and a Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation scheme using multiple carriers.

The DVB-T system is a terrestrial digital TV transmission system in Europe and is currently under trial broadcast in several European countries. The DVB-T system uses a COFDM transmission method. The COFDM scheme is divided into a 2K mode with 1705 carriers and an 8K mode with 6817 carriers according to the number of carriers in a symbol to be transmitted.

Unlike the conventional DVB-C (cable) or DVB-S (Satellite), the COFDM scheme transmits data using an Inverse Fast Fourier Transform (IFFT) at a transmitter and uses an FFT (FEC) part is characterized by sharing with other DVB-C or DVB-S. In addition to the sharing with other standards, a newly added portion is an inner interleaver. That is, when data is transmitted by performing internal interleaving at the transmitting end, a frequency null that occurs in a specific part of the transmission frequency band is divided into a whole frequency band, It is possible to improve the performance degradation due to the above-mentioned problems.

To this end, the inner interleaver is composed of a bit interleaver and a symbol interleaver. The bit interleaver interleaves the digital data to be transmitted in a bit unit of a predetermined size, and the symbol interleaver interleaves the data interleaved on a bit by bit basis. Here, the bit interleaver performs interleaving at the transmitting end and deinterleaving at the receiving end in units of constant COFDM bits. The main operation in such a bit interleaver / deinterleaver is to write data inputted to the memory by an address generated by the bit interleaving / deinterleaving rule and to read the data again.

FIG. 1 illustrates a conventional interleaving / deinterleaving method. In order to shift the order of input data, which is the basis of interleaving / de-interleaving, by a predetermined amount and output, a memory having a size of block size (N) 2 " This is because in order to change the order of data into a desired rule, the input signal must first be stored in a memory of a predetermined size for each symbol, and then the data must be output again in a different order generated by the predetermined rule.

To do so, data is written to one memory by switching among the two memories and data is written again to another memory after one block is written. That is, the memory write of the input data alternately performs the process of alternately writing data to one memory and writing data to another memory after completing writing of one block. The lead process is the same.

For example, if an address generated in accordance with the interleaving or deinterleaving rule is input and the data is written in the memory 1, the data is read from the memory 2. When the data write to the memory 1 and the data reading from the memory 2 are completed, Data is read and data is written to the memory 2 at the same time.

However, since the above-described method can easily control the memory, the memory capacity needs to be twice the block size (N) required for interleaving (or deinterleaving). Therefore, The size of the DVB-T receiving system becomes large, which is a great obstacle to the integration of the DVB-T receiving system into an IC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to reduce the memory size by allowing the symbol deinterleaved data to be written to the memory block unit, And a bit deinterleaving method.

1 is a block diagram showing a memory required for a conventional interleaving / deinterleaving process

2 is an overall block diagram of a DVB-T receiving system according to the present invention

3 is a block diagram showing a memory required for interleaving / deinterleaving processing according to the present invention.

4 is a detailed block diagram of the bit deinterleaver of FIG.

5 (a) to 5 (d) are input / output timing diagrams of respective parts of the bit deinterleaver of FIG. 4

6 (a) to (c) show the address generation timing diagram of the bit deinterleaver of FIG. 4

7 is a flowchart illustrating a bit deinterleaving method according to the present invention.

8A to 8C are timing diagrams showing output states of a bit deinterleaver for connection with a Viterbi decoder.

DESCRIPTION OF THE REFERENCE NUMERALS

21: control unit 22: demapper and symbol deinterleaver

23: bit interleaver 41: counter

42: address generator 43: memory

44: Multiplexer

According to another aspect of the present invention, there is provided a bit de-interleaving method for sequentially writing data received in a memory to a block size corresponding to a block size, And a process of reading data written in an address sequentially shifted by an interval and writing the data input at the immediately address position where data is read is repeated for each block.

With such a bit deinterleaving method, bit deinterleaving can be performed only with a memory capacity corresponding to a block size necessary for bit deinterleaving, and bit interleaving can be performed on the transmitting side as well.

Here, the interleaving is performed by the transmitting side, and the deinterleaving is performed by the receiving side, and only the input / output order of the data is different. Therefore, in the present invention, only deinterleaving is described as an embodiment.

Other objects, features and advantages of the present invention will become apparent from the detailed description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a DVB-T receiving system according to the present invention. The DVB-T receiving system includes a demapper and a symbol deinterleaver 22 for demapping data output from an equalizer and performing symbol deinterleaving on demapped data, A bit deinterleaver 23 for deinterleaving the data deinterleaved on a symbol basis by bit basis, and a TPS controller 21 for controlling de-mapping and deinterleaving using the received TPS information.

In the present invention configured as described above, the demapper 22 demaps the data output from the equalizer. In this case, the demapping method is usually performed using 3-bit or 4-bit soft decision. The COFDM standard is defined to be compatible with various modes. The information of the various modes is sent by TPS (Transmission Parameter Signaling). At the receiving end, the demapper and symbol deinterleaver 22, A deinterleaver 23, a Viterbi decoder, and the like.

That is, the TPS controller 21 inserts various parameter data related to the transmission at the transmitting end and transmits the data. The TPS decoder decodes the data into the TPS enable signal (tps_en) and the TPS data (tps_data) 21, the TPS controller 21 provides the tps_const information about the constellation to the demapper and symbol deinterleaver 22 and the bit deinterleaver 23, And provides information symbol_index for the OFDM symbol to the symbol deinterleaver.

The data output from the equalizer includes eg_flag indicating the turn_on of the equalizer, eq_sync indicating the beginning of the OFDM symbol, carrier_en indicating the active carrier data, not the pilot, and equal_I, equal_Q indicating the respective I and Q data, And CSI (Channel State Information) indicating information are input to the demapper and symbol deinterleaver 22.

The demapper and symbol deinterleaver 22 demaps the output of the equalizer and the original data mapped by the transmitter using CSI (Channel State Information), which is channel state information, and the demapped data is a constant OFDM symbol And outputs the resultant data to a bit deinterleaver 23. The bit deinterleaver 23 performs bit deinterleaving for bit-by-bit interleaving of the symbol-by-symbol data, and finally outputs the data to the FEC stage.

FIG. 3 shows a memory control method for bit deinterleaving according to the present invention, which is implemented with a memory size of block size N (126 bits in COFDM system is one block size). This is achieved by first writing the input data into the memory in a predetermined order and writing the address to the address while reading the size of one block after reading it by a certain address.

4 is a detailed block diagram of a bit deinterleaver, which includes a counter 41 for counting data input by various control signals output from the demapper and symbol deinterleaver 22 and outputting a control signal corresponding thereto, An address generator 42 for generating a read / write address in accordance with a control signal generated by the address generator 41, and a controller 42 for writing and reading the data input in accordance with the address provided by the address generator 43 and performing deinterleaving And a multiplexer 44 for outputting the data output from the memory 43 in a proper data order for a subsequent connection (Viterbi decoder).

In other words, a bit_index signal indicative of an output of the demapper and the symbol deinterleaver 22, that is, a symbol index, a bit_flag signal indicating the turn-on of the front end operation, a bit_sync signal indicating the start of each symbol, A bit_dvald signal indicative of a section of the active carrier is input to the counter 41. 5 (a), after the start signal (bit_sync) of a symbol input after the previous operation turn-on signal (bit_flag) becomes high, the counter 41 outputs a bit_dvald The input data is counted only when the signal is high as shown in FIG. 5 (b). When counting of the counter 41 starts from the beginning of the bit_dvald signal which is a valid data interval after the bit_sync signal, the data input as shown in FIG. 5C is written to the memory 43 at a constant address.

At this time, when the count value reaches a constant block size N, the read_flag signal is made high. That is, when the memory 43 is written by a predetermined block size N and the read_flag signal becomes high, the reading of the data stored in the memory 43 is started as shown in FIG. 5 (d).

By reading the data after the data write of one block size N after the write start time, the memory of one block size can be sufficiently implemented.

The block interval shown in (d) of FIG. 5 represents a period corresponding to the size of the block. In the bit_dvald signal, a low signal in a period after the bit_sync is input as high is a protection interval And represents data corresponding to a pilot signal (non-active carrier). In addition, the interval from the output of one bit_sync to the input of the next bit_sync signal is just one OFDM symbol interval.

Therefore, the data to be inputted after the bit_sync signal becomes high is continuously written in the memory 43.

On the other hand, the address generating unit 42 shown in Fig. 4 generates addresses necessary for writing and reading, respectively. In the case of OFDM, all the addresses required for six types of address generation (I0 to I5) are satisfied. The memory 43 writes the output data (bd0 to bd5) of the input symbol deinterleaver and reads or writes the data according to the address generated by the address generating unit 42, when necessary.

6 is a timing chart of the generation of the address type for writing and reading data in the memory 43. Fig.

That is, the order of input data B (e) is

(E) = (b _{e, 0} , b _{e, 1} , b _{e, 2} , ..., b _{e, N} )

And the output data A (e) is < RTI ID = 0.0 >

(A _{, 0} , a _{e, 1} , a _{e, 2} , ..., a _{e, N} )

As shown in FIG. First, assuming that the block size N = 126, the input / output expression has the following formula (1)

a _{e, H (w)} = b _{e, w}

And H (w) is shifted by the relation of the following equation (2).

H (w) = (w + 105) mod N (w = 0,1, ..., 125)

Here, e varies depending on the QAM scheme, that is, the number of constellations. In the case of 16QAM, it has a value of 0 to 3. In the case of 64QAM, it has a value of 0 to 5. The constant 105 in Equation (2) is one of the specifications, and may vary depending on the specification.

In this case, if the w value is substituted into the equation (2) from 0 to 125,

H (0) = (0 + 105) mod 126 = 105

H (1) = (1 + 105) mod 126 = 106

. .

. .

. .

H (20) = (20 + 105) mod 126 = 125

H (21) = (21 + 105) mod 126 = 0

H (22) = (22 + 105) mod 126 = 1

. .

. .

. .

H (124) = (124 + 105) mod 126 = 103

H (125) = (125 + 105) mod 126 = 104

.

That is, the data input in the order of 0, 1, 2, ..., 125 is output in the order of 21, 22, ..., 0, 1, ..., 20 on the output side.

In this case, as shown in FIG. 6A, the input data is written into the memory 43 during the first block period (write_flag indicates this). At this time, the address type generated by the address generating unit 42 becomes I0 address, and I0 = 0,1,2, ..., 124,125.

After the data of one block is written in the memory, the data written in the memory 43 is read and written at the same time. That is, read_flag is set to high after one block period to read data.

At this time, the order 0, 1, ..., 125 in the input of the bit deinterleaver 23 is in the order of 21, 22, ... on the output side (the order of such output is defined as r) And the address of the memory write or read in the memory 43 is written / read in the memory 43 by the address of I1. At this time, the address of I1 is the address of I0 = 21, 22, ..., 0, 1, ..., 20 plus r (= 21) The third address is also the address of I1 = I2 = 42, 43, ..., 0, 1, ..., 40 which is obtained by adding r (= 21) Likewise, if the address is generated by increasing r (= 21) in the subsequent blocks as well,

I3 = 63,64, ..., 0,1, ..., 61,62

I4 = 84,85, ..., 0,1, ..., 82,83

I5 = 105,106, ..., 0,1, ..., 103,104

I0 = 0,1, ..., 125

.

When the sixth address is added to the address 105 (r = 21), the address of the address I0 to I5 is repeated because the block size is 126. That is, the counter 41 sequentially repeats I0 to I5 every time the count value becomes a constant block size N, and outputs it to the address generator 42. [ When the I1 count signal is input from the counter 41, the address generator 42 generates an address corresponding to I1 and outputs the address to the memory 43. When the I2 count signal is input, the address generator 42 generates an address corresponding to I2 And outputs it to the memory 43.

If the address is not repeated by a certain rule, the next address is repeatedly increased by a constant size.

FIG. 7 is a flow chart of such an address generating method, in which a sequential address is generated during the first block, and the address is incremented by r continuously from the next block.

That is, after the symbol data is input from the symbol deinterleaver 22 (step 701), the variable k is initialized to 0 (step 702) and the input data is written into the memory 43 k = 0). Then, the next address is designated by the following equation (3) (step 704).

k = (k + 1) mod N

In this case, since k is initialized to 0 in step 702, k is 1 when applied to Equation (3). Here, N is the block size, i.e. 126.

If the next address is determined by Equation (3), it is determined whether the determined address k is 126 (Step 705). Here, 126 is a block size, which is different from N in Equation 3 according to the block size.

If it is determined in step 705 that k is smaller than 126, the process returns to step 703 to write the next data to the address k (k = 1) and then applies the equation 3 again to determine the next address. And the like are compared with each other.

In Equation (3), since the previous k value is 1,

When k = (1 + 1) mod 126, k determined as the next address becomes 2.

At this time, since the determined address k is not 126, the process returns to step 703 and the above processes are repeated, k is incremented by 1 sequentially.

Thus, when k is 126, it means that all the data for one block size has been written into the memory 43.

Therefore, if a data write of one block size N is made in the memory 43 after the write start time, the initial address for storing the read data and the data corresponding to the next block size N is expressed by Equation 4 below (Steps 706 and 707).

a = (a + r) mod N

Here, N is the block size, and r is a constant for shifting the address when the address type is changed according to the deinterleaving rule, and is set to 21 in the present invention. Then, a added to r is initialized to 0 in step 702 as a previous a. Therefore, applying these values to Equation 4 results in a = (0 + 21) mod 126, which results in a = 21.

Accordingly, when a obtained in Equation (4) is replaced by k and c is initialized to 0 (k = a, c = 0), the steps 701 to 705 are performed to write data corresponding to the first block size The address of the read data and the data write address of the next block are determined. That is, k increases sequentially from 21.

In other words, the data written to the address k (k = 21) of the memory 43 is read, and when the read is made, the data inputted at the position (k = 21) is written (step 708).

Then, the next address k for the read / write is designated by the following expression (5), and c is incremented by 1 (step 709).

k = (k + 1) mod N

In this case, k is 21 in the step 707, so that k = (21 + 1) mod 126 is applied to the equation (5).

If the next address k is determined by Equation (5), it is determined whether the incremented value c in step 709 is 126 (step 710). At this time, since k does not increase from 0 but increases from 21, it is judged that the read / write completion of data corresponding to one block size is made by using c.

If it is determined in step 710 that c is smaller than 126, the process returns to step 708 to write the next data to the address k (k = 22) and then applies the equation 5 again to determine the next address k and increase c , And whether the incremented c (c = 2) is equal to 126 is performed.

At this time, since k = 22,

k = (22 + 1) mod 126, and k determined by the next address becomes 23.

At this time, since the incremented c is not 126, the process returns to the step 708 and the above processes are repeated, and k and c are incremented by 1 sequentially. When k is 125 in the above process and is substituted into Equation (5), k becomes 0 by k = (125 + 1) mod 126. Then, the data at the address 0 is read and written. In this case, since c is not 126, the increase of k and c continues, and when c is 126, that is, when k is 21, it means that the reading and writing of data for one block size are all completed.

If it is determined in step 710 that c = 126, the process returns to step 706 to determine the initial address for storing the data corresponding to the next block size N and the read data rewritten by applying Equation (4) Step 710 is repeatedly performed to read / write data corresponding to one block size.

That is, when the address k increases from 42 to 125 and then to 0, and again to 43, the reading and writing of data for one block size is completed.

In the next block, the address k sequentially increases from 63 to 125, then becomes 0, and again reaches 62, the reading and writing of data for one block size is completed.

When data is read and written by such a process, bit de-interleaving can be sufficiently performed only by the memory having the size of the block size N. [

That is, in FIG. 7, steps 701 to 705 illustrate a process of writing data to a block size that is initially input, and steps 706 to 710 illustrate data read / write processes for subsequent input data.

Finally, the multiplexer 44 of FIG. 4 outputs the data output from the memory 43 in a proper data order for a subsequent connection (Viterbi decoder).

FIG. 8 shows an output method for connecting the output of the bit deinterleaver to the Viterdecoder in the next stage in the case of 16QAM. That is, in the case of 16-QAM, since 4 bits are composed of one symbol, the first and third are outputted as I and the second and fourth are outputted as Q for Viterbi decoder input, respectively. The dvaldout signal is also used as a signal indicating the effective period of the I or Q signal.

Meanwhile, the present invention can be applied not only to the bit deinterleaver but also to the bit interleaver on the transmission side, thereby reducing the amount of memory when bit interleaving is performed on the transmitting side.

As described above, according to the bit deinterleaving method of the present invention, the bit interleaver / deinterleaver of the OFDM system using a plurality of carriers and the interleaver / When implementing a deinterleaver, it is possible to perform interleaving / deinterleaving without data loss even by the amount of memory corresponding to only one block size. Therefore, it is possible to reduce the amount of internal memory required when designing such an interleaver / deinterleaver as an IC It is easy to IC. In addition, control of the memory for interleaving / deinterleaving is also very easy.

Claims (4)

A deinterleaving method for deinterleaving data deinterleaved on a symbol-by-bit basis by using a memory, A data write step of sequentially writing data received first in the memory as much as a block size; When the writing of data corresponding to one block size is completed in the data write step, the data is shifted by a predetermined interval to read the data written to the sequentially generated address, and the data input at the immediately address position where the data is read is written And a data read / write step of repeating the process for each block. 2. The method of claim 1, wherein the data read / A first step of shifting a start address of a next block by a predetermined distance from a start address of a previous block when writing of data for one block size is completed, A second step of reading the data written to the address position generated in the first step and writing the data to be input at the address position where the data is read, A third step of incrementing the address to designate the next address and then determining whether the data to be stored at the designated address corresponds to the last data of the block when the reading and writing of data at the address specified in the second step is completed; If it is determined that the last data is the last data, the process returns to the first step to perform a start address generation and a data read / write process for the next block. If it is determined that the data is not the last data, And a fourth step of performing a data read / write operation and a next address generating operation of the bit deinterleaving method. 3. The method of claim 2, wherein if the start address generated in the first step is equal to or larger than a block size value required for deinterleaving, the start address is divided into a block size value, Way. 3. The method of claim 2, wherein the address incremented in the third step is And restarts from 0 if equal to a block size value.