KR19990084465A - Memory Cells in Semiconductor Devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell of a semiconductor device. In particular, the structure of a cell consisting of one transistor and one capacitor constitutes a memory cell consisting of a unit cell consisting of a plurality of transistors and a plurality of capacitors, and is suitable for multi-value sensing. The present invention relates to a multi-transistor memory cell structure of a semiconductor device. The present invention provides a semiconductor substrate, a plurality of active regions formed in rows and columns on the semiconductor substrate, a plurality of first to sixth conductive line patterns orthogonal to the active region and formed on the active region and spaced apart from each other; An insulating layer covering the surface of the semiconductor substrate including the region and the first to sixth conductive line patterns, and a plurality of seventh conductive lines formed in alternating rows on the insulating layer in parallel with the active region and over the active region; Between the first conductive line and the second conductive line, the second conductive line and the third conductive line, the fourth conductive line and the fifth conductive line, and the fifth conductive line and the sixth conductive line, respectively. A plurality of storage node contacts formed through the insulating layer and the seventh conductive line and electrically connected to the respective storage node contacts and formed on the seventh conductive line. It comprises a rotor and a third conductive line pattern and the fourth conductive line to bit line contact electrically coupled to the active region and the seventh conductive line between the patterns.

Description

Memory Cells in Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell of a semiconductor device. In particular, the structure of a cell consisting of one transistor and one capacitor constitutes a memory cell consisting of a unit cell consisting of a plurality of transistors and a plurality of capacitors, and is suitable for multi-value sensing. The present invention relates to a multi-transistor memory cell structure of a semiconductor device.

Since a memory is a memory device, it is classified into a device capable of storing data and a device capable of carrying external data there or storing stored data externally. Devices that carry data are called peripheral circuits and storage devices are called cell arrays. A cell array is a collection of unit memory elements arranged in a matrix form. In general, a unit memory device capable of storing data in units of 1 bit includes a signal line (word line) for selecting and activating a memory cell and a line (bit line) for inputting / outputting data of the memory cell. Must be provided. In order to satisfy these components, various methods have been proposed, including two to four transistors, but a unit memory device composed of one MOS transistor and one capacitor, which is superior in terms of the number of devices, the number of wirings, and the required area, is mainly used. do.

Looking at the operation in the DRAM of a typical sense amplifier, a pair of bit lines run parallel to the cell array, and each bit line is connected to a plurality of cells, each cell connected to the same bit line is a different word The line is connected. Voltage lines and control lines for half Vcc precharge of the bit line pair are located opposite the sense amplifiers. This construction method is called a folded bit line method.

1 is a layout illustrating a folded bit line type memory cell of a semiconductor device manufactured according to the prior art.

Referring to FIG. 1, a plurality of bit lines 6, a word line 5, and a storage node formed in a polysilicon 4, an active region 3, and an active region 3 forming a storage node of a capacitor are formed on a semiconductor substrate. The bit line contact 1 of the contact 2 and the active region 3 is formed.

The plurality of bit lines 6 and the bit bar lines 7 are alternately formed in parallel to form a row, and the plurality of word lines 5 form a column to form the bit lines 6 and bits. It is formed perpendicular to the bar 7 and has a matrix structure.

The gates of one transistor are connected to two word lines 5 of the plurality of word lines 5 that meet one bit line 6, and the transistors are not connected to the next two word lines. The word line 5 connected to the transistor has a drain in common and a bit line contact 1 is formed in the active region 3 in which the common drain is formed. In addition, polysilicon 4 for a capacitor storage node is formed in the source region of the transistor through the storage node contact 2.

That is, one storage node contact 2 is formed in each of the bit line 6 and the bit bar line 7 between two adjacent word lines 5.

In such a memory cell structure, one word line is turned on and a pair of bit lines and a bit bar line are turned on so that data stored in the capacitor comes out along the bit line. This data is differentially amplified by the difference from the precharged value in the sense amplifier circuit, which is subsequently recognized as 0 or 1.

The above-described prior art uses a binary system, which is not suitable for sensing various values of data.

Accordingly, an object of the present invention is to provide a multi-value sensing device in which the structure of a cell consisting of one transistor and one capacitor constitutes a memory cell consisting of a unit cell consisting of a plurality of transistors and a plurality of capacitors, thereby making it suitable for multi-value sensing. To provide a transistor memory cell.

The memory cell of the semiconductor device according to the present invention for achieving the above object is a semiconductor substrate, a plurality of active regions formed in a row and a column on the semiconductor substrate, and orthogonal to the active region formed on the active region and spaced apart from each other A plurality of first to sixth conductive line patterns, an insulating layer covering the surface of the semiconductor substrate including the active region and the first to sixth conductive line patterns, and an alternating layer on the insulating layer parallel to the active region and over the active region A plurality of seventh conductive lines formed in a row, (first conductive line and second conductive line), (second conductive line and third conductive line), (fourth conductive line and fifth conductive line), ( A plurality of storage node contacts respectively formed between the fifth conductive line and the sixth conductive line) and penetrating through the insulating layer and the seventh conductive line, and each storage node contact. And a bit line contact electrically connected to the capacitor, the capacitor formed on the seventh conductive line, and an active region between the third conductive line pattern and the fourth conductive line pattern and the seventh conductive line.

1 is a memory cell layout of a semiconductor device manufactured according to the prior art.

2 is a memory cell circuit diagram of a semiconductor device according to the present invention.

3 is a memory cell layout consisting of two transistors and two capacitors of a semiconductor device manufactured according to the present invention.

4 is a memory cell layout consisting of three transistors and three capacitors of a semiconductor device manufactured according to the present invention.

According to the present invention, in a memory cell of a semiconductor device, one cell is composed of a plurality of transistors and capacitors, and data is stored in the plurality of capacitors under predetermined operating conditions. The embodiment of the present invention describes an example in which two transistors and the same number of capacitors are provided in one cell, and a case in which three transistors and capacitors are provided, respectively.

First, a description will be given with a layout in the case where two transistors and capacitors are provided in one cell.

When the word bar line is turned on, it is the same as the operation mechanism of the prior art. When the word bar line is turned on, data is stored in two capacitors in one cell. After the data is stored in each capacitor, if only the word bar line is turned on, three values of 0, 1, and 2 are generated by charge sharing of the data stored in the two capacitors. Therefore, in the data reading operation, each data is distinguished by a sense amplifier circuit which senses and amplifies each value of 0, 1, and 2, and these values are transmitted to a later stage through the data bus.

2 is a memory cell circuit diagram of a semiconductor device including two transistors and two capacitors according to the present invention.

Referring to FIG. 2, bit lines BL and bit bar lines / BL are alternately formed in parallel in a horizontal direction, and word lines WL and word bar lines / WL are vertical in a vertical direction. They form a column and are formed in parallel. In other words, the parallel parallel bit lines, bit bar lines, word lines, and word bar lines form a matrix structure.

The first cell located between the bit line BL and the bit bar line / BL has one word line WL and a word bar line / WL, and one bit line BL and a bit bar line (/). BL), a first NMOS transistor and a second NMOS transistor connected in series, and a first capacitor connected to a source of the first transistor and a second capacitor connected to a source of the second transistor. In this case, the gate of the first transistor is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the drain of the second transistor. The gate of the second transistor is connected to the word bar line / WL, and the source is connected to the second capacitor. In the first cell, one cell of the same type is adjacent to the bit line in the horizontal direction, and is repeatedly formed after crossing two pairs of word lines and word bar lines.

The second cell is located in a diagonal direction adjacent to the first cell, and is also the third in the matrix forming the bit bar line (/ BL) and the bit line BL, the word bar line (/ WL), and the word line WL. And a neighboring cell composed of a fourth transistor and third and fourth capacitors and having the same structure as that of the second cell in the horizontal direction with the bitbar line as in the first cell, and also having two word lines / word bars. It is repeatedly formed in the form of skipping phosphorus pair.

The drain of the third transistor is connected to the bit bar line / BL, the source is connected to the third capacitor, and the gate is connected to the word line WL. The drain of the fourth transistor is connected with the source of the third transistor, the source is connected with the fourth capacitor, and the gate is connected with the word bar line / WL.

3 is a folded bit line memory cell layout including two transistors and two capacitors of a semiconductor device manufactured according to the present invention.

Referring to FIG. 3, a storage node of a plurality of bit lines BL, a bit bar line / BL, a plurality of word lines WL, a plurality of word bar lines / WL, and a capacitor is disposed on a semiconductor substrate. (37, 38, 39, 40, 45, 46, 47, 48) polysilicon, active regions 31, 40, storage node contacts 33, 34, 35, 36, 41, 42, 43 and 44 and bit line contacts 32 and 49 of the active region are formed. At this time, the source / drain of the transistor is formed in the active regions 31 and 40.

A plurality of bit lines BL and bit bar lines / BL are alternately formed in parallel to form a row, and word lines WL / word bar lines / WL / word lines WL are formed in parallel. It forms a column and is formed perpendicular to the bit line BL and the bit bar line / BL to have a matrix structure.

At this time, two transistors are connected in series to one cell, and each transistor has one capacitor.

The space between the first line pattern composed of the bit bar line / BL and the word line WL / word bar line / WL / word line WL, that is, the word line WL and the word bar line ( / WL) and the active regions 31 and 40 between adjacent word bar lines / WL and wordlines WL and capacitors located thereon. Storage node contacts 33, 34, 35, 36, 41, 42, 43, 44 are formed through the bit bar line / BL. A bit line contact 32 is formed to connect the bit line with the right active region of the word line WL located on the rightmost side of the first line pattern. At this time, the bit line contact 32 is shared with another same cell formed in the same bit bar line part, and this pattern is repeated in the horizontal direction. However, only an insulating layer is located in the active region 31 or above the space between the word line WL and the word line WL which meets the bit bar line / BL.

The memory cells of the above-described type are also located in the bit line located directly below the bit bar line. However, the first line pattern is formed to have a structure in which the first line pattern is moved in parallel to the left side.

FIG. 4 is an open bit line memory cell layout including three transistors and three capacitors of a semiconductor device manufactured according to the present invention.

Referring to FIG. 4, an active region 60 having a rectangular shape on a semiconductor substrate is formed in a long horizontal pattern in rows and columns, and word lines 61 and WL are formed thereon. A plurality of line patterns and a plurality of bit lines formed of phosphorus 62 (/ WL) / second word bar line 63 (/ WL) / ground lines 64 (Vss) are formed in a matrix structure.

In each active region, two line patterns symmetrical to each other and one bit line BL cross each other. At this time, between the word line 61 and the first word bar line 62, the first word bar line 62 and the second word bar line 63, the second word bar line 63 and the ground line 64 Capacitors 65 are formed on the active region 60, and they are electrically connected to each other by the storage node contacts 66 that pass through the bit lines BL. The left active region 60 of the word line 61 is electrically connected to the bit line BL by the bit line contact 67.

Therefore, in the present invention, since the values 0 and 1 are used in the writing of data to a memory cell, they are used as they are without using a high voltage on the bit line side. However, in the reading operation, these values are classified into various values, thereby making multi-data, and amplifying them in a sense amplifier.

Claims (5)

Semiconductor substrate, A plurality of active regions formed in rows and columns on the semiconductor substrate; A plurality of first to sixth conductive line patterns orthogonal to the active region and spaced apart from each other; An insulating layer covering the surface of the semiconductor substrate including the active region and the first to sixth conductive line patterns; A plurality of seventh conductive lines parallel to the active region and formed in alternating rows on the insulating layer above the active region; And are formed between the first conductive line and the second conductive line, the second conductive line and the third conductive line, the fourth conductive line and the fifth conductive line, the fifth conductive line and the sixth conductive line, respectively, A plurality of storage node contacts formed through the insulating layer and the seventh conductive line; A capacitor electrically connected to each of the storage node contacts and formed on the seventh conductive line; And a bit line contact electrically connecting the active region between the third conductive line pattern and the fourth conductive line pattern and the seventh conductive line. The method of claim 1, wherein the first to sixth conductive line patterns are word lines / word bar lines / word lines / word lines / word bar lines / word lines, respectively, and the seventh conductive lines alternate bit lines / bit bar lines. A memory cell of a semiconductor device, characterized in that formed. The memory cell of claim 1, wherein the memory cell comprises two transistors and two capacitors. The memory cell of claim 1, wherein the memory cell comprises three transistors and three capacitors by adding one transistor and one capacitor. The memory cell of claim 1, wherein the memory cell is formed by adding conductive lines orthogonal to the active region and adding as many transistors and capacitors as the added number.