KR19990082845A - Single poly-eeprom cell that is programmable and erasable in a low-voltage environment and methods of programming, erasing and reading the same - Google Patents

Abstract

A single poly EPROM cell with spaced opposite conductive regions formed in the base region and thin film layer of tunnel oxide is formed in a triple well CMOS compatible process. Using a triple well structure and a thin layer of tunnel oxide, the cell of the present invention is electrically programmable and erasable in a low voltage environment of + 3.3V.

Description

SINGLE POLY-EEPROM CELL THAT IS PROGRAMMABLE AND ERASABLE IN A LOW-VOLTAGE ENVIRONMENT AND METHODS OF PROGRAMMING, ERASING AND READING THE SAME}

The present invention relates to a single poly electrically-erasable programmable read-only-memory cell, and more particularly to a single poly EEPROM cell programmable and erasable in a low voltage environment.

A single poly electrically-programmable read-only-memory (EPROM) cell is a nonvolatile memory device fabricated using a process step that is fully compatible with conventional single poly CMOS fabrication process steps. As a result, single poly EPROM cells are often embedded in CMOS logic and mixed signal circuits.

1A-1C are a series of diagrams illustrating a conventional single poly EPROM cell 100. FIG. 1A is a top view of the cell 100, FIG. 1B is a longitudinal cross-sectional view taken along line 1B-1B in FIG. 1A, and FIG. 1C is a longitudinal cross-sectional view taken along line 1C-1C in FIG. 1A.

As shown in FIGS. 1A-1C, the EPROM cell 100 includes a source and drain region 114 and 116 and a spaced apart source, each of which is formed in a p-type semiconductor material 112 such as a well or a substrate. And a channel region defined between the drain regions 114 and 116.

As further shown in FIGS. 1A-1C, cell 100 is formed in n well 120 and p-type material 112 formed in p-type material 112 to form source region 114 from n well 120. And a field oxide region (FOX) separating the drain region 116 and the channel region 118.

In addition, cell 100 further includes adjacent p + and n + contact regions 122 and 124, each of which is formed in n well region 120. The current generation cell also includes a p-type lightly doped drain (PLDD) region 126 adjacent to the p + contact region 122.

Further, control gate region 128 is defined between field oxide region (FOX) and PLDD region 126 that separate n well 120 from source region 114, drain region 116, and channel region 118. do. In addition, the gate oxide layer 130 is formed on the channel region 118, the control gate oxide layer 132 is formed on the gate region 128, and the floating gate 134 is formed on the gate oxide layer 130, Control gate oxide layer 132 and a portion of field oxide region FOX.

During fabrication of cell 100, gate oxide layer 130 and control gate oxide layer 132 typically grow simultaneously, resulting in, for example, about 120 microseconds in a 0.5 micron process and about 70 in a 0.35 micron process. Have substantially the same thickness of.

In operation, cell 100 is programmed by applying about 12 volts to contact regions 122 and 124 to short together and about 6 to 7 volts to drain region 116. In addition, the p-type material 112 and the source region 114 are grounded.

When a positive voltage is applied to contacts 122 and 124, a positive potential is induced on floating gate 134. Specifically, the positive voltage applied to the n + contact region 124 jointly with the potential of the floating gate 134 forms a deep depletion region on the surface of the control gate region 128, such that the control gate region Reduce the potential at the surface of 128.

The positive voltage applied to the p + contact region slightly forward-biass the p + contact region to the n well junction in the control gate region 128. As a result, holes are injected into the surface region of the control gate region 128, inverting the surface of the control gate region 128.

The injected holes quickly reduce the depth of the depletion region at the surface of the control gate region 128 (by picoseconds), and contact substantially all of the voltage applied to the contact region 124 across the control gate oxide layer 132. To area 124. As a result, the initial potential induced in the floating gate 134 is the control gate (which defines the coupling ratio between the n well 120 and the floating gate 134) and the voltage applied to the contact regions 122 and 124. It is defined by the thickness of the oxide layer 132.

If the p + contact region 122 is not present, holes will hardly accumulate on the surface of the control gate region 128 if the surface is initially depleted because the n well 120 contains relatively few holes. Thus, as the heat generating holes drift to the surface of the control gate region 128, the depth of the depletion region can be slowly reduced in size.

Since the depth of the depletion region is initially deep and the voltage applied to the contact 124 is disposed over the control gate oxide layer 132 and the relatively large depletion region, the initial potential induced in the floating gate 134 is substantially small. . Thus, the p + region 122 provides a method for rapidly decreasing the depth of the depletion region after the surface of the control gate region 128 is depleted to increase the potential initially induced in the floating gate 134.

As mentioned above, the current generating cell also requires the use of the PLDD region 126. As is known, the thickness of the control gate oxide layer 132 at the edge of the layer adjacent to the region of p + contact region 122 is due to a known process step of re-oxidation after the poly gate is etched. Slightly thicker than the middle of the layer. As a result, the depletion regions formed at the edges are too small to sufficiently invert the surface, limiting the function of the p + contact region 122 to inject holes into the surface of the control gate region 128.

Thus, the current generation cell uses the PLDD region 126 to form a hole injection region adjacent to the surface region of the control gate region 128 at a distance from the edge. Since the heat treatment step used during the fabrication of such cells allowed sufficient lateral diffusion of the p + contact region 122, conventional current generating cells do not require a PLDD region.

Referring back to the operation of the cell 100, the positive potential induced in the floating gate 134 by applying a positive voltage to the contact regions 122 and 124 forms a depletion region in the channel region 118 to form a channel region. Increase the potential at the surface of 118. Source region 114 injects electrons into the surface of channel region 118 to form a channel of mobile electrons.

The positive voltage applied to drain region 116 forms an electric field between source and drain regions 114 and 116 to accelerate electrons in the channel. Accelerated electrons have ionization collisions to form "channel hot electrons". The positive potential of the floating gate 134 penetrates the gate oxide layer 130 and attracts channel hot electrons that begin to accumulate on the floating gate 134 and raise the threshold voltage of the cell 100.

Cell 100 is read by applying about 5 volts to contact regions 122 and 124 and about 1 to 2 volts to drain region 116. In addition, both the p-type material 112 and the source region 114 are grounded.

Under these bias conditions, if the cell 100 is not programmed, it is sufficient to generate a channel current flowing from the drain region 116 to the source region 114, i.e., greater than the threshold voltage of the cell, and the cell 100 is programmed. In this case, a positive potential is induced on the floating gate 134 by the aforementioned mechanism which is insufficient to generate a channel current, i.e., smaller than the cell's threshold voltage. The logic state of the cell 100 is determined by comparing the magnitude of the channel current flowing into the drain region 116 with the reference current.

The EPROM cell 100 is erased by irradiating the cell 100 with ultraviolet (UV) light to remove electrons. UV light increases the energy of the electrons, allowing them to penetrate the surrounding layer of oxide.

The problem with a single poly EPROM cell mixed in CMOS logic and mixed signal circuits is that the cell is not suitable for low voltage and low power applications. Thus, even if the basic circuit is scaled down for low power applications, a single poly EPROM cell also needs a high voltage circuit to supply the necessary programming voltage.

In addition, the formation of channel high temperature electrons during the programming of a conventional single poly EPROM cell leads to a relatively large current for low power applications. Thus, there is a need for a single poly EPROM operating in a low voltage environment.

The present invention provides a single poly EPROM cell programmable in a low voltage environment. However, there remains a need for a single poly EEPROM capable of both program and erase in low voltage environments.

Conventional single poly EPROM cells program the cells using a relatively high voltage, for example + 12V. The present invention provides a single poly EEPROM that is programmable and erasable at low voltage, for example + 3.3V.

A single poly EEPROM cell of the present invention formed in a semiconductor material of a first conductivity type comprises a first well of a second conductivity type formed in the semiconductor material and a second well of a first conductivity type formed in the first well.

In addition, the single poly EEPROM cell of the present invention includes a source and drain region of a second conductivity type and a channel region defined between the source and drain regions spaced in the second well.

In addition, the cell of the present invention includes a base region of a second conductivity type formed in the second well and a separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region. Include.

The first and second contact regions spaced apart from each other are formed in the base region so that the first contact region has a first conductivity type and the second contact region has a second conductivity type.

In addition, a lightly doped region of the second conductivity type is formed in the semiconductor material adjacent to the first contact region, while a control gate region is defined between the lightly doped region and the isolation region. The cell of the present invention further includes a gate oxide layer formed on the channel region, a tunnel oxide layer formed on the control gate region, and a floating gate formed on part of the gate oxide layer, the tunnel oxide layer, and the isolation region. .

The cell of the present invention is programmed by applying a negative voltage of -3.3V to the first contact region, a positive voltage of + 3.3V to the second contact region, and grounding the second well.

In operation, in the first contact region accelerated to have an ionization collision that forms a high temperature charge carrier with a heat generated carrier, a programming bias voltage is band-to-band tunneling of the charge carrier of the second conductivity type. triggers to-band tunneling Hot charge carriers, defined as majority carriers in the base region, pass through the tunnel oxide layer and accumulate on the floating gate.

The cell of the present invention is erased by applying a negative voltage of -3.3V to the first contact region, the second contact region, and the second well. Also, while the drain is floating or grounded, a second voltage of + Vcc or higher is applied to the source region.

In operation, an erase bias voltage causes charge carriers, which are defined as majority carriers in the base region, to flow from the floating gate to the source region through Fowler-Nordheim tunneling.

The features and advantages of the present invention will be described in more detail with reference to the following detailed description and accompanying drawings, which illustrate exemplary embodiments in which the principles of the invention are used.

1A-1C are a series of diagrams illustrating a conventional single poly EPROM cell 100, FIG. 1A is a plan view of the cell 100, and FIG. 1B is a longitudinal cross-sectional view taken along line 1B-1B of FIG. 1A. 1C is a longitudinal cross-sectional view taken along line 1C-1C in FIG. 1A.

2A-2C are a series of diagrams illustrating a single poly EPROM cell 200 according to a parent invention, FIG. 2A is a top view of the cell 200, and FIG. 2B is a line 2B-2B of FIG. 2A. Is a longitudinal cross-sectional view taken along line), and FIG. 2C is a longitudinal cross-sectional view taken along line 2C-2C of FIG. 2A.

3A-3D are a series of diagrams illustrating a single poly EPROM cell 300 according to a first alternative of hair name, FIG. 3A is a top view of the cell 300, and FIG. 3B is a line 3B-3B of FIG. 3A. 3C is a longitudinal cross-sectional view taken along line 3C-3C of FIG. 3A, and FIG. 3D is a longitudinal cross-sectional view taken along line 3D-3D of FIG. 3A.

4A-4C are a series of diagrams illustrating a single poly EPROM cell 400 according to a second alternative of hair name, FIG. 4A is a top view of the cell 400, and FIG. 4B is a line 4B-4B of FIG. 4A. Is a longitudinal cross-sectional view taken along line), and FIG. 4C is a longitudinal cross-sectional view taken along line 4C-4C in FIG. 4A.

5A-5D are a series of diagrams illustrating a single poly EPROM cell 500 according to a third alternative of hair name, FIG. 5A is a top view of the cell 500, and FIG. 5B is a line 5B-5B of FIG. 5A. 5C is a longitudinal cross-sectional view taken along line 5C-5C of FIG. 5A, and FIG. 5D is a longitudinal cross-sectional view taken along line 5D-5D of FIG. 5A.

6A-6D are a series of diagrams illustrating a single poly electrically-erasable programmable read-only-memory cell 600 in accordance with the present invention, FIG. 6A is a plan view of the cell 600, and FIG. 6A is a longitudinal cross-sectional view taken along line 6B-6B in FIG. 6A, FIG. 6C is a longitudinal cross-sectional view taken along line 6C-6C in FIG. 6A, and FIG. 6D is taken along line 6D-6D in FIG. 6A. Longitudinal section view.

7 is a plan view of a cell 600 according to the present invention.

Explanation of symbols on the main parts of the drawings

Single Poly EPROM Cells: 100, 200, 300, 400, and 500

112: P-type semiconductor material 114: source region

116: drain region 118: channel region

120, 614: n well 122: p + contact region

124,, 410: n + contact area

126 p-type lightly doped drain (PLDD)

128: control gate region 130: gate oxide layer

132: control gate oxide layer

134: floating gate 212: PLDD region

310: NLDD region 600: single poly EEPROM cell

610: n base 612: p well

2A-2C are a series of diagrams illustrating a single poly EPROM cell 200 according to hair name. FIG. 2A is a top view of the cell 200, FIG. 2B is a longitudinal cross-sectional view taken along line 2B-2B in FIG. 2A, and FIG. 2C is a longitudinal cross-sectional view taken along line 2C-2C in FIG. 2A.

As shown in FIGS. 2A-C, the EPROM cell 200 is structurally similar to the EPROM cell 100 of FIG. 1, and as a result, designates a structure common to both cells using the same reference numerals.

EPROM cell 200 differs significantly from EPROM cell 100 in that EPROM cell 200 eliminates the need for n + contact region 124. In addition, cell 200 is also different from cell 100 in that cell 200 uses a smaller PLDD region 212. As shown in FIG. 2A, the surface of p + contact region 122 abuts both the PLDD region 212 and the surface of n well 120.

In addition, the cell 200 may be, for example, about 70 GPa in a 0.5 micron process and about 55 GPa in a 0.35 micron process, instead of a thicker layer of control gate oxide 132, for example, 120 GPa and 70 GPa thick, respectively. An additional substantially thinner layer of tunnel oxide 210 is used. Alternatively, oxide layers 132 and 210 may be formed to have substantially the same thickness.

As a result of using a relatively thin tunnel oxide layer, cell 200 provides a coupling ratio of n wells to a floating gate of about 0.8 or greater. In addition, due to the position of the p + contact region 122 relative to the floating gate 134, the cell 200 also provides a p + junction edge of the coupling ratio for very low floating gates of about 0.05 or less.

In operation, cell 200 is programmed by applying about −6 to −7 volts to the p + contact region and grounding p-type material 112. Also, both the source and drain regions 114 and 116 are grounded or floated.

As a result, the potential of n well 120 is fixed at about −0.5 volts which slightly biases p-type material 112 to n well 120 and reverse biases n well to the p + contact junction (p + contact Even if region 122, n well 120, and p-type material 112 form parasitic bipolar transistors, the anodic action is weak due to low concentration doping of p-type material 112). In addition, since n well 120 is close to ground and the coupling ratio of n well to floating gate is about 0.8, the voltage on floating gate 134 is also close to ground.

Under these bias conditions, the vertical electric field across the tunnel oxide layer 210 results in p + contact regions 122 and PLDD regions 212 where depletion regions increase the potential on the surfaces of p + contact regions 122 and PLDD regions 212. To form.

In addition, the vertical electric field is also large enough to adjust the band-to-band tunneling of the electrons to allow tunneling from the balance band to the conduction band in the p + contact region 122 that accumulates on the surface of the p + region 122. Although significant band-to-band tunneling does not occur in the PLDD region 212, heat-generating electrons accumulate on the surface of the PLDD region 212.

The band-to-band electrons drift into the depletion region of the n well reversed to the p + contact junction, which accelerates the electrons such that the lateral electric field across the depletion region forms ionization collisions forming band-to-band hot electrons.

In addition, electrons generated in the depletion region are accelerated by the lateral electric field to have ionization collisions that form thermal high temperature electrons. Band-to-band and thermal high temperature electrons disclose an avalanche process that generates a number of high temperature electrons. For the p + contact region 122 and the PLDD region 212, the larger positive potential of the floating gate 134 penetrates the tunnel oxide layer 210 and begins to accumulate hot electrons that begin to accumulate on the floating gate 134. Pulls.

Thus, by forming the PLDD region 212 so that the surface of the p + contact region 122 is in contact with both the surface of the PLDD region 212 and the n well 120, band-to-band and thermal high temperature electrons will most likely cause tunneling. The same is formed on the surface of the control gate region 128.

In general, the PLDD region 212 is formed such that the surface of the p + contact region 122 proximate the control gate region 128 does not contact the surface of the n well 120. However, in this case, because of the low lateral electric field for the n well associated with PLDD, low implantation efficiency is obtained. In addition, hot electrons from the p + contacts to the n well junction formed under the PLDD region must pass through the PLDD region and penetrate the tunnel oxide layer 210.

In addition to the formation of high temperature electrons, band-to-band electrons at the surface of the p + contact region 122 and heat generated electrons at the surface of the PLDD region 212 are also formed by the floating gate 134 by Fowler-Nordheim tunneling. Is injected into the phase.

For example, when -7 volts is applied to the p + contact region 122, if the tunnel oxide 210 is 70 kW thick, the electric field across the oxide layer 210 on the PLDD region 212 is about 10.0 MV / cm. to be. A slightly smaller electric field is formed on the p + contact region 122. A high oxide field can be obtained by increasing the voltage applied to the p + contact region 122, or by reducing the thickness of the tunnel oxide layer 210.

The cell 200 is read by applying about 5 volts to the p + contact region 122 and about 1 to 2 volts to the drain region 116. In addition, both the p-type material 122 and the source region 114 are grounded.

When a positive voltage is applied to the p + contact region 122, a positive potential is induced on the floating gate 134. Specifically, the positive voltage applied to the p + contact region 122 is depleted to the surface of the control gate region 128, which decreases the potential at the surface of the control gate region 128, in conjunction with the potential of the floating gate 134. The potential of the n well 120 is fixed to the voltage applied to the p + contact region 122 forming the region.

The positive voltage applied to the p + contact region 122 slightly finely biases the PLDD region with an n well junction at the surface that causes holes to be injected into the surface region of the control gate region 128.

With the cell 100, the injected holes deplete at the surface of the control gate region 128 which rapidly applies (approximately picoseconds) substantially all the voltage applied to the contact region 122 across the tunnel oxide layer 210. Reduces the depth of the. Thus, when cell 200 is read, the main function of PLDD region 212 is the source of holes.

Thus, when a read voltage is applied to the p + contact region 122, when the cell 200 is not programmed, it is sufficient to generate a channel current flowing from the drain region 116 to the source region 114, or When 200 is programmed, a positive potential is induced on floating gate 134 by the aforementioned action, which is insufficient to generate channel current.

The logic state of the cell 200 is determined by comparing the magnitude of the current flowing into the drain region 116 with a reference current. However, p from p + contact regions 122 due to the anodic action of parasitic bipolar transistors, i.e., p + contact regions 122, n well 120, and p-type material 112, which are emitters, bases, and collectors, respectively, There will be a greater leakage current in the cell 200 in the p + contact region for the n well region flowing into the mold material 112.

Thus, a single poly EPROM cell has been published that can be programmed, for example, between -6 and -7 volts to +12 volts, of about half the voltage (in terms of size) required in conventional single poly EPROM cells.

One of the main advantages of hair invention is that band-to-band tunneling leading to high temperature electron injection is at least 100 times more efficient than channel high temperature electronic programming previously used to program a single poly EPROM cell.

Thus, low power consumption is achieved during the program of the invention by the combination of low amplitude bias voltage and more efficient high temperature electron injection action. In addition, by removing the n + contacts used in conventional single poly EPROM cells, a substantially small cell layout is obtained.

3A-3D are a series of diagrams illustrating a single poly EPROM cell 300 according to the first alternative of hair name. FIG. 3A is a top view of the cell 300, FIG. 3B is a longitudinal sectional view taken along line 3B-3B of FIG. 3A, FIG. 3C is a longitudinal sectional view taken along line 3C-3C of FIG. 3A, and 3D is a longitudinal cross-sectional view taken along the line 3D-3D in FIG. 3A.

As shown in FIGS. 3A-3D, the EPROM cell 300 is structurally similar to the EPROM cell 200 of FIGS. 2A-C, with the same reference numbers designating a structure common to both cells as a result. . EPROM cell 300 differs principally from EPROM cell 200 in that EPROM cell 300 uses NLDD region 310.

The operation of cell 300 is the same as that of cell 200 except that NLDD region 310 enhances the formation of high temperature electrons due to the larger lateral electric field present across the depletion region of the p + contact for the NLDD junction. Do. As a result of the larger lateral electric field, cell 300 generates substantially more induced band-to-band tunneling and thermal hot electrons than cell 200.

4A-4C are a series of diagrams illustrating a single poly EPROM cell 400 according to a second alternative of hair name. 4A is a top view of the cell 400, FIG. 4B is a longitudinal cross-sectional view taken along line 4B-4B in FIG. 4A, and FIG. 4C is a longitudinal cross-sectional view taken along line 4C-4C in FIG. 4A.

As shown in FIGS. 4A-4C, the EPROM cell 400 is structurally similar to the EPROM cell 200 of FIGS. 2A-C, as a result of which the same reference numerals are used to specify structures common to both cells. do. EPROM cell 400 differs from EPROM cell 200 primarily in that EPROM cell 400 uses n + contact regions 410 spaced from p + contact regions 122, unlike conventional cells. Thus, other biasing voltages may be applied separately to the p + contact region 122 and the n + contact region 410.

In operation, cell 400 is programmed by applying about −4 volts to p + contact region 122, grounding p-type material 112, and applying about +4 volts to n + contact region 410. In addition, both source and drain regions 114 and 116 are grounded or floated.

As a result, the voltage applied to the n + contact region is applied to n well 120, which biases both p-type material 112 to n well 120 junction and n well 120 to p + contact junction.

In addition, since the potential on the n well 120 is about +4 volts, and the coupling ratio of the n well to the floating gate is about 0.8 or more, the potential on the floating gate 134 is also close to +4 volts. Thus, +4 volts are applied to the n + contact region 410 and -4 to the p + contact region 122 as formed in the cell 200 by applying -6 to -7 volts only on the p + contact region 122. By applying a bolt, substantially the same vertical electric field is formed in the cell 400.

Thus, the vertical electric field across the tunnel oxide layer 210 of the cell 400 is depleted in the p + contact region and the PLDD region 212, which increases the potential on the surfaces of the p + contact region 122 and the PLDD region 212. To form.

In addition, the vertical electric field is sufficiently large to adjust the band-to-band tunneling of electrons in the p + contact region 122 of the cell 400 and accumulate on the surface of the p + region 122. Although band-generated electrons are accumulated on the surface of the PLDD region 212, the major band-to-band tunneling does not occur in the PLDD region 212.

One major difference between cell 400 and cell 200, however, is that by using a small bias voltage with both positive and negative electrodes, cell 400 has a substantially large reverse bias in the n well junction across the p + contact region. Is to provide.

Thus, when band-to-band electrons drift into depletion regions of n wells reversely biased with p + contact junctions, the more powerful lateral electric field of cell 400 has more ionization collisions to form more band-to-band hot electrons. To accelerate the electrons.

In addition, electrons generated in the depletion region of the n well reversely biased to the p + contact junction are accelerated by a more powerful lateral electric field to have more ionization collisions to form more thermal hot electrons. Band-to-band tunneling and thermal hot electrons initiate the avalanche process to generate more hot electrons. With cell 200, the positive potential of floating gate 134 attracts band-to-band and thermal hot electrons to penetrate tunnel oxide layer 210 and begin to accumulate on floating gate 134.

In addition, band-to-band electrons at the surface of the p + contact region 122 and heat generated electrons at the surface of the PLDD region 212 with the cell 200 are formed on the floating gate 134 by Fowler-Nordheim tunneling. Is injected into.

Cell 400 may be read by the same method as cell 100 of FIGS. 1A-1C, or alternatively in the same way that cell 200 of FIGS. 2A-C is read. Thus, cell 400 applies the same voltage, for example 5 volts, to p + contact region 122 and n + contact region 410, or positively, for example, 5 volts to p + contact region 1222. It can be read by applying a voltage (eg, while applying a positive voltage of 1 volt to drain region 116 and grounding source region 114) and plotting n + contact region 122.

5A-5D are a series of diagrams illustrating a single poly EPROM cell 500 in accordance with a third alternative of hair name. FIG. 5A is a top view of cell 500, FIG. 5B is a longitudinal sectional view taken along line 5B-5B in FIG. 5A, FIG. 5C is a longitudinal sectional view taken along line 5C-5C in FIG. 5A, and FIG. 5D is a longitudinal cross-sectional view taken along the line 5D-5D in FIG. 5A.

As shown in FIGS. 5A-5D, the EPROM cell 400 is structurally similar to the EPROM cell 400 of FIGS. 4A-4C, as a result of which the same reference numerals are used to specify structures common to both cells. do. EPROM cell 500 differs primarily from EPROM cell 400 in that EPROM cell 500 uses NLDD region 510.

The operation of cell 500 is the operation of cell 400 except that NLDD region 510 enhances the formation of high temperature electrons by increasing the lateral electric field present across the depletion region of p + contacts for NLDD and mixed signal circuits. Is the same as

Recently, the trend of CMOS mixed mixed signal signal circuits has been to use triple well structures due to the higher noise separation provided by triple-well structures.

6A-6D are diagrams illustrating a single poly EEPROM cell 600 in accordance with the present invention. FIG. 6A is a top view of the cell 600, FIG. 6B is a longitudinal sectional view taken along line 6B-6B in FIG. 6A, FIG. 6C is a longitudinal sectional view taken along line 6C-6C in FIG. 6A, and FIG. 6D is a longitudinal cross-sectional view taken along the line 6D-6D in FIG. 6A.

As shown in FIGS. 6A-6D, the EEPROM cell 600 is structurally similar to the EPROM cell 400 of FIGS. 4A-C, as a result of which the same reference numerals are used to specify structures common to both cells. do.

The EEPROM cell 600 mainly uses the EPROM cell 600, that is, the shallow n base region 610 instead of the n well 120; n base region 610, source region 114, and drain region 116 are formed in p well 612 rather than directly in p substrate 112; p well 612 is formed in deep n well 614; And the n well 614 is different from the EPROM cell 400 in that it uses what is formed in the triple well structure formed in the p substrate 112.

In addition, NLDD region 310 is formed adjacent to p + contact region 122 (NLDD region 310 enhances the electric field for more efficient hot electron generation and injection). In addition, the PLDD region 212 may be used as the NLDD region 310 instead of or in place of the NLDD region 310 as shown in FIG. 7.

One advantage of the present invention is that cell 600 is fabricated by using one additional implant mask to form the n base 610 than is required for conventional triple well CMOS processes. As a result, the doping concentration for n base 610 can be set individually (the doping concentration of n well 120 in cells 200, 300, 400, and 500 can be set individually using additional implant masks). Can be).

In general, if cell 600 is used in a mixed signal circuit, the same n base implant mask is used to form a vertical pnp bipolar device. Thus, in mixed signal circuits using vertical pnp bipolar devices, cells 600 can be formed without additional fabrication steps (with mixed signal circuits alone, doping concentration on n base 610 is independent with the use of additional implant masks). Can be set).

In operation, cell 600 applies a negative supply voltage -Vcc to p + contact region 122; ground the p substrate 112, the source region 114, the drain region 116 and the p well 612; It is programmed by applying a positive supply voltage Vcc to the n + contact region 410 and the deep n well 614. Source and drain regions 114 and 116 may be generally floated.

The voltage applied to the n + contact region 410 is applied on n base 610 which reverse biases both the p well for the n base junction and the n base for the p + contact junction. Thus, with cells 400 and 500, cell 600 also eliminates parasitic bipolar transistors of cells 200 and 300.

Also, the potential for n base 610 is equal to the positive supply voltage Vcc and the coupling ratio of n base to floating gate is about 0.8. As a result, the potential for the floating gate 134 is about 0.8 Vcc. Thus, substantially the same vertical electric field is formed in cell 600 as formed by cells 400 and 500.

As a result, the vertical electric field across the tunnel oxide layer 210 of the cell 600 also causes a depletion region to form on the surface of the p + contact region 122, increasing the potential at the p + contact region 122.

In addition, the vertical electric field is large enough to adjust the band-to-band tunneling of the electrons so that the p + contact region 122 accumulates on the surface of the p + region 122.

Thus, when band-to-band electrons drift into the depletion region of the NLDD reverse biased to the p + contact junction, the strong lateral electric field across the junction accelerates the electrons to have ionization collisions to form band-to-band hot electrons.

In addition, electrons generated in the depletion region of the NLDD reverse biased (via the n base) relative to the p + contact junction are accelerated by the strong side electric field across the junction to have ionization collisions to form thermal high temperature electrons. Both band-to-band and thermal hot electrons initiate an avalanche process to generate a large number of hot electrons. With cells 400 and 500, both potentials of floating gate 134 attract hot electrons to penetrate tunnel oxide layer 210 and begin to accumulate on floating gate 134.

In addition, with cells 400 and 500, the band-to-band electrons at the surface of p + contact region 122 and the heat generated electrons at the surface of NLDD region 310 are also transferred to the floating gate (Fowler-Nordheim tunneling). 134).

When formed in the NOR array, the program operation can be performed in cells in one column or cells selected in one column. For example, a plurality of cells 600 are arranged in a NOR array in which each p + contact region 122 is electrically connected together in a row of p + contact regions, and each n + contact region (in a row of n + contact regions) 410 are electrically connected together, where each drain region 116 is electrically connected together in one row of drain regions, and when each source region 116 is electrically connected together in one row of source regions, 1 Cell 600 selected in the cell of the column applies + Vcc to the n + contact region and grounds the source region in the column; It is programmed simultaneously by applying -Vcc to the p + contact region, grounding the drain region corresponding to the row of cells in the column to be programmed, and grounding the p well 612 (ground and + Vcc are always at the substrate 112 and deep). n well 614, respectively). Unselected columns of the array have a ground applied to the n + contact region. As a result, program disturb can be ignored.

Cell 600 applies about 0.5 volts (in a 0.35 micron process apparatus) to drain region 116; Ground the substrate 112, the source region 114, the p well 612; Then, it is read by applying the power supply power supply + Vcc to the deep n well 614. In addition, the power supply voltage + Vcc is 1) either of the p + and n + contact regions 122 and 410, such as the cell 100 of the prior art, or 2) the p + contact region 122, which floats like the cell 400. (n + contact region 410).

In addition, if the doping concentration of n base 610 is increased over that used to form n well 120 at, for example, about 1 × 10 ¹⁹ to 1 × ^{10 20} atoms / cm ³ , about 0.5 to drain region 116. Applying a bolt; Ground the substrate 112, the source region 114, the p well 614; Applying a power supply voltage + Vcc to deep n well 614; And while plotting p + contact region 122; The cell 600 can also be read by inputting the power supply voltage + Vcc only to the n + contact region 410 (in general, when the boron is implanted to set the threshold voltage of the CMOS transistor, the n base 610 is masked). Low doping concentration may be used).

When the doping concentration is high on the surface of the n base 610, when the read voltage is applied only to the n + contact region 410, it is finely depleted, or the surface only has electrons continuously. As a result, the coupling ratio is kept high.

However, as the concentration of impurities on the surface of n base 610 decreases, the read voltage applied only to n + contact region 410 causes the depletion region to increase and eventually reverses as described for cell 100. As a result, the concentration of reducing impurities on the surface of the n base 610 causes a reduction in the coupling ratio.

As previously described, each of the cells 600 in the selected column of cells, when formed in a NOR array, has + Vcc (if high surface impurity concentrations are present). 1) p + and n + contact regions of each cell of the cells in the selected column. It is read simultaneously by applying to both of 122 and 410, 2) to the p + contact region 122, or 3) to the n + contact region.

In addition, ground is applied to the source region 114 of each cell in the selected column of cells; Ground is applied to each of the p + contact regions in each row of the selected column, and + 0.5V is applied to each of the drain regions 116; Ground is applied to the p well 612.

The unselected column of the array plots both n + contact region 410 and source region 114 when Vcc is applied to both p + and n + contact regions 122 and 410 on the selected face, and in the selected column If Vcc is applied only to the p + contact region 122, the source region 114 is plotted, and if Vcc is applied only to the n + contact region 410 in the selected column, then n + contact region 410 and the source region 114 Apply ground to the

According to the present invention, cell 600 applies -Vcc to p + contact region 122, n base 610 (via n + contact region 410), and p well 612; + Vcc is applied to deep n well 614; Ground the substrate 112; Ground or float drain region 116; And a positive source voltage of + Vcc or greater is erased by edge Fowler-Nordheim tunneling by applying from source 114 to source region 114 sufficient to induce Fowler-Nordheim tunneling from floating gate 134.

As a result, while the potential on the floating gate 134 is close to -Vcc, the entire n base and p wells are biased at about -3.3V. (Considering the coupled coupling from n base 610 and p well 612, about -3.3 V will be present on the floating gate. Considering the total electrons on the floating gate, this voltage is lower than -Vcc.) Therefore, a positive voltage of + Vcc or more, which ejects charge in addition to other erase bias voltages, must be applied to the source region 114 to induce edge Fowler-Nordheim tunneling in a 0.35 micron process device.

For example, if cell 600 is fabricated with a 0.35 micron photolithography process, a full voltage of at least about 7 volts is sufficient to induce Fowler-Nordheim tunneling using a Vcc voltage of 3.3 volts and a source voltage of about +4 volts. Is applied over the gate oxide layer 130.

As described above, the gate oxide layer 130 is thicker than the control gate oxide layer 210 (about 70 GPa for layer 130 as compared to about 55 GPa thick for layer 210). Thicker gate oxide layer 130 not only has a smaller tunneling current from the floating gate (due to the thicker oxide) to the source edge (during erasure), but also a larger coupling ratio from the n base to the floating gate and from the source to the floating gate. Produces a smaller coupling ratio.

In addition, the total voltage drop across the source junction is about -2 Vcc and lower than the breakdown voltage to minimize hot carrier generation. Thus, LDD structure 618 is used adjacent to the source.

When formed in a NOR array, as described above, the erase operation is performed on the entire array, one block of cells, or a selected column of the array. If less than the entire array is erased, the p + and n + contact regions 122 and 410 of the cell are grounded in the unselected column.

Various other embodiments of the embodiments of the invention described herein can be used to practice the invention. For example, the present invention applies the same proportional to 0.25 and 0.18 micron photolithography processes where the bias voltage is scaled down.

Accordingly, the following claims define the scope of the present invention, and therefore, structures within the scope of these claims and their equivalents are also protected.

The present invention provides that band-to-band tunneling to induce hot electron injection is at least 100 times more efficient than channel hot electron programming previously used to program a single poly EPROM cell, and cell 600 forms an n base 610. Only one implant mask is needed, which is more than is needed for a conventional three well CMOS process, and the cell 600 is required to form an n base 610 than is needed for a conventional three well CMOS process. Create only one implant mask. Thus, it is possible to provide a single poly EEPROM capable of both program and erase in low voltage environments.

Claims (6)

A memory cell formed of a semiconductor material of a first conductivity type, A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer having a thickness and formed on the channel region; A tunnel oxide layer having a thickness and formed on the control gate region; And And a floating gate formed on the gate oxide layer, the tunnel oxide layer, and a part of the isolation region. A method of programming a memory cell formed in a first conductivity type semiconductor material, the method comprising: A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer formed on the channel region; A tunnel oxide layer formed on the control gate region; And A method of applying a programming bias voltage of a memory cell having the gate oxide layer, the tunnel oxide layer, and a floating gate formed on a portion of the isolation region may include: Applying a first voltage having a negative value to the first contact region; Applying a second voltage greater than the first voltage to the second contact region; And Grounding the second cell; The programming bias voltage causes charge carriers, defined as majority carriers in the base region, to accumulate on the floating gate. A method for erasing memory cells formed in a first conductivity type semiconductor material, A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer formed on the channel region; A tunnel oxide layer formed on the control gate region; And A method of applying an erase bias voltage of a memory cell having the gate oxide layer, the tunnel oxide layer, and a floating gate formed on a portion of the isolation region may include: Applying the first voltage to the first contact region; Applying the first voltage to the second contact region; Applying the first voltage to the second well; And Applying a second voltage greater than the first voltage to the source region, And wherein the erase bias voltage causes charge carriers to flow from the floating gate, defined as majority carriers in the base region. A method of reading a memory cell formed on a first conductivity type semiconductor material, A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer formed on the channel region; A tunnel oxide layer formed on the control gate region; And A method of applying a read bias voltage of a memory cell having the gate oxide layer, the tunnel oxide layer, and a floating gate formed on a portion of the isolation region, includes: Applying a first voltage to the first contact region; Plotting the second contact region; Applying a third voltage to the second well; Applying a fourth voltage to the drain region; And Applying the third voltage to the source region; Said read bias voltage causes a current to flow from said drain region to said source region when said cell is not programmed. A method of reading a memory cell formed on a first conductivity type semiconductor material, A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer formed on the channel region; A tunnel oxide layer formed on the control gate region; And A method of applying a read bias voltage of a memory cell having the gate oxide layer, the tunnel oxide layer, and a floating gate formed on a portion of the isolation region, includes: Plotting the first contact region; Applying a first voltage to the second contact region; Applying a third voltage to the second contact region; Applying a fourth voltage to the drain region; And Applying the third voltage to the source region; The read bias voltage causes a current to flow from the drain region to the source region when the cell is not programmed. A method of reading a memory cell formed on a first conductivity type semiconductor material, A first well of a second conductivity type formed in said semiconductor material; A second well of a first conductivity type formed in said first well; A source region of a second conductivity type formed in said second well; A drain region of a second conductivity type formed in said second well; A channel region defined between the source and drain regions; A base region of a second conductivity type having a surface and formed in said second well; A separation region formed in the second well to separate the source region, the drain region, and the channel region from the base region; A first contact region of a first conductivity type having a surface and formed in said base region; A second contact region of a second conductivity type disposed in the base region and spaced apart from the first contact region; A lightly doped region of a second conductivity type formed adjacent to the first contact region such that the surface of the first contact region is adjacent to the surface of the base region and the surface of the lightly doped region; A control gate region defined between the lightly doped region and the isolation region; A gate oxide layer formed on the channel region; A tunnel oxide layer formed on the control gate region; And A method of applying a read bias voltage of a memory cell having the gate oxide layer, the tunnel oxide layer, and a floating gate formed on a portion of the isolation region, includes: Applying a first voltage to the first contact region; Applying a first voltage to the second contact region; Applying a third voltage to the second contact region; Applying a fourth voltage to the drain region; And Applying the third voltage to the source region; The read bias voltage causes a current to flow from the drain region to the source region when the cell is not programmed.