KR19990079979A - Frame Cache Approach to Reduce Processor Access Time in Multithreading - Google Patents

Abstract

The present invention provides a processor access time in a multi-threading scheme in which multiple sections of cache memory are sequentially processed in order to improve processor utilization and throughput while operating multiple threads in a system. A method of accessing a frame cache for reducing a frame cache, the method of accessing a frame cache for reducing a processor access time in a multithreading method using a prefetching method based on frame scheduling, the processor When a frame is called, arbitrary frames among the plurality of frames are currently in an executable state when accessed by the processor, and the set of frames in such an executable state is connected to the frames according to the prepared priority in the frame. Ordered by pointer It is by allowing the processor to carry out these frames in sequence to the sequence set, the invention in which the processor and the shelf wear can reduce but not to interfere with each other when accessing the cache memory access time does not occur.

Description

Frame Cache Approach to Reduce Processor Access Time in Multithreading

The present invention relates to a multithreading scheme, and in particular, divides the cache memory into two areas to improve processor utilization and throughput while operating multiple threads in the system. The present invention relates to a frame cache access method for reducing processor access time in a multi-threading scheme for sequentially processing.

In general, the multithreading method is divided into a software method and a hardware method. First, the software method is to use a compiler to execute a program in a form of thread execution code suitable for a multithreading execution method.

This type of structure is so important that the role of a frame is called a frame-based performance structure. The frame stores local variable values that are most used by the processor, and shares data among threads. It also serves as a unit of work for parallel processing, and because there is a problem that the processor does not reduce the access latency when accessing.

However, as described above, the cache memory may be connected between the local memory and the processor as a method for reducing the time for the processor to access the frame data. In this case, the processor may be executed to increase the success rate of accessing the cache memory. Scheduling information, which is the order of execution of the frames, is included in the form of a ready queue in the frame structure so that when the current frame is being performed, the next frame is loaded on the ready queue and loaded into the frame cache in advance. do.

However, at this time, when the processor accesses data stored in the cache memory and at the same time accesses the cache memory for preloading, the cache memory cannot handle both simultaneously and there is a problem that a collision occurs, and the current frame When the area of the cache memory to be inserted and the data is overlapped, there is a problem that the valid data of the current frame is evicted from the cache memory by the preload operation.

An object of the present invention is to solve the above problems, the cache memory connected between the processor and the local memory divided into two memory areas to operate independently of each other by the processor and the preloader approach each other It is to provide a frame cache approach to reduce the processor access time in a multi-threading scheme to avoid collisions.

In the multi-threading method of the present invention for achieving the above object, an access method of the frame cache for reducing the processor access time, the satellite signal control apparatus of the set-top box, the pre-input method based on frame scheduling (frame scheduling) In the method of accessing a frame cache to reduce the processor access time in the multi-threading scheme used, when the processor calls a frame, arbitrary frames among a plurality of frames are currently executable upon access by the current processor. The set of frames in such an executable state is determined by the connection pointers of the frames according to the prepared priorities within the frames so that the processor sequentially executes the frames. It features.

1 is a flowchart illustrating a method of accessing a frame cache in a multi-threading scheme of the present invention.

2 is a schematic diagram showing a process of alternately operating the cache memory of the present invention.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment according to the spirit of the present invention "method of the method of accessing the frame cache for reducing the processor access time in the multi-threading method" as follows.

As shown in FIG. 1, in the method of accessing a frame cache memory in the multi-threading scheme of the present invention, an activation tree structure is a tree structure in which frames generated when a processor calls a frame are activated. The figure shows a darkened portion of the nodes of a plurality of frames, showing a set of frames that are currently executable upon access by the processor.

The set of frames in the executable state is determined by the connection pointers of the frames according to the priorities already prepared in the frames, and the processors sequentially execute the frames.

The inside of one frame activated for the execution of such a code block includes a code block base indicating a start address of the code block, and a ready frame link connecting frames that are activated and ready to be executed. ready frame link), local variable storage for storing frame local variables, sync counter for storing counter variables for thread synchronization, and information on threads ready to run. It consists of a continuation vector part.

And a program consists of a collection of code blocks, one of which consists of a thread code part and a message processing part for a function foo, for example. It will represent a function or a loop body.

When a code area is called once to provide a data area for such code blocks to be executed while the program is running, there is a structured memory space called a frame. The frame is a structured memory area that provides a data storage environment for storing local variables for the code block to be executed.

In the multi-threading scheme of the present invention, the frame cache memory approach used in the frame cache approach to reduce the processor access time is based on frame scheduling unlike the conventional approach used in the cache memory. Use the preload method. The frame cache memory is divided into two areas that are independently accessed, a current area and another area. Here, the current area refers to an area used for a frame currently being activated and performed, and the next area refers to an area used for prefetching data in a next frame on frame scheduling.

As such, the cache memory is divided into two regions, one of which is an area used by the processor to refer to data of a frame currently being executed, and the other cache memory area is accessed by a preloader to process the processor. Is the area to insert the data to perform next.

In addition, these two areas are divided into even and odd frames in order to continue using the data of the cache area that was previously used even when a specific frame is reactivated. In this case, the criteria for distinguishing the even and odd frames are used. Is based on the frame start address.

The area approached by the preload is called a shadow cache, and FIG. 2 shows the structure of the shadow frame cache.

In the multi-threading scheme of the present invention as described above, the operation and efficiency of the frame cache access method for reducing the processor access time will be described.

As shown in Fig. 2, when the processor approaches the current area of the frame cache while executing the current frame (bold solid line in Fig. 2), the preloader reads the next frame data on the preparation queue (dotted line in Fig. 2). Put it in the next area of the shadow cache. As such, the data paths of the processor and the preloader for the two regions exist independently of each other by accessing the odd frames when the processor approaches even frames. What was in the current area becomes the next area to perform the prefetch operation, and what was in the next area becomes the current area to serve the cache request.

In addition, the cache access area of the processor is also switched to use the data path for the current area before the change, after the frame switch to use the data path to the next area.

In addition, as described above, the data path of the preloader is also changed at the time of context switching so that one frame data is loaded only in one area and not in the next area, thereby maintaining cache consistency for both areas.

And even if a specific frame is activated again, all frames are divided into even and odd frames, so that valid data of the previously used cache area can continue to be used.

Using this starting address, frames are divided into odd and even numbers, and the cache area is fixed to an area for odd frames and even frames, so that only odd frames can be loaded in an area designated as a cache area for odd frames. Only the even frames can be loaded in the area designated as the cache area for the even frames.

At this time, if the area of the cache memory in which the currently executing frame is working is an area for odd frames only, the next area of the cache memory area for preloading is an area for loading even frames only. Therefore, the updated data does not need to be updated in the memory every frame switching, and even if the modified data remains in the previously used cache area, the cache consistency is maintained by working in a new area different from the previous one.

This method, on the contrary, means that only odd frames are subject to preload when an odd frame is being executed. On the preparation queue, the next frame is also performed during the odd frame since the odd and even frames are not always in standby. In addition, if the odd number is not pre-filled or the search is performed until an even frame is generated according to the preparation queue, in this case, if the preparation queue of the frame is operated separately for odd and even numbers, Since the next frame for prefetching can be selected directly from the even preparation queue when an odd frame is being performed, prefetching is performed unless the preparation queue is empty.

Accordingly, when the work on the current frame is completed, as shown in FIG. 2, the switching of the frame is also changed with the switching of the two regions of the cache memory.

In the software method, multithreading plays a role of a compiler for controlling the creation of threads and the execution structure. The compiler analyzes a program written in a higher level language to find a remote memory access and sequentially accesses code without interference. Creates a set of object codes in a form suitable for multithreaded execution constructs by making them into bundles that can be executed.

The data in the frame structure are local variables used in one code block, and these data are shared among thread codes.

In addition, since a code block represents a function or a block of code that is repeatedly executed, locality is well represented between frame data as in a general program.

In addition, it is desirable to use cache memory for frame data in order to shorten the access time of frame memory that provides a basic environment for processor execution and to make good use of locality existing between variables.

In the multi-threading scheme of the present invention configured as described above, the frame cache access method for reducing the processor access time may be performed by separating the cache memory connected between the processor and the local memory into two memory regions and operating independently of each other. In the multi-threaded processor node structure, the cache memory is used to reduce the access time while preventing the processor and the preloader from accessing the cache memory, thereby improving access performance.

Claims (13)

In the frame cache approach to reduce the processor access time in the multi-threading method using a frame scheduling based on frame scheduling, when the processor calls a frame, arbitrary frames among a plurality of frames are selected. The processor is in an executable state when accessed by the current processor, and the set of frames in the executable state is determined by the connection pointer of the frame according to the prepared priority in the frame. Approach to the frame cache to reduce the processor access time in the multi-threading method characterized in that to perform their frames sequentially. The method of claim 1, wherein the inside of the active frame includes a code block base indicating a start address of a code block, a ready frame link connecting frames that are activated and ready to be executed. A local variable storage for storing frame local variables, a sync counter for storing counter variables for thread synchronization, and a continuation vector for information about threads ready to run. Approach to the frame cache for reducing the processor access time in the multi-threading method characterized in that consisting of. 2. The method of claim 1, wherein the code block comprises a plurality of code blocks to form one program. 4. The method of claim 3, wherein the one code block base is composed of a thread code portion and a message processing portion for one function. Frame cache approach. 5. The method of claim 4, wherein the frame cache memory is divided into two independently accessed regions, a current region and a next region. 6. 6. The method of claim 5, wherein the current area is an area used for a frame currently being activated and executed. 6. The method of claim 5, wherein the next area is an area used for prefetching data in a next frame on frame scheduling. The method of claim 2, wherein the current area and the next area are divided into even and odd frames in order to continue using data of a previously used cache area even when a specific frame is activated again. Frame cache approach to reduce processor access time in threading. 10. The method of claim 8, wherein the even and odd frames start based on a base address of a frame. 10. The next region of claim 8, wherein if the processor approaches the current region of the frame cache while executing the current frame (bold solid line), the prefetcher reads the next frame data on the preparation queue (dashed line) and is the region of the shadow cache. In contrast, when the processor approaches even frames, the preloader is independent of each other by accessing odd frames. The method of claiming a frame cache for reducing processor access time in a multithreading scheme. 11. The method according to claim 10, wherein the data path of the preloader is changed at the time of context switching so that one frame data is loaded only in one area and not in another area, thereby maintaining cache consistency for both areas. Frame cache approach to reduce processor access time in multithreading scheme. 12. The cache consistency of claim 11 is that if one frame is interrupted and deleted from the ready queue, later the thread is reactivated and enters the ready queue. The method of the frame cache for reducing the processor access time in the multi-threading method characterized in that the instruction is executed by the access of the processor. The method of claim 1, wherein a compiler is used to control a thread creation and a performance structure of the multithreading. 3.