KR19990075517A - Video asynchronous decoder - Google Patents

Abstract

The present invention is to asynchronously design the structure in the video decoder, to operate each processor independently and to easily implement the entire system considering only the adjacent interface signal, the present invention is to input the system bitstream in the system decoder After receiving the video bitstream and the audio bitstream separately, the video parser decodes the header of the video bitstream to separate the data for each slice and adds the board ID for each slice's vertical address to create the slice bitstream asynchronously. After the output, the slice bitstreams are asynchronously decoded by the plurality of slice decoders to generate pixel data for the macroblock, and the motion compensation processor performs motion compensation to generate and output the actual image pixel data. It is possible to operate the processing unit independently and considering only the adjacent interface signals to facilitate the implementation of the entire system.

Description

Video asynchronous decoder

The present invention relates to a video decoding apparatus, and more particularly, to an apparatus designed to asynchronously design a structure in a video decoder, thereby allowing each processor to operate independently and to facilitate implementation of the entire system in consideration of only adjacent interface signals.

In general, a video decoder is a device for decoding an input video signal, and is used for HDTV (High Definition TeleVision, High Definition Television).

The conventional video decoder outputs image data by decoding the input bitstream by performing system decoding, parsing, slice decoding, and motion compensation.

Here, the system decoding function outputs the input system bit stream by separating the video bit stream and the audio bit stream, and the parsing means decoding the header of the video bit stream and separating data for each slice. . In addition, slice decoding refers to decoding a slice bitstream of a video bitstream, and motion compensation refers to generating and outputting actual image pixel data by performing motion compensation (MC) of the decoded slice bitstream.

However, since the conventional video decoder processes the slice bitstream by the parsing function and performs the slice decoding synchronously, the system must be implemented in consideration of the synchronization of the entire interface signal. There was a problem.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to design the structure asynchronously in a video decoder, so that each processing unit operates independently and only the adjacent interface signals are considered. The present invention provides a video asynchronous slice decoder that facilitates the implementation of the.

In order to achieve the above object, the video asynchronous slice decoding apparatus according to the present invention,

A system decoder which receives the system bitstream and outputs the video bitstream and the audio bitstream separately; Receives the video bitstream from the system decoder and decodes the header of the video bitstream to separate the data for each slice, and adds a board ID (ID) for each slice vertical address to asynchronously slice the bitstream. An output video parser; A plurality of slice decoders for asynchronously decoding a slice bitstream of the video parser to generate pixel data for a macroblock; Technical features of the present invention include a motion compensation processor that receives pixel data of the slice decoder and performs motion compensation to generate and output actual image pixel data.

1 is a block diagram of a video asynchronous decoding device according to the present invention;

FIG. 2 is a detailed block diagram of the video parser in FIG. 1;

3 is a detailed block diagram of a slice decoder in FIG. 1;

4 is a detailed block diagram of FIG. 3;

5 is a detailed block diagram of an input processing unit of FIG. 4;

6 is a detailed block diagram of a variable length coder in FIG. 4;

FIG. 7 is a detailed block diagram of an output asynchronous control unit in FIG. 4; FIG.

<Explanation of symbols for the main parts of the drawings>

10: system decoder 20: video parser

30a-30g: Slice decoder 40: Motion compensation processor

Hereinafter, an embodiment according to the technical concept of the video asynchronous slice decoding apparatus constructed as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a general video decoding apparatus.

As shown therein, a system decoder 10 for receiving a system bitstream and separating and outputting a video bitstream and an audio bitstream; Receiving the video bitstream from the system decoder 10 to decode the header of the video bitstream to separate the data for each slice, and to add the board ID for each slice vertical address and output the slice bitstream asynchronously A video parser 20; A plurality of slice decoders (30a-30g) for asynchronously decoding the slice bitstream of the video parser (20) to generate pixel data for the macroblock; A motion compensation processor 40 is configured to receive pixel data of the slice decoders 30a-30g to perform motion compensation to generate and output actual image pixel data.

Here, the input data of the video decoder is a system bitstream, and the system decoder 10 having received the bitstream separates the video bitstream and the audio bitstream, and transmits the video bitstream to the video decoder and the audio bitstream to the audio decoder. do. In the present invention, an asynchronous system is constructed to solve the timing problem between boards, which is a difficult problem when operating the entire system synchronously in the system configuration of the video decoder.

Thus, the video parser 20 receiving the video bitstream decodes the header of the video bitstream and separates data for each slice. The data separated for each slice is transferred to the slice decoders 30a-30g by adding a board ID for each slice's vertical address. The slice decoders 30a-30g are composed of seven pieces, each slice board decoding a slice bitstream of the video bitstream. Each slice decoder 30a-30g takes a slice bitstream and undergoes Variable Length Decoding (VLD), interlaced scan (ISCAN), inverse quantization (IQUANT), and IDCT. (Inverse Discrete Cosine Transform, Inverse Discrete Cosine Transform) to generate pixel data for each macro block (MB, Macro Block).

The motion compensation processor 40 receiving the pixel data performs motion compensation to generate actual image pixel data and transmit the same to the output terminal. In the present invention, a configuration of a portion in which the slice bitstream is separated by the video parser 20 and asynchronously processed by the slice decoders 30a to 30g and transferred to the motion compensation processor 40 is described.

FIG. 2 is a detailed block diagram of the video parser 20 in the video asynchronous decoder of FIG.

As shown therein, a slice start code detector 21 which detects a slice start code by decoding a header of an input video bitstream; A board ID counter (22) for including a board ID for selecting the plurality of slice decoders (30a-30g) in the slice data detected by the slice start code detector (21) to perform asynchronous bitstream processing; The video bitstream and the board ID are input, and the slice data is carried on the data bus, and the identification address for the board ID and the picture header is configured on the address bus 23.

Therefore, the slice start code detector 21 first decodes the header in the video bitstream and then detects the slice start code. The detected slice data is transferred to the board ID counter 22, and the board ID counter 22 sends the board ID for selecting each of the seven slice decoders 30a to 30g to the address generator 23. do.

The address generator 23 then receives the video bitstream and receives the board ID from the board ID counter 22. Therefore, the slice data is carried on the data bus gdata [], and the board ID and the identification address for the picture header are carried on the address bus gadrdr [].

3 and 4 are detailed block diagrams of the slice decoder 30 in the video asynchronous decoder of FIG.

As shown therein, the input asynchronous controller 31 checks the board ID for each input bitstream, stores slice bitstream data if the board ID is corresponding, and passes the data if the board ID is not the board ID; A variable length decoder decoder 32 which asynchronously decodes the variable length code with respect to the data stored in the input asynchronous controller 31; An interlaced scanning processor (33) which performs interlaced scanning of the variable long code decoded by the variable long code decoding unit (32); An inverse quantization processor (34) for performing inverse quantization of interlaced data by the interlaced scanning processor (33); An IDCT processor 35 for performing IDCT of the dequantized data by the inverse quantization processor 34; An output asynchronous control unit 36 for sequentially transmitting the data finally processed by the IDCT processing unit 35 to the motion compensation processing unit 40.

Here, the input asynchronous controller 31 includes an input processor 311 which receives an address, data and a board ID from the address generator 23 and determines whether data is present; If the data determined by the input processor 311 is present, the data is stored, and the stored data is independently processed according to the internal processing speed of the slice decoder 30 (FIFO 1 to FIFO 3) 312 to 314. It consists of

In addition, the output asynchronous control unit 36, an output FIFO for sequentially storing the data processed by the IDCT processing unit 35; And an output processor for sequentially transmitting data stored in the output FIFO to the motion compensation processor 40.

Therefore, the input asynchronous control unit 31 checks the board ID for each bitstream as the slice bitstream, and if the corresponding board ID, the input asynchronous control unit 31 inserts the slice bitstream data into the input FIFO, and passes the data if the corresponding board ID is not. Each slice data of Chapter 7 processes variable length code, interlacing, inverse quantization, and IDCT asynchronously for the data of each input FIFO, and is stored in the output FIFO. The data of each of the slice decoders 30a-30g stored in the output FIFO need only be passed when the motion compensation processing unit 40 sequentially requests data.

This will be described in detail with reference to the detailed block diagram of the slice decoder 30 shown in FIG. 4 as follows.

First, in order to operate asynchronously with each slice decoder 30 in each slice decoder 30, a FIFO is used at the input and output terminals so as not to consider a synchronization problem with other processing units.

Accordingly, the input processing unit 311 having received the input data gaddr, gdata, and the board ID determines whether there is the corresponding data and puts it into the FIFOs 312-314. The processing of the data is performed according to the internal processing speed of the slice decoder 30. It will work independently. Thus, data that has undergone variable length coding, interlaced scanning, inverse quantization, and IDCT on data stored in each FIFO 312-314 is stored in the output FIFO so that the synchronization with the next slice decoder 30 may not be considered.

In addition, the FIFO at the output stage is composed of two stages to perform a frame conversion (Conversion). The frame conversion adjusts the order of transmitting the luminance signals Y1, Y2, Y3, Y4 and the chroma signals Cb and Cr according to the DCT_TYPE macroblock parameter. The data passed to the next slice decoder 30 simultaneously transfers macroblock header data together with pixel data. The data transfer order is performed by exchanging the motion compensation processor 40, which is a next processor, with the srdny and srdx signals for each macroblock. Each slice decoder 30 of the seven chapters sends a srdyx signal, which is a signal that each is ready for data transmission. The motion compensation processor 40 sequentially checks the srdyx for each slice decoder 30 in the slice data unit, and transmits the srdx signal in the macroblock unit if it is enabled. The slice decoder 30 sends parm and YB1, YB2, YB3, YB4, Cb1, Cb2, Cb3, and Cb4 data, which are macroblock header data, to the srdx signal. Like the input stage, the output stage of the slice decoder 30 is configured to operate independently using the FIFO without considering the synchronization with the next decoder 30.

FIG. 5 is a detailed block diagram of the input processor 31 in the slice decoder 30 of FIG.

As shown in the figure, a picture header / slice data separator 315 for receiving an address, data and a board ID from the address generator 23 to separate a picture header and each slice data; A bypass unit 316 for bypassing the slice data separated by the picture header / slice data separation unit 315 and transferring the slice data to the next slice decoders 30a to 30g; A board ID comparison unit 317 for comparing slice data separated by the picture header / slice data separation unit 315 with a board ID to determine whether the slice data is identical to the corresponding board ID; As a result of the determination of the board ID comparison unit, if the board ID and the corresponding board ID of the slice data are the same, the board ID comparator includes a recursive counter 318 which sequentially writes the plurality of FIFOs 312 to 314.

Thus, gaddr, gdata, and board ID are input to separate the picture header from each slice data. The separated slice data is compared with the board ID, and if the same as the board ID, it is put in each FIFO. The recursive counter is operated on three FIFOs and sequentially written. The input gaddr, gdata is transferred to the next slice decoder 30 as it is for processing in the next slice decoder 30.

FIG. 6 is a detailed block diagram of the variable length code decoding unit 32 in the slice decoding unit 30 of FIG.

As shown therein, a FIFO read control unit 321 for controlling sequential reads of the plurality of FIFOs 312 to 314; A slice syntax decoder 322 for decoding the syntax of the slice data read according to the control of the FIFO read controller 321; A code length determiner 323 for determining a code length based on the slice syntax decoded by the slice syntax decoder 322; A code length adder 324 for adding a code length according to a code determined by the code length determiner 323 and transmitting the code length to the FIFO read controller 321; Run and level of Discrete Cosine Transform (DCT) coefficients received from the code length determiner 323 and the code length adder 324 through the slice syntax decoder 322. A run / level determination unit 325 for determining a value of Level) and transmitting it to the interlaced scanning processor 33; The slice syntax decoder 322 includes a parameter processor 326 that analyzes the slice syntax decoded and processes a parameter.

Thus, the FIFO read controller 321 sequentially reads the three FIFOs 312-314, decodes the slice headers, and delivers the slice headers to the parameter processor 326. The parameter processor then passes to the parameter FIFO of the output FIFO.

In addition, the run / level determination unit 325 receives the outputs of the code length determination unit 323 and the code length addition unit 324 to determine the run and level values of the DCT coefficients and pass them to the interlaced scanning processing unit 33.

FIG. 7 is a detailed block diagram of the output asynchronous controller 36 in the slice decoder 30 of FIG.

As shown therein, a block counter and a color difference multiplexing unit 361 and 362 that receive pixel data processed by the IDCT processing unit 35 and count block data in order, and multiplex a luminance signal and a color difference signal; A plurality of first FIFOs 362-370 for sequentially writing the luminance data and the color difference data of the block counter 361; A DCT type multiplexer 371 for multiplexing and reading data stored in the plurality of first FIFOs 362-370 according to a DCT type; A plurality of second FIFOs 372-377 for sequentially storing parameters of data processed by the IDCT processor 35 and luminance / color difference data read by the DCT type multiplexer 371; And an output data multiplexer 378 which multiplexes data of the plurality of second FIFOs 372 to 377 and transmits the multiplexed data to the motion compensation processor 40.

Thus, the pixel data of the IDCT processor 35 is counted in order by the block counter 361 into six block data (Y1, Y2, Y3, Y4, Cb, Cr) and input to the first FIFOs 363-370. . Accordingly, the luminance data Y1, Y2, Y3, and Y4 are sequentially written to the FIFOs 363 to 366 storing the luminance data, and the color difference data Cb1, Cb2, Cr1, and Cr2 are sequentially stored on the FIFOs storing the color difference data. 370 are sequentially written.

The data written to the FIFOs 363 to 370 are processed in a reverse order with respect to the luminance data with reference to the DCT_TYPE. That is, if DCT_TYPE is '0', 64 pieces are read by Y1, Y2, Y1, Y2 ...... and then 64 pieces are read by Y3, Y4, Y3, Y4 .... On the other hand, if the DCT_TYPE is '1', the second FIFOs 374-377 for storing luminance data by reading 64 pieces in order of Y1, Y2, Y3, Y4, Y1, Y2, Y3, Y4, ... Light on.

Meanwhile, the PARM [12..0] data input to the second FIFOs 372 and 373 are data for decoding the slice header and then passing the macroblock parameter to the next slice decoder 30.

Accordingly, the output data multiplexer 378 multiplexes and outputs data of the second FIFOs 372 to 377. That is, if the state of YB1, YB2, YB3, YB4 of the second FIFOs 374-377 is equal to or greater than one block of data, srdyx is passed to the next slice decoder 30, and the next slice decoder 30 According to this signal, srdx is sent. The slice decoder 30 sends PARM [] 12 times according to this signal, and then sends Y, Cb, and Cr simultaneously. That is, all data for one macroblock of an image is transmitted for one srdx signal. The data processing of the slice decoder 30 operates independently regardless of the synchronization of the other slice decoders 30 and independently performs write and read operations based on the FIFO.

As described above, according to the present invention, the structure of the video decoder is designed asynchronously, so that each processing unit is operated independently and only the adjacent interface signals are considered, thereby facilitating the implementation of the entire system.

Although preferred embodiments of the present invention have been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the video asynchronous slice decoder according to the present invention can design the structure of the video decoder asynchronously to operate each processing unit independently and to easily implement the entire system considering only the adjacent interface signals. Will be.

Claims (9)

In the video asynchronous slice decoder, A system decoder which receives the system bitstream and outputs the video bitstream and the audio bitstream separately; A video parser that receives the video bitstream from the system decoder and decodes the header of the video bitstream to separate data for each slice, and asynchronously outputs the slice bitstream by adding a board ID for each slice's vertical address; ; A plurality of slice decoders for asynchronously decoding a slice bitstream of the video parser to generate pixel data for a macroblock; And a motion compensation processor configured to receive pixel data of the slice decoder and perform motion compensation to generate and output actual image pixel data. The method of claim 1, wherein the video parser, A slice start code detector for detecting a slice start code by decoding a header of an input video bitstream; A board ID counter including a board ID for selecting the plurality of slice decoders in the slice data detected by the slice start code detector to perform asynchronous bitstream processing; And an address generator which receives the video bitstream and the board ID and transmits slice data to the data bus, and an identification address for the board ID and the picture header on the address bus. The method of claim 1, wherein the slice decoding unit, An input asynchronous controller that checks the board ID for each input bit stream and stores slice bitstream data if the board ID is corresponding, and passes the data if the board ID is not corresponding to the board ID; A variable length code decoding unit for decoding the variable length code asynchronously with respect to the data stored in the input asynchronous control unit; An interlaced scanning processor that performs interlaced scanning of the variable length code decoded by the variable length code decoding unit; An inverse quantization processing unit that performs inverse quantization of interlaced data by the interlacing processing unit; An IDCT processor configured to perform IDCT of dequantized data in the dequantization processor; And an output asynchronous controller for sequentially transmitting the data finally processed by the IDCT processor to the motion compensation processor. The method of claim 3, wherein the input asynchronous control unit, An input processor for receiving an address, data, and board ID from the address generator to determine whether data is present; And if there is data determined by the input processing unit, processing the stored data comprises a plurality of FIFOs that operate independently according to the internal processing speed of the slice decoding unit. The method of claim 4, wherein the input processing unit, A picture header / slice data separator for receiving an address, data, and board ID from the address generator to separate a picture header and slice data; A bypass unit which bypasses the slice data separated by the picture header / slice data separator and transmits the slice data to a next slice decoder; A board ID comparison unit comparing slice data separated from the picture header / slice data separation unit with a board ID to determine whether the slice data is identical to the corresponding board ID; And a recursive counter sequentially writing to the plurality of FIFOs when the board ID of the slice data and the corresponding board ID are the same, as a result of the determination of the board ID comparison unit. The method of claim 3, wherein the output asynchronous control unit, An output FIFO for sequentially storing data processed by the IDCT processor; And an output processor for sequentially transmitting data stored in the output FIFO to the motion compensation processor. The method of claim 3, wherein the variable length code decoding unit, A FIFO read control unit controlling sequential reads of the plurality of FIFOs; A slice syntax decoding unit for decoding the syntax of the slice data read under the control of the FIFO read control unit; A code length determiner configured to determine a code length based on a slice syntax decoded by the slice syntax decoder; A code length adder which adds a code length according to a code determined by the code length determiner and transmits the code length to the FIFO read controller; A run / level determination unit which receives outputs of the code length determination unit and the code length addition unit through the slice syntax decoding unit, determines run and level values of DCT coefficients, and transmits them to the interlaced scanning processing unit; And a parameter processing unit for processing parameters by analyzing the slice syntax decoded by the slice syntax decoding unit. The method of claim 3, wherein the output asynchronous control unit, A block counter and a color difference multiplexer which receives pixel data processed by the IDCT processor and counts block data in order and multiplexes a luminance signal and a color difference signal; A plurality of first FIFOs which sequentially write luminance data and color difference data of the block counter; A DCT type multiplexer for multiplexing and reading data stored in the plurality of first FIFOs according to a DCT type; A plurality of second FIFOs for sequentially storing parameters of data processed by the IDCT processor and luminance / color difference data read by the DCT type multiplexer; And an output data multiplexer which multiplexes data of the plurality of second FIFOs and transmits the multiplexed data to the motion compensation processor. The method of claim 1, wherein the slice decoding unit, If there is more than one block of data, the data transmission ready signal is passed to the next slice decoder, and the next slice decoder transmits a receive enable signal to the previous slice decoder according to the signal, and then passes the parameter processing signal to the next slice decoder first. And then transmitting luminance data and chrominance data at the same time, thereby transmitting all of the data for one macroblock of the image for one reception enable signal.