KR19990074255A - Data frequency converter and method with timing violation prevention function - Google Patents

Abstract

Disclosed are a data frequency converter and a method having a timing violation prevention function. A data frequency conversion device having a timing violation prevention function according to the present invention includes a discrete time oscillator, a clock control value, and a discrete time oscillator for sequentially adding a period of a system clock signal to generate a sequential clock control value corresponding to a period of a sub clock signal. Comparison means for comparing the first reference value and the second reference value, and outputting the compared result as a first or second level control signal, a first register for outputting data input in response to the sub-clock signal, and responding to the control signal And a multiplexer for selectively outputting the input data or the previous data output through the output terminal, and a second register for outputting the output of the multiplexer in response to the system clock signal.

Description

Apparatus and method for converting data frequency with timing violation prevention function

The present invention relates to a data frequency conversion device, and more particularly, to a data frequency conversion device and method having a timing violation prevention function capable of real-time frequency conversion of video, audio, and all data, and preventing timing violations from occurring. It is about.

In general, not only an image processing system for recording / reproducing video data, but also a communication system and other data processing systems for transmitting audio data, conventionally, two line memories or field memories are used to convert data frequencies. That is, when the frequency of the input data is f1 and the frequency of the converted data is f2, when data is written to the line memory, the data is written in synchronization with a clock signal having the frequency of f1, and the data is read from the line memory. In this case, a method of reading data in synchronization with a clock signal having a frequency f2 is used. In the case of using a field memory, the frequency of data is converted using the above-described method.

However, in the conventional data frequency converter using a line memory or a field memory, a data transmission delay time occurs. For example, there is a disadvantage that a delay of one line occurs when using line memory, and a delay of one field occurs when using field memory. In addition, there is a problem that by using the line memory and the field memory, the chip size as large as allocated to the memory increases.

The first technical problem to be achieved by the present invention is to provide a data frequency conversion device having a timing violation prevention function that can convert the frequency of data in real time using a discrete time oscillator and a comparator, and prevent the timing violation from occurring. It is.

A second technical problem to be achieved by the present invention is to provide a frequency conversion method performed in the data frequency conversion device.

The third technical problem to be achieved by the present invention is to provide a data frequency conversion device having a timing violation prevention function for converting the frequency of data in real time using a discrete time oscillator and an interpolator and preventing a timing violation from occurring. have.

A fourth technical object of the present invention is to provide a frequency conversion method performed in the data frequency conversion device.

1 is a block diagram illustrating a general data frequency conversion device using a register.

2 (a) and 2 (b) are waveform diagrams for explaining timing violations occurring in the data frequency converter shown in FIG. 1.

Figure 3 is a block diagram of a preferred embodiment for explaining a data frequency conversion device having a timing violation prevention function according to the present invention.

FIG. 4 is a block diagram illustrating a discrete time oscillator of the data frequency converter shown in FIG. 3.

FIG. 5 is a flowchart for describing a frequency conversion method performed in the data frequency conversion device shown in FIG. 3.

Figure 6 is a block diagram of another embodiment for explaining a data frequency conversion device having a timing violation prevention function according to the present invention.

FIG. 7 is a block diagram illustrating an interpolation unit of the data frequency converter of FIG. 6.

FIG. 8 is a flowchart for describing a frequency conversion method performed in the data frequency conversion device shown in FIG. 6.

In order to achieve the first object, the data frequency conversion apparatus having a timing violation prevention function according to the present invention is a discrete to sequentially add the period of the system clock signal to generate a sequential clock control value corresponding to the period of the sub-clock signal. Comparing means for comparing the time oscillator, the clock control value with the first reference value and the second reference value, and outputting the compared result as a control signal of the first level or the second level, and outputting data input in response to the sub clock signal. Preferably, the first register includes a first register, a multiplexer for selectively outputting data input in response to a control signal or previous data output through an output terminal, and a second register for outputting the output of the multiplexer in response to a system clock signal. .

In order to achieve the second task, the frequency conversion method according to the present invention inputs predetermined data output in response to the sub-clock signal as current data, and outputs the current data in response to the system clock signal to output the frequency of the data. A data frequency conversion method for converting, the method comprising: (a) generating a clock control value for generating a sub clock while sequentially adding a cycle of a system clock signal, wherein the clock control value is present between the first reference value and the second reference value; Determining whether a clock control value exists between the first reference value and the second reference value, and determining that a timing violation has occurred and generating a control signal having a first logic level, and (b) adjusting the first logic level. Selecting previous data fed back in response to the control signal having a clock control value not present between the first reference value and the second reference value; If not, determining that no timing violation has occurred and generating a control signal having a second logic level, (c) selecting the currently applied data in response to the control signal having a second logic level, and (b Or) outputting the data selected in step (c) in response to the system clock signal.

In order to achieve the third task, the data frequency conversion apparatus having the timing violation prevention function according to the present invention inputs the N + 2th data from the outside and outputs the input data in response to the sub clock signal N + 1. The first register outputting the first data and the N + 1 th data are input, and the second register outputting the N + 1 th data as the N th data in response to the system clock signal, and the N th data is the system clock. A third register outputting the N-th data in response to the signal, a discrete time oscillator generating a sequential clock control value corresponding to the period of the sub clock signal by sequentially adding periods of a system clock signal, and a clock control value; Comparison means for comparing the first reference value and the second reference value and outputting the compared result as a high or low level control signal, the N + 1th data, the Nth data The interpolation value of the N-th data is input and the interpolation value of the N-th data or the sum of the N + 1-th data and the N-th-1 data divided by 2 is selectively selected in response to the control signal. The interpolation means for outputting, and the fourth register for outputting the output of the interpolation means in response to the system clock signal are preferable.

In order to achieve the fourth task, the data frequency conversion method according to the present invention includes generating a clock control value for generating a sub clock while sequentially adding a cycle of a system clock signal, wherein the clock control value is equal to the first reference value. Determining whether the second reference value exists between the first reference value and the second reference value, determining that a timing violation has occurred, and generating a control signal having the first logic level; a) selecting a half value of the sum of the N + 1th data and the N-1th data of the applied data in response to the control signal having the first level, wherein the clock control value is equal to the first reference value; If it is not present between the second reference values, determining that a timing violation has not occurred, and generating a control signal having a second logic level, (b) responding to a control signal having a second logic level, the Nth number; Selecting the applied data, performing interpolation using the data selected in step (c) (a) or (b), the period and the clock control value of the sub-clock signal, and performing the interpolated data. It is preferably configured to output in response to the clock signal.

Hereinafter, a data frequency converter having a timing violation prevention function according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a general data frequency conversion apparatus using a register, and is composed of registers 12 and 14.

Referring to FIG. 1, the register 12 outputs data input in response to the clock signal f1, and the register 14 outputs the output of the register 12 in response to the clock signal f2 to output the output terminal DOUT. Will output via Here, the data input through the data input terminal DIN is not limited to the image data used in the image processing system, and can be applied to general video, audio and all kinds of data.

2 (a) to 2 (b) are waveform diagrams for explaining the case where a timing violation occurs in the data frequency converter shown in FIG. 1, and 2 (a) is a clock signal f1 having a first frequency. 2 (b) represents a clock signal f2 having a second frequency.

That is, FIG. 2 illustrates a case where timing violations of clock signals f1 and f2 having two types of frequencies that are asynchronous occur. Assuming that clock signal f2 is a system clock signal, clock signal f1 It can be regarded as a sub clock signal. In addition, Q denotes the period of the first clock signal or the sub clock signal f1, P denotes the period of the second clock signal or the system clock signal f2, and α denotes the allowable value of the setup timing violation. Β denotes the allowable value of the hold timing violation.

As in the related art, it can be seen that in a data frequency converter which converts the frequency of data without using a memory, a setup / hold timing violation may occur when latching data due to the use of a clock signal having two asynchronous frequencies. . That is, in the case of converting the frequency of the input data using the two asynchronous clock signals f1 and f2, the two clock signals may rise at the same time or almost constant time. That is, when the rising edge of the second clock signal f2 is between the rising edge of the first clock signal f1 and β, a data hold time violation occurs, and the rising edge of the second clock signal f2 is the clock signal. If it is between the rising edge of (f1) and α, a data setup time violation will occur.

Therefore, the present invention implements a data frequency conversion device capable of real-time frequency conversion since no memory is used, and also prevents setup / hold timing violations occurring at the time of data latching by using different asynchronous clock signals. I would like to.

Figure 3 is a block diagram of a preferred embodiment for explaining a data frequency conversion apparatus having a timing violation prevention function according to the present invention, a discrete time oscillator (DTO) 32, a comparator 34, a first It consists of a register 35, a multiplexer 36 and a second register 38.

The DT0 32 shown in FIG. 3 is implemented as a P: Q ratio counter or a modulo counter, and the sub clock signal is obtained by sequentially adding the period P of the system clock signal f2. In order to generate (f1), a sequential clock control value Q _N corresponding to the period Q of f1 is generated. Here, P and Q represent integer values of the clock signal f2 and the clock signal f1, respectively. That is, the N-th clock control value P _N of the sub clock signal f1 is generated from the period P of the system clock signal f2 using the modulo Q counting method. As described above, P represents an integer period of the second clock signal (or system clock signal) f2, and Q represents an integer period of the first clock signal (or sub clock signal) f1. The comparator 34 compares the current clock control value Q _N of the first clock signal f1 output from the DTO 32 with the first reference value REF1 and the second reference value REF2. The corresponding control signal CNT is output. The control signal CNT output from the comparator 34 is applied as the selection signal of the multiplexer 36. The register 35 outputs the input data D _{N + 1} in response to the sub clock signal f1, and the output data D _N is applied to the second input of the multiplexer 35. Here, it is assumed that the data D _N is data input at the present time. The multiplexer 36 feeds back the data output through the output terminal OUT, that is, the previous data to the first input, applies the current data D _N to the second input, and responds to the control signal CNT. Outputs one input or a second input selectively. That is, the multiplexer 36 outputs the currently input data D _N or the feedback previous data D _N-1 according to the control signal CNT. In addition, the register 38 inputs current data or previous data selectively output from the multiplexer 36, and outputs the input data in response to the system clock signal f2.

FIG. 4 is a block diagram for explaining the discrete time oscillator (DTO) 32 of the data frequency converter shown in FIG. 3, and is comprised of an adder 42 and a register 44. As shown in FIG.

The adder 42 shown in FIG. 4 adds the period P of the second clock signal f2 and the output of the register 34, and generates the added result as a clock control value Q _N , which clock The control value Q _N is applied to the input of the register 44. Here, the register 44 is a modulo Q register which outputs the remainder of the value obtained by dividing Q by the period P being continuously added.

In general, the reason for using the DTO 32 is when the second clock signal f2, which is a system clock signal, is in a proportional relationship falling below the decimal point without being divided by a constant integer multiple of the first clock signal f1, which is a subclock signal. Since the sub clock signal cannot be generated by dividing the system clock signal f2, the above-described discrete time oscillation method is used.

That is, the discrete time oscillator 32 is a P: Q ratio (RATIO) counter using a modulo counting method, and the period P of the system clock signal f2 with respect to the period Q of the sub clock signal f1. Counting sequentially. Accordingly, the discrete time oscillator 32 generates the current clock control value Q _N while continuously adding the period P of the second clock signal (or system clock signal) f2 using a modulo counting method. do. If the above-described operation of the DTO 32 is described in more detail, first, the periods P and Q can be obtained from the following equation.

Here, the minimum value of Q multiplied by f1 / f2 is represented by 2 ^N so that P can be expressed as an integer. That is, as shown in FIG. 4, the reason for representing the value of Q as 2 ^N is to implement a modulo counter. Therefore, Q is a maximum, so that any register may represent, if, is the Q 2 is ^N when using the N-bit register. Therefore, when the value of the register 44 is smaller than Q while the period P of the system clock signal f2 is continuously added in the DTO 32, the value is output as it is as a clock control value, that is, _QN . If the value is greater than or equal to Q, that is, if an overflow occurs, the rest of the value obtained by dividing Q from the value is taken and output as the clock control value Q _N. That is, for each clock cycle, P is added to produce a series of digital values that increase linearly. Therefore, the output clock control value Q _N is expressed as follows.

Q _N = (P + Q _N-1) moduloQ

FIG. 5 is a flowchart for describing a frequency conversion method performed in the data frequency conversion apparatus having the timing violation prevention function shown in FIG. 3, and generates a sub clock signal while sequentially adding a period P of a system clock signal. Generating a clock control value Q _N (operation 510), determining whether the clock control value exists between the first reference value and the second reference value (operation 515), and the clock control value is the first operation If it exists between the reference value and the second reference value, it is determined that a timing violation has occurred, and generating a control signal of the first logic level to select previous data fed back (steps 520 to 525), and the clock control value is the first reference value If it does not exist between and the second reference value, it is determined that the timing violation does not occur, and selecting the currently applied data in response to the control signal of the second logic level (steps 530 to 535) And outputting the selected data in response to the system clock signal (operation 540). 2, 3, 4 and 5 will be described in detail with respect to the operation and frequency conversion method of the data frequency conversion device having a timing violation prevention function according to the present invention.

First, a clock control value Q _N for generating the sub clock signal f1 is generated by sequentially adding the period P of the system clock signal f2 calculated in Equation 1 above (step 510). . That is, As you add the old value of the DTO adder (42) the period (P) to the input P and the control of the clock 32, the value (Q _N) to generate a clock control value (Q _N). The comparator 34 compares the N-th clock control value Q _N output from the DTO 32 with the first reference value REF1 and the second reference value REF2 and compares the result with a control signal having 1 or 0 ( CNT). Here, the first reference value REF1 represents the allowable value of the data hold time as Q-β, and the second reference value REF2 represents the allowable value of the data setup time as Q-α. When realizing a chip, α and β are fixed to appropriate values when the process and the design specification (SPEC) to implement the chip are determined, and thus the reference values REF1 and REF2 are also fixed. At this time, the comparator 34 determines whether the output clock control value Q _N exists between REF1 and REF2 (step 515). If the clock control value Q _N exists between REF1 and REF2, it is determined that a timing violation has occurred at the present time, and thus generates a control signal CNT having a first logic level, that is, a logic '1'. Step 520). In addition, when Q _N is smaller than the first reference value RE1 or larger than the second reference value REF2, it is determined that no timing violation has occurred at the present time, and the comparator 34 determines a second logic level, that is, logic '0. In step 530, a control signal CNT having 'is generated. Therefore, if the output CNT of the comparator 34 is in the logic '1' state, the multiplexer 36 selects the previous data fed back (step 525). However, when the output CNT of the comparator 34 is in a logic '0' state, the multiplexer 36 sub-clocks the current data D _N , that is, the previous data D _{N + 1} , applied to the second input. In response to f1, the output data is selected (step 535). That is, when a timing violation occurs, the register 38 does not latch the new data D _N in response to the system clock signal f2, and maintains the state of the previous data. That is, the register 38 outputs latched data, that is, current data or previous data, in response to the system clock signal f2 (operation 540). That is, the data applied in response to the sub clock signal f1 can be converted to the frequency of the system clock signal f2 using the above method, and the timing point at which a timing violation occurs can be detected.

FIG. 6 is a block diagram of another embodiment for explaining a data frequency conversion apparatus having a timing violation prevention function according to the present invention, and includes a first register 600, a second register 610, a twenty-third register 615, and discrete. It is composed of a Discrete Time Oscillator (DTO) 620, a comparator 630, an interpolation block 640, and a fourth register 650.

The first register 600 shown in FIG. 6 outputs the applied data, that is, the N + 2th data D _{N + 2} as N + 1th data in response to the first clock or sub clock signal f1. The second register 610 inputs the applied N + 1th data D _{N + 1} and converts the input data into the Nth data D _N in response to the second clock signal f2. Output Here, the N-th data D _N is a signal delayed by one period of the N + 1 th data D _{N + 1} . In addition, the third register 615 and outputs it as the N-th data (D _N), the input and the second clock signal, the data input in response to (f2) The N-1-th data (D _N-1). Here, the N-1-th data (D _N-1) is the N-th data and the delayed data by one period of the (D _N), (N + 1) th data delayed by two periods for the (D _{N + 1)} data to be. These data D _{N + 1} , D _N , D _N-1 are applied as sequential input data of the interpolator 640, respectively. The DTO 620 is implemented as a P: Q ratio counter having a structure as shown in Fig. 4, inputting a period P of the system clock (or second clock signal) f2, and giving a period P Sequential clock control values Q _N are generated to generate the sub clock (or first clock signal) f1. The comparator 630 compares the clock control value Q _N output from the DTO 520 with the preset first reference value REF1 and the second reference value REF2, and compares the result with a logic '1' or '0. It outputs as a control signal CNT having '. In addition, the interpolator 640 is a block for removing high frequency noise generated when the frequency of the data is converted, and the data D _N-1 after one clock period in response to the control signal CNT output from the comparator 630. ) And the previous data (D _{N + 1} ) are interpolated based on 1/2 of the data or interpolated based on the current data, that is, D _N. That is, the data interpolated by the interpolator 640 is output through the output terminal DO. The fourth register 650 latches the data output from the interpolator 640 in response to the system clock signal f2, and outputs the latched data through the output terminal OUT. Here, since the structure and operation of the DTO 620 is similar to that shown in Figure 4, a description thereof will be omitted.

FIG. 7 is a detailed block diagram illustrating the interpolation unit 640 of the data frequency converter shown in FIG. 6, which includes an adder 71, a divider 72, a multiplexer 73, a register 75, and a multiplier ( 76, 77, an adder 78, and a divider 79.

That is, the adder 71 shown in FIG. 7 adds the applied N + 1 th data D _{N + 1} and the N-1 th data D _N-1 , and the divider 72 adds ₁ to the added value. / 2 is obtained to generate an output (K _N). The multiplexer 73 selectively outputs the N-th data D _N applied to the first input and the data K _N applied to the second input in response to the control signal CNT. The register 75 outputs the output of the multiplexer 73 as the N-th data in response to the system clock signal f2. The multiplier 77 multiplies the output of the register 65 by the clock control value Q _N output from the discrete time oscillator 520, and the multiplier 76 multiplies the output of the multiplexer 73 with (QQ _N ). Multiply. The adder 78 adds outputs of the multiplier 76 and the multiplier 77, and the divider 79 divides the result added by the adder 78 by Q to generate interpolated data. The interpolated data is output through the output terminal DO of the interpolator 640.

FIG. 8 is a flowchart for describing a data frequency conversion method performed in the data frequency conversion apparatus shown in FIG. 6, and includes a clock control value for generating a sub clock signal while sequentially adding a period P of a system clock signal. step (the step 810) for generating a (Q _N), the clock control value (Q _N) is the first reference value and the step of determining whether existing between the second reference value (the step 815), the clock control value (Q _N) If it exists between the first reference value and the second reference value, it is determined that a timing violation has occurred, and a control signal of the first logic level is generated, and half of the value obtained by adding N + 1st data and N-1th data is selected. If the clock control value does not exist between the first reference value and the second reference value (steps 820 to 825), it is determined that a timing violation does not occur, and a control signal of a second logic level is generated to apply the Nth time. The selected data ( Steps 830 to 835, interpolation is performed using the selected data, the period and the clock control value of the sub clock signal, and outputs the interpolated data in response to the system clock signal (steps 840 to 850). do.

6, 7 and 8 will be described in detail with reference to the accompanying drawings with respect to the operation and frequency conversion method of the data frequency conversion apparatus.

First, the DTO 620 generates a clock control value Q _N for generating the sub clock signal f1 while sequentially adding the period P of the system clock signal f2 (operation 810). The interpolator 640 inputs the N + 1th data D _{N + 1} , the Nth data D _N , and the N−1 th data D _N-1 based on the current time point N, respectively. The multiplexer 73 of the interpolation unit 640 receives the currently applied data D _N as a first input, and the N + 1 th data D _{N + 1} and the N−1 th data D _{N. -1} ) is the second input of the sum of the data obtained by dividing by 2 (K _N ). Herein, the N + 1th data is data output by synchronizing the N + 2th data with the sub clock signal f1. That is, the comparator 630 compares the clock control value Q _N output from the DTO 620 with the first reference value REF1 and the second reference value REF2 and compares the result of the control signal with 1 or 0 ( CNT). Here, the first reference value REF1 and the second reference value REF2 are the same values as the reference values REF1 and REF2 in the data frequency converter shown in FIG. Allowance of. That is, the comparator 630 determines whether the output clock control value Q _N exists between REF1 and REF2 (step 810).

If the clock control value Q _N exists between REF1 and REF2 in step 810, that is, if REF1 ≤ Q _N ≤ REF2, the comparator 630 determines that a setup or hold timing violation has occurred at the present time. Accordingly, a control signal CNT having a first logic level, that is, logic '1' is generated (operation 820). In addition, when the clock control value Q _N is smaller than the first reference value REF1 or larger than the second reference value REF2, the comparator 630 determines that a timing violation does not occur at the present time and the second logic level is determined. That is, the control signal CNT having the logic '0' is generated. The level of the control signal may be set differently depending on the design method. Thus, when the output CNT of the comparator 630 is in a logic '1' state, the multiplexer 73 of the interpolator 640 receives a second input, that is, one in response to the control signal CNT having the logic '1'. In operation 825, 1/2 of the value obtained by adding the data before the clock D _{N + 1} and the data after the clock D _N-1 is selected. Assuming such data is K _N , the interpolator 640 performs interpolation using the period Q of the data K _N , the sub clock signal f1, and the clock control value Q _N (step 840). step). That is, the register 75 inside the interpolator 640 inputs a value of K _N , and synchronizes one clock delayed data of the input data K _N in synchronization with the second clock signal f2 (or a system clock signal). K _N-1 ) is output. Further, the data K _N output from the multiplexer 73 is multiplied by the predetermined value QQ _N in the multiplier 76 to generate the data K _N * (QQ _N ). The multiplier 77 also multiplies the control value Q _N output from the DTO 620 by the output K _N-1 of the register 75 to generate K _N-1 * Q _N. The outputs of multiplier 76 and multiplier 77 are added to each other in adder 78 and divided by Q in divider 79 to produce the following interpolation data.

DO _N = [K _N-1 * Q _N + K _N * (QQ _N )] / Q

Therefore, the N-th data D0 _N output through the output terminal DO of the interpolator 640 is applied to the input of the register 650, and the frequency is converted in response to the system clock signal or the second clock signal f2. The data is output as data (step 850).

On the other hand, if it is determined that the clock control value Q _N output from the DTO 630 is smaller than the first reference value REF1 or larger than the second reference value REF2, the comparator 630 violates the setup or hold timing violation. Is generated, and a control signal CNT having a logic '0' is generated (step 830). Therefore, the multiplexer 73 of the interpolator 640 selects the currently applied Nth data, that is, the data D _N (step 835). Therefore, the interpolator 640 interpolates in the above process using the selected data, that is, the N-th data D _N , the period Q of the sub clock signal f1, and the clock control value Q _N. In operation 840, the process is performed. That is, the data output through the multipliers 76 and 77, the adder 78, and the divider 79 inside the interpolation unit 640 is expressed by the following equation.

DO _N = [D _N-1 * Q _N + D _N * (QQ _N )] / Q

Accordingly, the interpolation value DO _N for the N th data D _N is output through the output terminal DO and output in response to the system clock signal f2 in the register 650 (step 850). Through the above-described process, it is possible to implement a real-time data frequency conversion apparatus that does not use a memory, and to prevent a setup or hold timing violation occurring during the frequency conversion.

According to the present invention, since the memory is not used as in the conventional method, not only is it possible to frequency-transform and output all data including video or audio data in real time, but also a timing violation occurring at the time of data latching by using the DTO. It has the effect of eliminating (VIOLATION). In addition, the present invention can be easily applied not only to a specific field such as an image processing field, but also to a communication field using an audio signal or other unspecified field, and to reduce the size of a circuit because no memory is used.

Claims (10)

A discrete time oscillator for sequentially adding a period of the system clock signal to generate a sequential clock control value corresponding to the period of the sub clock signal; Comparison means for comparing the clock control value with a first reference value and a second reference value and outputting the compared result as a control signal of a first level or a second level; A first register configured to output data input in response to the sub clock signal; A multiplexer for selectively outputting the input data or previous data output through the output terminal in response to the control signal; And And a second register configured to output an output of the multiplexer in response to the system clock signal. The method of claim 1, wherein the discrete time oscillator, A first adder configured to generate a clock control value by adding a period of the system clock signal and a modulo value of the clock control value; And And a third register configured to input the clock control value and output a modulo value of the clock control value to the first adder in response to the sub clock signal. A first register configured to externally input the N + 2th data and output the input data as the N + 1th data in response to a sub clock signal; A second register inputting the N + 1th data and outputting the N + 1th data as an Nth data in response to a system clock signal; A third register configured to output the N-th data as N-th data in response to the system clock signal; A discrete time oscillator for sequentially adding a period of the system clock signal to generate a sequential clock control value corresponding to the period of the sub clock signal; Comparison means for comparing the clock control value with a first reference value and a second reference value, and outputting the compared result as a high or low level control signal; The N + 1 th data, the N th data, and the N th -th data are input, and in response to the control signal, an interpolation value of the N th data, or the N + 1 th data and the N th -1 th data. Interpolation means for selectively outputting an interpolation value of a sum of data divided by two; And And a fourth register for outputting the output of the interpolation means in response to the system clock signal. The method of claim 3, wherein the interpolation unit, A second adder for adding the N + 1th data and the N-1th data; A first divider dividing the output of the second adder by two; A second multiplexer for selectively outputting Nth data or data obtained by dividing the sum of the N + 1th data and the N−1th data by 2 in response to the control signal; A fifth register configured to output an output of the multiplexer in response to the system clock signal; A first multiplier that multiplies the output of the multiplexer by a difference between the period of the sub clock signal and the clock control value; A second multiplier that multiplies the output of the fourth register by the clock control value; A second adder for adding outputs of the first multiplier and the second multiplier; And And a second divider for dividing an output of the second adder by a period of the sub-clock signal, and outputting the divided signal as an interpolation value. The method of claim 1 or 3, wherein the comparing means sets the applied first reference value as an allowable value of the data hold time, and the first reference value is a difference between the allowable value of the period of the sub clock signal and the hold violation time. Characteristic data frequency converter. 4. The method of claim 1 or 3, wherein the comparing means sets the applied second reference value as an allowable value of a data setup time, wherein the second reference value is a difference between a period of the sub-clock signal and a tolerance of a setup violation time. Characteristic data frequency converter. A data frequency conversion method of converting a frequency of the data by inputting predetermined data output in response to a sub clock signal as current data and outputting the current data in response to a system clock signal. (a) generating a clock control value for generating a sub clock while sequentially adding periods of a system clock signal; Determining whether the clock control value exists between a first reference value and a second reference value; If the clock control value exists between the first reference value and the second reference value, determining that a timing violation has occurred and generating a control signal having a first logic level; (b) selecting previous data fed back in response to the control signal having the first logic level; If the clock control value does not exist between the first reference value and the second reference value, determining that the timing violation has not occurred and generating a control signal having a second logic level; (c) selecting currently applied data in response to the control signal having the second logic level; And And outputting the data selected in the step (b) or step (c) in response to the system clock signal. The method of claim 7, wherein the step (a), Generating the clock control value by adding a period of the system clock signal and a previous value of the clock control value; Determining whether the clock control value has exceeded a period of the sub clock signal; Outputting the generated clock control value if the clock control value does not exceed a period of the sub clock signal; And If the clock control value exceeds the period of the sub clock signal, adding the remainder of the division of the clock control value by the period of the sub clock signal and the period of the system clock signal to generate the clock control value; Data frequency conversion method, characterized in that. Generating a clock control value for generating a sub clock while sequentially adding periods of a system clock signal; Determining whether the clock control value exists between a first reference value and a second reference value; If the clock control value exists between a first reference value and a second reference value, determining that a timing violation has occurred and generating a control signal having a first logic level; (a) selecting half of a value obtained by adding N + 1th data and N−1th data of the applied data in response to the control signal having the first level; If the clock control value does not exist between the first reference value and the second reference value, determining that a timing violation has not occurred and generating a control signal having a second logic level; (b) selecting the Nth applied data in response to the control signal having the second logic level; (c) performing interpolation using the data selected in step (a) or (b), the period of the sub-clock signal, and the clock control value; And And outputting the interpolated data in response to the system clock signal. The method of claim 9, wherein step (c) comprises: (d) multiplying the difference between the period of the sub clock signal and the clock control value by the selected data; (e) multiplying one clock delayed data of the selected data by the clock control value; And And dividing each data generated in the step (d) and the step (e) into a period of the sub-clock signal, and outputting the divided data as interpolation data.