KR19990073344A - Converter of Partial Resonant Type Realized Zero Voltage Switching Of Main Switch and Supplementary Switch - Google Patents

Abstract

The present invention relates to a partially resonant converter that enables zero voltage switching.

In the partial resonant converter implementing zero voltage switching of the main switch and the auxiliary switch of the present invention, a transformer in which the primary side and the secondary side are insulated, and the pulse width modulation for generating a square wave pulse whose duty ratio varies according to the secondary voltage variation of the transformer A control unit, a juice switching element for supplying a DC input voltage to the primary side of the transformer by zero voltage switching using charge / discharge of the capacitor, a first control circuit unit for controlling the juice switching element in response to a square wave pulse, and a preset Alternating with the juice switching element by dead band, supplying DC input voltage to the primary side of transformer by zero voltage switching using charge / discharge of capacitor and clamping spike voltage by reverse electromotive force applied to primary side of transformer An auxiliary switching element and a second control circuit portion for controlling the auxiliary switching element in response to the square wave pulse The.

By such a configuration, the partial resonant converter according to the present invention not only enables zero voltage switching by charge / discharge of a capacitor in a switching period, but also achieves high efficiency and miniaturization by realizing low loss.

Description

Partial Resonant Type Realized Zero Voltage Switching Of Main Switch and Supplementary Switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to switching power supplies, and more particularly, to a partially resonant converter capable of zero voltage switching (hereinafter referred to as "ZVS").

Square wave converter of general pulse width modulation (hereinafter referred to as "PWM") method has a switching loss increases in proportion to the oscillation frequency, there is a limit to increase the frequency due to the heat generated by the switching loss. In addition, the square wave converter includes a large amount of noise in the output signal by the leakage inductance of the transformer and the inductance component of the pattern due to the high frequency signal during switching, and the conduction noise and the radiation noise affecting the human body and the peripherals are increased.

The problem of this square wave converter is as follows. First, since heat generation is generated by switching loss as described above, in order to minimize such heat generation, the rating of the switching element is used by raising the rating of about 2 to 3 times the actual required value, and dissipating a large amount of heat Large and heavy heat sinks are needed for this purpose. In addition, when the output capacity is large, since the heat dissipation effect by the heat sink is small, the additional cost for the direct current fan increases because the cooling must be performed using a direct current fan. In addition, the self-heating of the square wave converter adversely affects the peripheral components, thereby shortening the lifespan and leading to the occurrence of noise as a major cause of noise. In addition, the self-heating of the square wave converter not only increases the power consumption of the switching power supply, but also increases the volume of the switching power supply, thereby increasing the size and increasing the cost.

Due to these problems, it is difficult for the square wave converter to be high efficiency and high frequency. Recently, development of a resonant converter has been actively conducted as a solution to the problem of the square wave converter. Such a resonant converter can reduce switching loss and noise by changing the current or voltage waveform of the switching element into a sinusoidal waveform. FIG. 1 compares the voltage, current waveform and switching loss of a square wave converter and a resonant converter, and it can be seen that the loss of the resonant converter is smaller than that of the square wave converter due to the sinusoidal current waveform.

As can be seen from the above resonant converter, the switching loss is small, so that high frequency and miniaturization are possible, and the voltage or current waveform is a sine wave, which generates less noise. However, the resonant converter has a large voltage or current stress and on loss of the switching element, and the resonance condition is often not maintained by the input condition and the load condition. have. In addition, as a problem of the resonant converter, there is a disadvantage in that the shape of the transformer choke coil is limited at the lowest frequency at light load.

In order to solve the problems of the square wave converter and the resonant converter, there is a demand for a method capable of realizing ZVS using a resonance phenomenon only during a switching period.

Accordingly, an object of the present invention is a partial resonant converter that implements zero voltage switching of a main switch and an auxiliary switch to enable ZVS by using a resonance phenomenon only in a switching period.

1 is a waveform diagram showing voltage and current losses of a conventional square wave converter and a resonant converter.

2 is a circuit diagram illustrating a partially resonant converter implementing zero voltage switching of a main switch and an auxiliary switch according to an exemplary embodiment of the present invention.

FIG. 3 is a characteristic diagram illustrating a discharge voltage of a capacitor during switching of the eighth transistor shown in FIG. 2.

4 is a characteristic diagram illustrating a discharge voltage of a capacitor when switching of the seventh transistor illustrated in FIG. 2.

FIG. 5 is a waveform diagram illustrating driving voltages, primary currents, and voltages of a juice switching element and an auxiliary switching element in the partial resonant converter implementing zero voltage switching of the main switch and the auxiliary switch shown in FIG. 2; FIG.

FIG. 6 is a locus waveform diagram showing a total loss amount of a partially resonant converter in which zero voltage switching of a main switch and an auxiliary switch shown in FIG. 2 is implemented.

<Description of Symbols for Main Parts of Drawings>

2: voltage detector 4: PWM controller

6: load

In order to achieve the above object, the partial resonant converter implementing zero voltage switching of the main switch and the auxiliary switch of the present invention is a transformer insulated from the primary side and the secondary side, and a square wave whose duty ratio varies according to the secondary side voltage variation of the transformer. A pulse width modulation control unit for generating a pulse, a juice switching element for supplying a DC input voltage to the primary side of the transformer by zero voltage switching using charge / discharge of a capacitor, and a control unit for controlling the juice switching element in response to a square wave pulse. 1 The control circuit unit and the pre-set deadband are alternately operated with the juice switching element to supply DC input voltage to the primary side of the transformer by zero voltage switching using charging / discharging of the capacitor, and the counter electromotive force applied to the primary side of the transformer. The auxiliary switching element for clamping the spike voltage by means of the second switching element and the auxiliary switching element in response to the square wave pulse And a second control circuit for group.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 6.

2, a transformer T for insulating the primary side 1A and the secondary side 2A, and a switching element for supplying a DC input voltage Vin to the primary side 1A of the transformer T. 7th and 8th transistors Q7 and Q8, 1st, 2nd and 3rd transistors Q1, Q2 and Q3 for controlling the 8th transistor Q8 and 7th transistor Q7 for controlling The third, fourth, and fifth transistors in response to the output signals of the fourth, fifth, and sixth transistors Q4, Q5, and Q6, the voltage detector 2 for detecting the output voltage, and the voltage detector 2; And a PWM controller 4 for controlling the sixth transistors Q3, Q4, Q5, Q6. Npn junction transistors are used as the first and fifth transistors Q1 and Q5, and pnp junction transistors are used as the second and sixth transistors Q2 and Q6. An n-channel MOS FET is used for the third, fourth, seventh, and eighth transistors Q3, Q4, Q7, and Q8.

The primary side 1A of the transformer T is connected in parallel with the first capacitor C1, the eighth transistor Q8, and the second capacitor C2, which are active clamp circuits. DC input voltage Vin is supplied directly. The eighth transistor Q8 serves as an auxiliary switch with respect to the seventh transistor Q7 which is the main switch, and the first capacitor C1, which is the clamp capacitor, continues to operate even during the off time of the clamp capacitor. Absorbs parasitic energy that wanders through all cycles while minimizing losses and minimizes ripple voltage. The seventh transistor Q7 and the third capacitor C3 serving as the main switch are common to the source terminal of the eighth transistor Q8 and the primary side 1A of the transformer T via the first node n1. The DC input voltage Vin is supplied to the primary side 1A of the transformer T according to the operating state of the seventh transistor Q7. The voltage supplied to the primary side 1A of the transformer T is transferred to the secondary sides 2A and 2B, and then rectified by the diodes D1 and D2, the inductor L _R and the capacitor C _R. It is smoothed and supplied to the load 6 by DC voltage.

The voltage detector 2 is connected to the output nodes nout1 and nout2 to detect an output voltage fluctuation state on the output nodes nout1 and nout2 to supply the PWM control circuit 4. The PWM controller 4 generates a control signal in the form of a square wave by pulse-width modulating the output voltage variation detected from the voltage detector 2 at a preset ratio. The square wave control signal generated from the PWM controller 4 drives the seventh and eighth transistors Q7 and Q8 to maintain the output voltage constant. In addition, the PWM controller 4 detects an overvoltage on the tenth node n10 and controls a control signal in the form of a square wave according to the overvoltage. In detail, the square wave control signal generated from the PWM controller 4 is divided by the third, fourth, and fifth resistors R3, R4, and R5 connected in series to form a gate of the third transistor Q3. Supply to terminals and source terminals. The drain terminal of the third transistor Q3 has a DC input voltage Vin through the first resistor R1, the fifth diode D5, the second node n2, and the second resistor R2. Supplied. On the other hand, the fourth capacitor C4 connected in parallel to the DC input voltage Vin is used for power supply noise removal, and the fifth diode D5 serves to block reverse voltage and current. The fifth and sixth capacitors C5 and C6 connected in parallel between the first node n1 and the second node n2 remove noise components on the second node n2, and are controlled by the charge / discharge characteristics. 8 Turn-on / turn-off time of transistor Q8 is controlled. The third transistor Q3 is turned on / off by the divided voltages of the third and fourth resistors R3 and R4 connected to its gate terminal, thereby turning on the third node n3. The voltage is varied to control the first and second transistors Q1 and Q2. The first and second transistors Q1 and Q2 have base terminals commonly connected to the third node n3, and one of them is turned on by the voltage on the third node n3. The first transistor Q1 is turned on when the voltage on the third node n3 is equal to or higher than its threshold voltage Vth, and the second transistor Q2 is turned on when the voltage on the third node n3 is its own. It is turned on when the potential is below the threshold voltage Vth. When the first transistor Q1 is turned on, the voltage on the second node n2 is supplied to the twelfth resistor R12 to turn on the eighth transistor Q8, and the second transistor Q2 is turned on. When turned on, the voltage on the fourth node n4 is supplied toward the first node n1.

In addition, the square wave control signal generated from the PWM controller 4 is supplied to the gate terminal of the fourth transistor Q4 via the fifth node n5 and the seventh capacitor C7 and the thirteenth resistor R13. ) Is supplied to the drain terminal of the fourth transistor Q4. The seventh capacitor C7 is partially charged with the voltage on the fifth node n5 when the voltage on the fifth node n5 is high potential, while the partially charged is charged when the voltage on the fifth node n5 is low potential. The voltage and the charge charged in the base of the fifth transistor Q5 are charged in the seventh capacitor C7 through the sixth diode D6, and the charge is supplied to the gate terminal of the fourth transistor Q4. The fourth transistor Q4 is turned on during the discharge of the seventh capacitor 7 to discharge the voltage on the seventh node n7 toward the sixth node n6. Accordingly, the third and fourth transistors Q3 and Q4 are alternately turned on according to the level of the square wave pulse generated from the PWM control circuit 4. Meanwhile, the sixth diode D6 connected in parallel with the thirteenth resistor R13 between the fifth node n5 and the seventh node n7 serves to speed up the turn-off time of the fifth transistor Q5. Done. The fifth and sixth transistors Q5 and Q6 have base terminals commonly connected to the seventh node n7, and one of them is turned on by the voltage on the seventh node n7. The fifth transistor Q5 is turned on when the voltage on the seventh node n7 is equal to or higher than its threshold voltage Vth, and the sixth transistor Q6 has its own voltage on the seventh node n7. It is turned on when the potential is below the threshold voltage Vth. When the fifth transistor Q5 is turned on, the voltage on the ninth node n9 is supplied to the sixth resistor R6 to turn on the seventh transistor Q7, and the sixth transistor Q6 is turned on. When turned on, the driving charge accumulated in the gate of the seventh transistor Q7 is supplied toward the sixth node n6 via the seventh resistor R7 to turn off the seventh transistor Q7.

The gate terminal of the seventh transistor Q7 is connected to the sixth and seventh resistors R6 and R7 and the second zener diode ZD2 via an eighth node n8, and is connected between the source terminal and the gate terminal. The four diodes D4 and the third capacitor C3 are connected in parallel. The fourth diode D4 is an internal diode of the seventh transistor Q7. The seventh transistor Q7 is turned on when the voltage on the eighth node n8 is equal to or greater than its own moonturn voltage Vth. The third capacitor C3 charges the voltage on the first node n1 when the seventh transistor Q7 is turned off, that is, when the voltage on the first node n1 is high potential, while the seventh transistor C3 is charged. When Q7 is turned on, that is, when the voltage on the first node n1 is at a low potential, the charged voltage is discharged. At this time, the seventh transistor Q7 is switched to ZVS by charging / discharging of the third capacitor C3. The gate terminal of the eighth transistor Q8 is connected to the twelfth resistor R12 and the first zener diode ZD1, and the third diode D3 and the second capacitor C2 are paralleled between the source terminal and the gate terminal. Is connected to. The eighth transistor Q8 is turned on when the voltage supplied via the twelfth resistor R12 is equal to or higher than its own turn-on voltage Vth. The second capacitor C2 charges the voltage discharged from the first capacitor C1 when the eighth transistor Q8 is turned off, while the second capacitor C2 discharges the charged voltage when the eighth transistor Q8 is turned on. Done. Accordingly, the switching capacitance of the first capacitor C1, which is the clamp capacitor, the output capacitance Coss of the FET, and the leakage inductance of the second capacitor C2, which is the synthetic capacitance, and the transformer T, are switched by the eighth transistor Q8. Resonance occurs due to (L _L ) and magnetizing inductance. At this time, the eighth transistor Q8 is switched to ZVS by charging / discharging of the second capacitor C2. ZVS switching is performed when the charge voltage of the second and third capacitors C2 and C3 is discharged to a negative potential and the discharge voltage is clamped to the built-in diodes of the seventh and eighth transistors Q7 and Q8. The seventh and eighth transistors Q7 and Q8 are implemented by turning on.

The first and second zener diodes ZD1 and ZD2 connected to the gate terminals of the seventh and eighth transistors Q7 and Q8 have a constant voltage supplied to the gate terminals of the seventh and eighth transistors Q7 and Q8. In addition, the seventh and eighth transistors Q7 and Q8 are protected from overvoltage. The resistors R8, R9, R10, and R11 connected in parallel between the sixth and tenth nodes n6 and n10 match impedance between the DC input voltage Vin and the ground voltage source GND of the PWM controller 4. In addition, the seventh and eighth transistors Q7 and Q8 are protected from overcurrent.

Since the seventh and eighth transistors Q7 and Q8 are alternately turned on by the dead band in which the third and fourth transistors Q3 and Q4 are already designed, the fourth node n4 and the fourth transistor are respectively turned on. It is turned on in response to the voltage on the eight node n8. These seventh and eighth transistors Q7 and Q8 are driven as described above so that the voltage supplied to the primary side 1A of the transformer T is transferred to the secondary side 2A, 2B. The voltage delivered to the secondary sides 2A and 2B is first rectified by the first and second diodes D1 and D2 connected in the form of a center tap, and then the inductor L _R and the capacitor C _In the smoothing circuit consisting of _R ) is rectified second and supplied to the load (6).

As a result, the square wave pulse generated from the PWM controller 4 according to the voltage variation on the output nodes nout1 and nout2 turns on / off the seventh and eighth transistors Q7 and Q8 alternately. And a capacitor is charged / discharged according to the turn-on / off of the eighth transistors Q7 and Q8 to obtain ZVS, and the first capacitor C1 which is a clamp capacitor, the leakage inductance L _L of the transformer T, and The resonance can be realized by the magnetizing inductance. Here, a constant dead band exists when ZVS switching of the seventh and eighth transistors Q7 and Q8 is performed.

The operation of the partial resonant converter according to the present invention will be described as follows.

<Mode 1>

In the on period of the seventh transistor Q7, the current ID1 flows to the secondary side 2A through the transformer T and the first diode D1. At this time, the current ID2 flowing through the second diode D2 is not blocked by the second diode D2. The excitation current change amount ΔIm1 of the transformer T at this time is represented by Equation 1 below.

ΔIm1 = (nVout / L _Prime ) DT

Here, D = Ton / (Ton + Toff), L _Prime means primary inductance, n is the turns ratio, and Vout is the output voltage. DT represents the ratio of the on / off time of the seventh transistor Q7 to the period T.

The change amount ΔID1 of the secondary side current is expressed by Equation (2).

Where the primary current I _Pri = Io / n

A voltage of VC1 + Vin is applied to both ends of the second capacitor C2.

<Mode 2>

As the current flows to the primary side of the transformer T from the time when the seventh transistor Q7 is turned off, the third capacitor C3 is charged until it becomes equal to the DC input voltage Vin. At this time, the second capacitor C2 is discharged until it becomes equal to the voltage Vc1 charged in the first capacitor C1.

<Mode 3>

The secondary diodes D1 and D2 are simultaneously conducted. Apparently, only the leakage inductance L _L of the transformer T serves as an inductance while the first and second diodes D1 and D2 are short-circuited. Will be The resonance frequency fc at this time is as shown in equation (3).

Here, when C2 and C3 are the capacitances of the second and third capacitors C2, respectively, C = C2 + C3.

The resonance energy E _Res required for ZVS is expressed by Equation 4.

Here, I _Prime represents a current applied to the primary side of the transformer, and Vc1 represents a voltage charged in the first capacitor C1.

By this resonance energy, the conditional expression of ZVS at the time of turn-on of the eighth transistor Q8 is expressed by Equation (5).

The voltage Vds between the drain terminal and the source terminal of the second capacitor C2 or the eighth transistor Q8 at this time is shown in FIG. 3. In FIG. 3, when the voltage of the second capacitor C2 is discharged to the negative polarity (-) and clamped to the internal diode D3 of the eighth transistor, the eighth transistor Q8 is turned on to ZVS. It is switched and operates as a low loss snubber circuit.

<Mode 4>

With the secondary diodes D1 and D2 conducting at the same time, the current ID1 flowing through the first diode D1 is reduced while the current flowing through the second diode D2 ( Since ID2 is raised, the current ID2 flowing through the second diode D2 is equal to the output current Io.

<Mode 5>

Mode 5 is a mode corresponding to mode 1. During the period in which the eighth transistor Q8 is kept in the on state, the excitation energy of the transformer T1 is reset, and the energy of the counter electromotive force is supplied to the secondary sides 2A and 2B. If the mode 2 to mode 4 period and the mode 6 to mode 7 period are approximated to a sufficiently short side with period T, the period of mode 5 is (1-D) T. Where D is Ton / (Toff + Ton). The amount of excitation current change ΔIm1 'of the transformer T1 during this period is expressed by Equation (6).

ΔIm1 '= {(VC1-nVout) / LP} (1-D) T

The reset condition of the transformer T is ΔIm1 = ΔIm1 ', and Vout = VinD / n and Vc1 = VinD / (1-D).

<Mode 6>

When the eighth transistor Q8 is turned off, since the primary current I _Prime continues to flow, the third capacitor C3 is discharged until it is equal to the DC input voltage Vin, and the second capacitor C2 is discharged. It is charged to the voltage VC1 charged in one capacitor C1.

<Mode 7>

As in mode 3, the secondary side diodes D1 and D2 are simultaneously in a conductive state, and since the secondary side tap is short-circuited, only the leakage inductance L _L of the transformer T operates as an inductance. The resonance operation occurs. The conditional expression of ZVS at this time is as shown in Equation (7).

The voltage of the third capacitor C3 at this time is as shown in FIG. 4. In FIG. 4, when the voltage of the third capacitor C3 is discharged to the negative polarity (−) and clamped to the internal internal diode of the seventh transistor Q7, when the seventh transistor Q7 is turned on, ZVS is turned on. And the switching loss is zero ("0").

<Mode 8>

The current ID2 of the second diode D2 decreases while the secondary side 2A and 2B diodes D1 and D2 are simultaneously conducted, while the current ID1 of the first diode D1 is the output current. It is a period until it is equal to (Io).

As described above, since switching is performed in the resonant operation by ZVS in the mode 3 and the mode 7 during the period T of the square wave pulse signal generated from the PWM controller 4, there is almost no switching loss.

The characteristics of the partial resonant converter according to the present invention, the conventional square wave converter and the resonant converter are shown in Table 1 below.

efficiency Switching stress frequency Parts score Square wave converter usually Bad fixing many Resonant Converter Recession Resonance ZVS Good Quantity (current stress) variable usually Voltage resonance ZVS Good Quantity (current stress) variable usually Partial resonance ZVS Good Good fixing usually

5 is a waveform illustrating a primary current I _Prime , a voltage Vds, and a gate driving voltage of a partially resonant converter implementing zero voltage switching of a main switch and an auxiliary switch.

Meanwhile, as shown in FIG. 6, a loss characteristic diagram of a partial resonant converter implementing zero voltage switching between a main switch and an auxiliary switch has either a peak current (Id) or a drain voltage (Vds). ), The other is zero, so the total loss is zero.

As described above, the partial resonant converter according to the present invention has a capacitor in the switching period by connecting a capacitor in parallel to each of the two switching elements and a circuit for achieving resonance operation and a low loss snubber on the primary side of the transformer. ZVS switching is possible by charging / discharging. Accordingly, the partial resonant converter according to the present invention can reduce the switching loss to reduce the amount of heat generated, thereby improving efficiency and miniaturization. In addition, the voltage variation between the drain and the source of the transistor used as the main switching element for the input voltage is reduced, and the low breakdown voltage switching element can be used on the secondary side of the transformer.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A transformer with insulated primary and secondary sides, A pulse width modulation controller configured to generate a square wave pulse having a duty ratio different according to the secondary voltage variation of the transformer; A juice switching element for supplying a DC input voltage to the primary side of the transformer by zero voltage switching using a charge / discharge of a capacitor; A first control circuit unit for controlling the juice switching element in response to the square wave pulse; Alternating with the juice switching element by a dead band preset, the DC input voltage is supplied to the primary side of the transformer by zero voltage switching using charge / discharge of a capacitor and is applied to the counter electromotive force applied to the primary side of the transformer. An auxiliary switching element for clamping a spike voltage by And a second control circuit unit for controlling the auxiliary switching element in response to the square wave pulse. The method of claim 1, The first control circuit unit includes a first switching device connected between the juice switching device and the pulse width modulation control unit to drive the juice switching device at a voltage charged by charging the square wave pulse. And the second control circuit part further comprises a second switching element connected between the auxiliary switching element and the pulse width modulation control part to drive the auxiliary switching element in response to the square wave pulse. The method of claim 2, The juice switching device includes a first transistor including a drain and source electrode connected between a primary side of the transformer and a base voltage source, and a gate electrode connected to an output terminal of the first switching device, and in parallel with the drain and source electrode. A first capacitor and a connection between the primary side of the transformer and the drain terminal, The auxiliary switching element includes a second transistor including a drain and a source electrode connected to both ends of the primary side of the transformer, and a gate electrode connected to an output terminal of the second switching element, and in parallel with the drain and the source electrode of the second transistor. And a clamp capacitor connected between the connected capacitor and the DC input voltage source and the drain electrode of the second transistor. The method of claim 3, wherein A first diode connected in parallel with the first capacitor to clamp the discharge voltage at a predetermined negative polarity level when the charging voltage of the first capacitor is discharged to a negative polarity potential; And a second diode further connected in parallel with the second capacitor and configured to clamp the discharge voltage at a predetermined negative polarity level when the charging voltage of the second capacitor is discharged to a negative polarity potential. Converter.