KR19990069610A - Self-burning test circuit of semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-burn-in test circuit of a semiconductor memory. In the conventional self-burn-in test circuit of a semiconductor memory, an integration degree is generated by generating an address for testing a semiconductor memory using a counter corresponding to the number of columns and rows of a memory cell unit. There was a declining issue. In view of the above problems, the present invention provides an address counter having a plurality of counters that generate an address by dividing the pulse generation and output pulses of the controller; A counter which receives, divides and outputs an output signal of a counter for generating the highest address among the addresses of the address counter; A combination circuit unit for controlling an increase / decrease of an address by combining each address of the address counter unit and an output signal of the counter; An output unit for latching and inverting an output of the combination circuit unit and outputting the latched unit; It consists of a sense amplifier controller that always drives the sense amplifier during burn-in test operation, enabling columns and rows using the same address signal during self-burn test operation, and equalizing once enabled bit lines during self-burn test operation. In this case, the semiconductor memory can be tested and the number of counters can be reduced to improve the integration of the semiconductor memory.

Description

Self-burning test circuit of semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-burn-in test circuit of a semiconductor memory, and more particularly to a semiconductor memory that is suitable for improving the integration density by testing a semiconductor memory by using a counter of the same number as the number of columns or row addresses of the semiconductor memory. It relates to a self burn-in test circuit.

In general, the self-burn test of a semiconductor memory means that when a user inputs a specific signal called a self-burn-in test signal from the outside, the semiconductor memory itself stores data in each cell and outputs it again without inputting other signals necessary for operating the memory. By performing the operation, the user can easily determine whether an error occurs in each cell included in the semiconductor memory without using a special device.

In order to enable such a self-burn test, a semiconductor memory generally includes a burn-in test detector for detecting a burn-in test signal, a pulse generator and a pulse controller for generating a constant pulse and adjusting the pulse, an address counter for generating an address, A self-burn-in test circuit including a data generator for generating data to be stored in a memory cell corresponding to an address generated by the address counter is provided. The self-burn-in test circuit of a conventional semiconductor memory having such a function will be described with reference to the accompanying drawings. It will be described in detail as follows.

FIG. 1 is a block diagram of a general semiconductor memory. As shown in FIG. 1, an input of a test mode signal TM is detected to generate a pulse, the pulse is normalized, and the standardized pulse is counted to determine an address. A self-burn-in test circuit for generating data to be stored in a memory cell of the memory cell unit 1 corresponding to the address; A column control signal generator (2) for receiving a clock signal and an address signal from the self-burn-in test circuit to generate a control signal for controlling the column side of the memory cell unit (1); An address buffer unit 3 for buffering and outputting an address signal of the self-burn-in test circuit; A column address signal and a row address signal are respectively received from the address buffer unit 3 and decoded to enable the column decoder 4 and the row decoder 5 to enable word lines and bit lines of the memory cell unit 1. It is composed.

The self-burn-in test circuit of the semiconductor memory includes a burn-in detector 11 for detecting a test mode signal TM; A pulse generator 12 for generating a pulse according to the output signal of the burn-in detector 12; A pulse controller 13 for normalizing the pulses of the pulse generator 12; An address counter unit 14 for counting pulse signals normalized through the pulse control unit 13 using a plurality of counters to generate all addresses of the memory cell unit 1; And a data generator 15 for generating data to be stored in the memory cell unit 1.

FIG. 2 is an internal configuration diagram of the address counter unit 14. As shown in FIG. 2, a column address counter unit for generating a plurality of column address signals by receiving and counting a pulse signal of the pulse controller 13 16); A row address counter unit 17 for receiving a count of the address signals of the column address counter unit 16 to generate a plurality of row address signals; A transmission unit (18) for transmitting and controlling the column address signal and the row address signal; And an output unit 19 which latches and inverts a column address signal or a row address signal transmitted through the transfer unit 18 and outputs the latched and inverted signals.

The column address counter unit 16 includes a counter CNTR1 that receives and counts the pulse signal, and counts as many counters CNTR2 as the number of columns of the memory cell unit 1 that receives and counts a counter output of a previous stage. CNTR9).

The row address counter 17 includes a counter CNTR10 for receiving and counting the output signal of the counter CNTR9 located at the last end of the column address counter 16 and inputting the counter output of the previous stage. It is composed of the counters CNTR11 to CNTR18 corresponding to the number of rows of the memory unit 1 that receive and count.

The transmission unit 18 transfers and controls the outputs of the counters CNTR1 to CNTR9 of the column address counter unit 16 according to the control signals CN and CN of the pulse controller 13. A column address transmitter 20 comprised of TG1 to TG9; When the output signal of the column address counter unit 16 is not output through the column address transfer unit 20, a plurality of transmission signals of the counters CNTR10 to CNTR18 of the row address counter unit 17 are transmitted. It consists of a row address transmitter 21 composed of transfer gates TG10 to TG18.

The output unit 19 is a row address counter unit at a position corresponding to the output signals of the counters CNTR1 to CNTR9 of the column address counter unit 16 and the counters CNTR1 to CNTR9 of the column address counter unit 16. A plurality of latches LATCH1 to LATCH9 for receiving and latching the output signals of the counters CNTR10 to CNTR18 of (17) as common inputs, respectively; Inverters INV1 to INV9 output the inverted output signals of the plurality of latches LATCH1 to LATCH9, respectively.

The operation of the self-burn-in test circuit of the conventional semiconductor memory configured as described above will be described below.

First, in the burn-in test operation of the semiconductor memory, external column / row address strobes CAS and RAS and write / read enable signals WE and OE are blocked.

At this time, when the test mode signal TM is input, the burn-in detection unit 11 which detects this outputs a detection signal, and the pulse generator 12 receiving the test mode continuously outputs a predetermined pulse PULSE.

Then, the pulse controller 13 shapes the pulse signal generated from the pulse generator 12 in accordance with the standard, which is input to the address counter 14.

The counter CNTR1 included in the column address counter 16 of the address counter 14 receiving the pulse signal receives the pulse in synchronization with the rising edge of the input pulse signal as shown in FIG. A pulse signal divided by two is output, and the counter CNTR2 outputs a pulse signal divided by two in the same manner as the output signal of the counter CNTR1. In this manner, the counter CNTR9 is performed.

Next, the output signals of all the counters CNTR18 of the row address counter unit 17 are processed through the same process of dividing the output signal of the counter CNTR10 from the counter CNTR11 to divide the output pulse of the counter CNTR9 again. Is determined.

In this process, all the output signals of the counters CNTR1 to CNTR9 are output at high potential in the first section t1, and the addresses output through the transfer gates TG1 to TG9 of the column address transmitter 20 are '111111111'. 'Is output through the latches LATCH1 to LATCH9, and the column address signal inverted through the inverters INV1 to INV9 is output as' 000000000'.

At this time, all of the transfer gates TG10 to TG18 of the row address transmitter 21 are turned off to block transmission of the counters CNTR10 to CNTR18.

Next, in the second section t2, only the output of the counter CNTR1 transitions to low potential and is output. Accordingly, the column address output through the output unit 19 is output as '000000001', and the third In the section t3, since the output signal of the counter CNTR1 transitions to the high potential again, and the output signal of the counter CNTR2 transitions to the low potential and is output, the output column address is output as '000000010'. By repeating the above process, the column addresses are all enabled from '000000000' to '111111111'. After this process is completed, the transfer gates TG1 to TG9 are turned off and the transfer gates TG10 to TG18 are turned off. Turn on to output the row address.

At this time, the output row address is also enabled for the row address from the lowest address to the highest address in the same manner as the output operation of the column address.

As described above, the column address and the row address are input to the column decoder 4 and the row decoder 6 and decoded by the address buffer unit 3 which receives and buffers the column addresses and the row addresses sequentially input. Enable columns and rows in (1).

In this case, the data generator 15 generates predetermined data and outputs the data to the column control signal generator 2, and the column control signal generator 2 outputs the data to the enabled memory cell unit 1. Data is stored in a specific memory cell.

After the data is stored as described above, the specific columns and rows of the memory cell unit 1 are enabled by the operations of the counters CNTR1 to CNTR18 to output the stored specific data to the outside. Through this process, abnormality of the memory cell is detected, and a feature of the related art is that each column address and row address are converted to an operation of a sense amplifier (not shown) for amplifying data input / output to the memory cell unit. At this point in time, all bit lines of the memory cell unit 1 were equalized.

As described above, the self-burn-in test circuit of the conventional semiconductor memory generates an address for testing the semiconductor memory using a counter corresponding to the number of columns and rows of the memory cell unit, thereby reducing the degree of integration.

It is an object of the present invention to provide a self-burn-in test circuit of a semiconductor memory capable of testing all memory cells using a counter corresponding to a large number of columns or rows of a memory cell unit.

1 is a block diagram of a general semiconductor memory.

Fig. 2 is a detailed configuration diagram of an address counter section in a self-burn-in test circuit of a conventional semiconductor memory.

Fig. 3 is a waveform diagram of an address which is an output of each counter in Fig. 2;

4 is a detailed configuration diagram of an address counter in the self-burn-in test circuit of the semiconductor memory of the present invention.

*** Description of the symbols for the main parts of the drawings ***

1: Memory cell unit 2: Column control signal generator

3: Address buffer section 4: Column decoder

5: low decoder 11: burn-in detection unit

12: pulse generating unit 13: pulse control unit

14: address counter 15: data generator

16: Counter unit 19: Output unit

22: combination circuit unit 23: sense amplifier control unit

The above object is a burn-in detector for detecting a test mode signal; A pulse generation and control unit for generating and normalizing a pulse signal according to an output signal of the burn-in detection unit; In the self-burn-in test circuit of a semiconductor memory including an address generator for generating an address signal by counting the pulse generation and the output pulse of the control unit, the address generator is provided with a plurality of counters to generate the pulse generation and output pulses of the control unit. An address counter unit for dividing to generate an address; A counter which receives, divides and outputs an output signal of a counter that generates the highest address among the addresses of the address counter; A combination circuit unit for controlling an increase / decrease of an address by combining each address of the address counter unit and an output signal of the counter; An output unit for latching and inverting an output of the combination circuit unit and outputting the latched unit; It consists of a sense amplifier controller that always drives the sense amplifier during the self burn-in test operation, enabling columns and rows using the same address signal during the self burn-in test operation, and equalizing the once enabled bit line during the self burn-in test operation. It will be achieved by not doing so, when the present invention will be described in detail with reference to the accompanying drawings as follows.

FIG. 4 is a circuit diagram of the address counter section 14 in the self-burn-in test circuit of the semiconductor memory of the present invention. As shown in FIG. 4, other configurations are the same as those shown in FIG. A plurality of counters (CNTR2 to CNTR9) corresponding to a large number of columns or rows of a semiconductor memory, including a counter (CNTR1) for receiving and counting a pulse signal of the pulse controller 13. A counter unit 16 for performing; A counter CNTR10 which receives an output signal of the counter CNTR9 of the counter unit 16 and counts the output signal; Combination circuit unit 22 composed of a plurality of exclusive ogates (XOR1 to XOR9) for outputting a combined or exclusive combination of each of the counter (CNTR1 to CNTR9) output signals of the counter unit (16) and the output signal of the counter (CNTR10). Wow; And an output unit 19 for latching and inverting the output signal of the combination circuit unit 22 and outputting the same, and further including a sense amplifier controller 23 for controlling the operation of the sense amplifier.

Hereinafter, the operation of the self-burn-in test circuit of the semiconductor memory of the present invention configured as described above will be described.

First, when the test mode signal TM is input, it is detected by the burn-in detector 11, and the pulse generator 12 generates a pulse signal according to the output signal of the burn-in detector 11.

Then, the pulse signal of the pulse generator 12 is normalized and output by the pulse controller 13, and the output signal of the pulse generator 12 is input to the counter CNTR1 and divided and outputted. The counter is divided in two by the counter CNTR2 of the next stage, which proceeds to the counter CNTR9 located at the last stage of the counter 16.

Then, the counter CNTR10 divides the output signal of the counter CNTR9 into two and outputs it.

As described above, since the counter CNTR10 is outputted after the cycle of the counters CNTR1 to CNTR9 has been performed once, the output signals of the counters CNTR1 to CNTR9 and the output signals of the counter CNTR10 are respectively output. The combination circuit unit 22 outputting the combination of the two or more exclusively combines the address, which is an output signal thereof, and then sequentially decreases when the output signal of the counter CNTR10 is inverted.

Next, the output signal of the combination circuit unit 22 is latched through the latches LATCH1 to LATCH9 of the output unit 19, and is inverted and output through the inverters INV1 to INV9.

As described above, when the address signal is output, the sense amplifier controller 23 operating by receiving an output signal of a predecoder (not shown) continues to drive the sense amplifier until the test of one memory cell unit 1 is completed. .

Then, the address buffer unit 3 receiving the address signal buffers the address signal and applies the same address to the column decoder 4 and the row decoder 5.

By the operation of the column decoder 4 and the row decoder 5 which receive the same address signal, decode and output the same, the memory cells of the memory cell unit 1 are diagonally extending from the memory cells located at the top left to the bottom right memory cells. The memory cells in the direction are sequentially enabled and store the data of the data generator 15.

At this time, when the address signal is in the increasing direction, data is loaded on the first bit line, and the first word line is driven to store data in the memory cell positioned at the upper left corner.

Then, when the address is increased and the next memory cell in the diagonal direction is enabled from the left top, the memory cell located below the left top memory cell is also enabled, since the sense amplifier is driven. Data is simultaneously stored in a memory cell positioned below the left uppermost memory cell and a memory cell positioned diagonally adjacent to the left uppermost memory cell.

When the address increases through this operation, memory cells located diagonally from the upper left memory cell to the lower right memory cell and the lower memory cells are enabled and predetermined data. Will be saved.

Subsequently, when the output signal of the counter CNTR10 transitions to a low potential and is input after the above process, the address is sequentially decreased. At this time, since all the sense amplifiers are in operation, high-potential data is applied to each bit line of the memory cell unit 1, and as a result, addresses are sequentially reduced and input to all memory cells of the memory cell unit 1. Data is stored.

Then, after the data is stored as described above, the stored data is read again to test the semiconductor memory.

As described above, the present invention includes a counter corresponding to the number of word lines or bit lines of a semiconductor memory, enabling memory cells in the memory cell portion to be diagonally using the same address signal during a self burn-in test operation, and self-burn-in. By not equalizing the once enabled bit line during the test operation, data is stored and output in all memory cells to perform a self-burn test, thereby reducing the number of counters in the configuration, thereby improving integration.

Claims (3)

A burn-in detector for detecting a test mode signal; A pulse generation and control unit for generating and normalizing a pulse signal according to an output signal of the burn-in detection unit; In the self-burn-in test circuit of a semiconductor memory including an address generator for generating an address signal by counting the pulse generation and the output pulse of the control unit, the address generator is provided with a plurality of counters to generate the pulse generation and output pulses of the control unit. An address counter unit for dividing to generate an address; A counter which receives, divides and outputs an output signal of a counter that generates the highest address among the addresses of the address counter; A combination circuit unit for controlling an increase / decrease of an address by combining each address of the address counter unit and an output signal of the counter; An output unit for latching and inverting an output of the combination circuit unit and outputting the latched unit; A self-burning test circuit of a semiconductor memory, characterized by comprising a sense amplifier control unit which always drives the sense amplifier during a burn-in test operation. The memory cell of claim 1, wherein the address counter unit comprises a lowest address counter that receives the pulse generation and the output pulses of the control unit and divides the output pulses into two divisions, and divides and outputs two output signals of the counter located at the front end. A self-burn-in test circuit for a semiconductor memory, characterized by comprising as many counters as there are negative word lines or bit lines. 2. The self-assembly of the semiconductor memory according to claim 1, wherein the combination circuit unit comprises a plurality of orifices for exclusively combining each of the output signals of the plurality of counters provided in the address counter unit and the output signals of the counters. Burn-in test circuit.