KR19990069564A - Plasma Ion Accelerator for Semiconductor Wafer Etching Process - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma ion acceleration device used in a semiconductor wafer etching process, wherein wafers 1 are plasma (P) ions present in the chamber 10 by using an electromagnetic force that is charged when an electric field and a magnetic field exist at the same time. In order to provide a plasma ion accelerator for accelerating to the side, the chamber 10 for the reaction of plasma P for accommodating the wafer 1 and the support of the wafer 1 in the chamber 10 are supported. A susceptor 11 for disposition, an electrode and a magnet 20 disposed on an inner circumferential surface of the chamber 10 to accelerate internal charge in a specific direction by the electromagnetic force, and a high density provided on the outside of the chamber 10. It is composed of a plasma generator 12, using the electromagnetic force according to the simultaneous formation of the electric field and the magnetic field, and the principle that the internal charge proceeds in the vector product direction of the magnetic field and the electric field By accelerating the plasma P ions present in the chamber 10 toward the wafer 1, unnecessary high frequency accelerators 120 can be removed, thereby miniaturizing the device, thereby reducing the required cost. Of course, since the acceleration voltage is not directly transmitted to the wafer 1, it is possible to prevent damage to the semiconductor device, and relates to a plasma ion accelerator for a semiconductor wafer etching process capable of achieving stability of the plasma (P). .

Description

Plasma Ion Accelerator for Semiconductor Wafer Etching Process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma ion acceleration device used in a semiconductor wafer etching process, and more particularly, to semiconductor wafer etching for accelerating plasma ions present in a chamber toward a wafer by using an electromagnetic force that is charged when an electric field and a magnetic field exist at the same time. It relates to a plasma ion accelerator for the process.

According to a wafer processing process of a general semiconductor, an oxide film is formed on a polished wafer surface in a quartz tube of a diffusion furnace controlled at a temperature of 900 ° C. to 1200 ° C., followed by photolithography. Apply liquid photoresist for Photo Engraving.

The plasma apparatus for performing the photolithography process as described above vaporizes the photoresist coated for the purpose of forming a selective etching pattern by using ionized high temperature plasma. It is a device that is removed by painting.

Here, plasma refers to an arc gas in which oxygen, nitrogen, or a mixture of these gases is ionized by high frequency energy such as microwave, and has conductivity and is affected by a magnetic field.

In the case of an etching apparatus using plasma, a system for separating plasma high frequency power (Radio Freuency) for plasma generation and acceleration of plasma ions into a separate device is developed to independently control the density and acceleration of the plasma. have. Such a device is called a De-Coupled Plasma Etcher, and when a high density plasma is required, the above-described separate plasma etching device having two high frequency powers is used.

In this case, the two high frequency powers use the main high frequency power for generating the plasma and the negative high frequency power for accelerating the plasma ions in the chamber by generating a bias voltage on the susceptor on which the wafer is placed. do.

That is, the conventional plasma wafer etching process for semiconductor wafers, as shown in FIG. 1, includes a chamber 10 for plasma P reaction for accommodating the wafer 1, and the chamber 10. A susceptor 11 for supporting the wafer 1, an electrode 124 formed on a contact surface of the wafer 1 of the susceptor 11, and the susceptor 11. A high frequency accelerator (RF biasing system) 120 constituting a circuit for high frequency acceleration, and a high density plasma generator 12 provided outside the chamber 10.

Here, the high density plasma generator 12 is a device corresponding to the main high frequency power, and the high frequency accelerator 120 is a device corresponding to the negative high frequency power.

In this case, the susceptor 11 to which the negative high frequency power for generating the ion acceleration voltage is supplied instead of the main high frequency power for generating the plasma P has the function of the electrode 124 as described above. Negative high-frequency power is made of a dielectric isulator (Dielectric Isulator), the high-frequency accelerator 120, the blocking capacitor (Blocking Capacitor) 121, the RF Matching Network (RF Matching Network) 122, and a high frequency It is connected to an RF generator 123 and the like to serve as another plasma generator.

In other words, when only the electrode 124 of the susceptor 11 is looked at, a small-scale plasma generator is formed by the electrode 124, and thus, as a whole, two kinds of plasma generators are formed in one chamber 10. Plasma P is generated. Of course, since the plasma P generated by the electrode 124 is for accelerating it, it appears very weak.

As described above, the conventional plasma etching apparatus has to be provided with a separate high-frequency accelerator 120 including the electrode 124 to accelerate the plasma (P) ions, so that the size of the system due to the space occupied In addition, a lot of incidental costs for operating the same, and because two plasma (P) is present in one chamber 10, there was a problem that the interference and perturbation phenomenon between the two plasma occurs.

In addition, since the plasma etching apparatus directly forms an acceleration voltage on the wafer 1, there is a concern that the semiconductor device may be damaged.

Accordingly, the present invention has been made to solve the above problems, by using the electromagnetic force according to the simultaneous formation of the electric field and magnetic field, by accelerating the plasma ions present in the chamber toward the wafer to realize miniaturization of the device, It is an object of the present invention to provide a plasma ion accelerator for a semiconductor wafer etching process that can reduce the required cost and stabilize the plasma.

1 is a schematic diagram of a plasma apparatus for a semiconductor wafer etching process according to the prior art,

2 is a schematic diagram of a plasma ion accelerator for a semiconductor wafer etching process according to the present invention;

3 is a cross-sectional view of a plasma ion accelerator for a semiconductor wafer etching process according to the present invention;

Figure 4 is a cross-sectional view showing the arrangement of the electrode and the magnet according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

P; Plasma 1; wafer

10; Chamber 11; Susceptor

12; High density plasma generator 20; Electrodes and magnets

120; High frequency accelerator 121; Blocking capacitor

122; High frequency matching network 123; High frequency generator

124; electrode

Plasma ion acceleration apparatus for semiconductor wafer etching process according to the present invention for achieving the above object, the chamber for the plasma reaction for accommodating the wafer, the susceptor for supporting the wafer in the chamber, and the chamber Is disposed on the inner circumferential surface of the electrode and a magnet for accelerating the internal charge in a specific direction by the electromagnetic force, characterized in that consisting of a high-density plasma generator provided on the outside of the chamber.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 to 4, the plasma ion accelerator for the semiconductor wafer etching process according to the present invention includes a chamber 10 for the plasma P reaction for accommodating the wafer 1, and the chamber 10 A susceptor (11) for supporting the wafer (1), an electrode and a magnet (20) disposed on the inner circumferential surface of the chamber (10) to accelerate internal charge in a specific direction by the electromagnetic force; It is composed of a high-density plasma generator 12 provided outside the chamber 10.

The electrode and the magnet 20 are disposed at a predetermined position in the chamber 10 where the plasma P is generated so that the crossing state of the electric field and the magnetic field may always proceed in a constant direction. That is, the electrode and the magnet 20 are continuously arranged along the inner circumferential surface of the chamber 10 in the order of N pole, + pole, S pole, and-pole as in the embodiment shown in FIGS. 3 and 4. It is desirable to allow magnetic and electric fields to cross each other.

At this time, the magnet is irrespective of which of the permanent magnets or electromagnets is selected and used.

Referring to the operation of the present invention by the configuration as described above are as follows.

In the present invention, in order to accelerate the plasma (P), the electromagnetic force is used instead of the conventional electrode accelerator, and when the electric field and the magnetic field exist at the same time, the vector product of the two forces (F = E × B) uses the principle of electromagnetic force to move the electric charge in the chamber 10 in the direction corresponding to the force. The direction of the vector product is directed toward the surface of the wafer 1.

Accordingly, the electrode and the magnet 20 are disposed in the chamber 10 generating the plasma P to introduce the electric field and the magnetic field. As the respective positions of the electrode and the magnet 20 are changed, Since the intensity and direction can be adjusted, the acceleration direction and intensity of the plasma P ions can be arbitrarily adjusted.

On the other hand, after three consecutive pairs of permanent magnets and three pairs of electrodes are installed alternately as shown in the preferred embodiment (Fig. 4), connecting the power supply system to the electrodes, the strength of the electrodes easily It can be adjusted.

By controlling the degree of acceleration of the ion by this principle, it is possible to obtain the same effect as the conventional high frequency accelerator (120).

The effects of the present invention that can be expected by the configuration and action as described above are as follows.

Plasma ion acceleration apparatus for semiconductor wafer etching process according to the present invention uses the electromagnetic force according to the simultaneous formation of the electric field and the magnetic field, the chamber 10 by using the principle that the internal charge proceeds in the vector product direction of the magnetic field and the electric field By accelerating the plasma P ions present in the wafer 1, the unnecessary high frequency accelerator 120 can be removed, thereby miniaturizing the device, thereby reducing the required cost and, of course, the wafer 1. Since the accelerating voltage is not directly transmitted to the Nth, the damage of the semiconductor device can be prevented, and the stability of the plasma P can be achieved.

Claims (4)

A chamber for plasma reaction for accommodating a wafer, a susceptor for supporting the wafer in the chamber, an electrode and a magnet disposed on an inner circumferential surface of the chamber for accelerating internal charge in a specific direction by the electromagnetic force; And a plasma ion accelerator for semiconductor wafer etching process comprising a high density plasma generator provided outside the chamber. The plasma ion acceleration apparatus of claim 1, wherein the electrode and the magnet are disposed at a predetermined position such that the crossing state of the electric field and the magnetic field always proceeds in a constant direction in the chamber in which the plasma is generated. According to claim 1 or 2, wherein the electrode and the magnet are arranged along the inner circumferential surface of the chamber in the order of N pole, + pole, S pole,-pole so that the magnetic field and the electric field cross each other, characterized in that Plasma ion accelerator for semiconductor wafer etching process. 3. The plasma ion accelerator of claim 1, wherein the magnet comprises a permanent magnet or an electromagnet. 4.