KR19990065869A - Memory Cells to Reduce Power Consumption - Google Patents

Abstract

The present invention relates to a memory cell, and more particularly, to a memory cell capable of reducing power consumption due to a bit line, the memory cell comprising: bit lines; Word lines; A latch circuit connected between the bit lines; A switch controlled by said word line and connected between said bit line and a latch circuit; Being controlled by a bit line select signal. And a blocking circuit connected between the latch circuit and the switch. By such a cell, power consumption due to unselected bit lines can be reduced.

Description

Memory cell for reducing power consumption

The present invention relates to a memory cell, and more particularly to a memory cell of the SRAM that can reduce power consumption.

1 is a circuit diagram illustrating a conventional SRAM memory cell structure including a latch circuit and a transistor for selecting a word line. In general, SRAM is determined by the address from which the bit line selection is applied from the outside. In order to prevent an increase in cell loading, a problem occurs in that power is consumed by being charged or discharged to an unselected bit line. About 40% of the current drawn in the SRAM is spent charging and discharging the bit lines.

It is therefore an object of the present invention to provide a memory cell that blocks charge and discharge for an unselected bit line.

1 is a circuit diagram showing a cell structure of a typical SRAM:

2 is a circuit diagram showing a cell structure of an SRAM according to an embodiment of the present invention:

3 shows a structure of a plurality of cell arrays:

(Configuration)

According to one aspect of the present invention, a memory cell includes: bit lines; Word lines; A latch circuit connected between the bit lines; A switch controlled by said word line and connected between said bit line and a latch circuit; Being controlled by a bit line select signal. And a blocking circuit connected between the latch circuit and the switch.

Such a circuit can prevent charging and discharging of unselected bit lines.

(Example)

Referring to the reference drawings according to a preferred embodiment of the present invention 2 and 3 as follows.

FIG. 2 is a circuit diagram showing an SRAM memory cell structure, in which transistors 1 and 2 turned on and off by a word line, transistors 4 and 5 for blocking selection of a bit line, and a latch circuit ( Include 3). The transistors 1 and 2 have gates connected to word lines and bit lines B / L, ) And the latch circuit 3. The blocking transistors 4 and 5 for preventing charging and discharging of the unselected bit lines exist between the latch circuit and the transistors 1 and 2 and are turned on and off by the column select signal col_sel.

For example, when the gates of 1 and 2 are connected to a word line of 1 and the column select signal col-sel is 0, the blocking transistors 4 and 5 are turned off. As a result, unselected bit lines (B / L, ) Is not discharged. An array of cells having the structure as described above is schematically illustrated in FIG. 3.

Referring to FIG. 3, a plurality of cells bit_cell0, bit_cell1, bit_cell2, and bit_cell3 are formed by bit lines B / L0, , B / L1, ) And word lines (W / L0, ) And the bit lines B / L0, , B / L1, ) Is selected by the multiplexers mux0, mux1: 20a, 20b. The multiplexers mux0 and mux1: 20a and 20b receive the column select signals col_sel0 and col_sel1 and receive a bit line pair B / L0, ), (B / L1, ) And a selected signal (selected_bit, selected_) indicating that a pair of bit lines are selected. )

If col_sel0 equal to 1 and col_sel1 equal to 0 are applied, B / L0, through the multiplexer mux0, 20a, is applied. Is selected. The bit lines B / L0, ) Is selected_bit, selected_ Is discharged by the bit cells 10a and 10b. On the contrary, the multiplexers mux1 and 20b, which are different from the above, respond to the col_sel1 bit line pair B / L1. Do not select The bit lines are not discharged by corresponding bit cells. Therefore, unselected bit lines are not discharged, thereby reducing power consumption.

When the memory cell of the present invention is provided, power consumption of 20% can be expected in the case of a 2x1 column multiplexer, and power consumption of 39% can be reduced in the case of a 32x1 column multiplexer.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

Therefore, the present invention can prevent the discharge to the unselected bit line to minimize the power consumption.

Claims (1)

Bit lines; Word lines; A latch circuit connected between the bit lines; A switch controlled by said word line and connected between said bit line and a latch circuit; Being controlled by a bit line select signal. And a blocking circuit connected between the latch circuit and the switch.