KR19990063001A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990063001A KR19990063001A KR1019980054456A KR19980054456A KR19990063001A KR 19990063001 A KR19990063001 A KR 19990063001A KR 1019980054456 A KR1019980054456 A KR 1019980054456A KR 19980054456 A KR19980054456 A KR 19980054456A KR 19990063001 A KR19990063001 A KR 19990063001A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
본 발명의 목적은, 층간절연막을 가지는 반도체기판상에 금속배선을 형성하는 공정에 있어서, 화학적기계적연마가 행해진 반도체기판에 잔류하는 금속이온을 확실하게 제거하는 것이다. 이를 위해, 반도체기판(1)에 대해서 화학적기계적연마를 행하며, 그 후, 화학적기계적연마에 의해 반도체기판(1)에 잔류하는 Fe이온의 제거효과를 가지는 세정액을 사용하는 것에 의해, 연마가 끝난 반도체기판(1)을 세정한다.An object of the present invention is to reliably remove metal ions remaining on a semiconductor substrate subjected to chemical mechanical polishing in a step of forming metal wiring on a semiconductor substrate having an interlayer insulating film. To this end, the semiconductor substrate 1 is subjected to chemical mechanical polishing, and thereafter, by using a cleaning liquid having a removal effect of Fe ions remaining on the semiconductor substrate 1 by chemical mechanical polishing, the polished semiconductor is used. The substrate 1 is cleaned.
Description
본 발명은, 반도체장치의 제조방법에 관한 것으로, 특히 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method.
일본특허공개 평6-196461호 공보에 개시된 종래 예의 기술에서는, 최종연마후의 실리콘웨이퍼를 NH3과 H2O2를 함유하는 수용액을 사용해서 전 단계 처리를 행한 후, 1∼10중량%의 구연산과 0.2∼2중량%의 HCl를 함유하는 수용액을 사용해서 세정을 행하였다.In the conventional example technique disclosed in Japanese Patent Application Laid-Open No. 6-196461, after the final polishing of the silicon wafer after the final polishing using an aqueous solution containing NH 3 and H 2 O 2 , 1 to 10% by weight of citric acid And an aqueous solution containing 0.2 to 2% by weight of HCl.
일본특허공개 평7-335597호 공보에 개시된 종래 예의 기술에서는 도 4에 도시하듯이, 시료대(11)상에 반도체기판(12)을 적재하고, 반도체기판(12)을 회전시키면서 브러시(13)에 의해 반도체기판(12)을 연마한 후, 연마에 의해 층간절연막을 평탄화한 반도체기판(이하 웨이퍼라 함)(12)의 표면을 불소화암모니움(14), 초산, 또는 불산 중 적어도 하나 이상의 물약을 사용해서 세정을 행하였다.In the conventional example technique disclosed in Japanese Patent Laid-Open No. 7-335597, as shown in Fig. 4, the semiconductor substrate 12 is placed on the sample stage 11, and the brush 13 is rotated while the semiconductor substrate 12 is rotated. After polishing the semiconductor substrate 12 by means of polishing, the surface of the semiconductor substrate 12 (hereinafter referred to as a wafer) 12 having the planarized interlayer insulating film by polishing is a potion of at least one of ammonium fluoride 14, acetic acid, or hydrofluoric acid. It wash | cleaned using.
따라서, 상술한 종래 예의 기술에서는, 웨이퍼의 표면에 잔존한 금속이온이 오염원이 되어서, 하지공정의 웨이퍼를 오염시켜서 반도체의 수율의 저하를 이끈다고 하는 문제가 있다.Therefore, in the technique of the conventional example described above, there is a problem that metal ions remaining on the surface of the wafer become a contamination source, contaminating the wafer in the underlying process, leading to a decrease in the yield of the semiconductor.
그 이유는, 배선형성을 위한 연마에 Fe계 산화제를 사용한 알루미나입자 슬러리를 사용하고 있고, 연마 후의 세정공정 후에 Fe이온이 웨이퍼상에 잔류하고 있으면, 반도체장치의 제조라인이 하지공정과 상지공정이 공존하는 반도체제조라인에서는, 웨이퍼 일 표면에 잔존한 금속이온이 오염원이 되어서 하지공정의 웨이퍼를 오염시켜 버리기 때문이다.The reason for this is that when a slurry of alumina particles using an Fe-based oxidant is used for polishing for forming the wiring, and Fe ions remain on the wafer after the cleaning step after polishing, the manufacturing process of the semiconductor device is based on This is because in the coexisting semiconductor manufacturing line, metal ions remaining on one surface of the wafer become a contamination source and contaminate the wafer of the ground process.
또, 하지에 대해 손상을 주는 문제가 있다.In addition, there is a problem of damage to the lower limbs.
그 이유는, 연마후의 세정액으로서 불산과 같이 산화물의 용해성이 높은 용액을 사용하면, 하지산화막을 에칭해서 웨이퍼 표면의 금속이온은 제거하게 되지만, 그 반면, 금속배선의 배리어막의 Ti막도 용해해서 에칭해 버린다. 이 때문에, 배선하지의 배리어막은 제거되어서 도통불량이 일어나며, 반도체장치의 수율 저하를 일으켜 버리기 때문이다.The reason is that when a solution having high solubility of oxides such as hydrofluoric acid is used as the cleaning solution after polishing, the underlying oxide film is etched to remove metal ions on the wafer surface, while the Ti film of the barrier film of the metal wiring is also dissolved and etched. Do it. For this reason, the barrier film under wiring is removed, resulting in poor conduction, which causes a decrease in yield of the semiconductor device.
본 발명의 목적은, 금속의 화학적기계적연마(Chemical Mechanical Polishing, 이하 CMP라 함)공정 후에 행해지는 세정공정에 있어서 웨이퍼 표면의 Fe계 금속이온의 제거효과를 가지는 세정액을 사용하는 것에 의해, 신뢰성의 향상과 수율의 향상을 달성할 수 있는 반도체장치의 제조방법을 제공하는 것이다.An object of the present invention is to provide reliability by using a cleaning liquid having a removal effect of Fe-based metal ions on the wafer surface in a cleaning step performed after a chemical mechanical polishing (CMP) process of a metal. It is to provide a method for manufacturing a semiconductor device that can achieve an improvement and an improvement in yield.
도 1은 본 발명의 실시예 1을 공정순으로 도시하는 단면도이며,1 is a cross-sectional view showing a first embodiment of the present invention in the order of process,
도 2는 본 발명의 실시예 2를 공정순으로 도시하는 단면도이며,2 is a cross-sectional view showing a second embodiment of the present invention in the order of process;
도 3은 본 발명의 실시예 3을 공정순으로 도시하는 단면도이며,3 is a cross-sectional view showing the third embodiment of the present invention in the order of process;
도 4는 종래 예를 공정순으로 도시하는 단면도이다.4 is a cross-sectional view showing a conventional example in process order.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 실리콘산화막1: semiconductor substrate 2: silicon oxide film
3 : 제 1의 금속배선 4 : 제 1의 층간절연막3: first metal wiring 4: first interlayer insulating film
5 : 비어홀 6 : 밀착층5: beer hole 6: contact layer
7 : 텅스텐막7: tungsten film
상기 목적을 달성하기 위해, 본 발명에 따른 반도체장치의 제조방법은, 층간절연막을 가지는 반도체기판상에 금속배선을 형성하는 공정을 적어도 포함하는 반도체장치의 제조방법에 있어서,In order to achieve the above object, the semiconductor device manufacturing method according to the present invention comprises at least a step of forming a metal wiring on a semiconductor substrate having an interlayer insulating film,
상기 반도체기판에 대해서 화학적기계적연마를 행하며, 그 후, 상기 화학적기계적연마에 의해 반도체기판에 잔류하는 금속이온에 대해서 킬레이트효과를 가지는 세정액을 사용하는 것에 의해, 상기 연마가 끝난 반도체기판을 세정하는 것이다.The polishing of the polished semiconductor substrate is performed by performing chemical mechanical polishing on the semiconductor substrate, and then using a cleaning liquid having a chelating effect on the metal ions remaining on the semiconductor substrate by the chemical mechanical polishing. .
또, 상기 금속이온은 Fe이온이다.In addition, the said metal ion is Fe ion.
또, 상기 금속이온에 대해서 킬레이트효과를 가지는 세정액은, 수산, 폴리아미노카르복실산, 킬레이트제 첨가의 구연산 중 적어도 하나를 함유하는 것이다.Moreover, the washing | cleaning liquid which has a chelating effect with respect to the said metal ion contains at least one of hydroxyl acid, a polyamino carboxylic acid, and the citric acid of addition of a chelating agent.
또, 상기 Fe이온 제거효과를 가지는 세정액에 포함되는, 수산, 폴리아미노카르복실산, 킬레이트제 첨가 구연산의 농도는, 1중량%∼30중량%의 범위로 설정한다.Moreover, the density | concentration of the hydroxyl, polyamino carboxylic acid, and the chelating agent addition citric acid contained in the washing | cleaning liquid which has the said Fe ion removal effect is set to the range of 1 weight%-30 weight%.
또, 상기 Fe이온을 함유하는 연마제로서, 알루미나입자에 Fe계 산화제가 함유되는 연마제를 사용한다.In addition, an abrasive containing Fe-based oxidant in alumina particles is used as the abrasive containing Fe ions.
또, 상기 Fe이온을 함유하는 연마제로서, 실리카계 입자에 Fe계 산화제가 함유되는 연마제를 사용해도 된다.Moreover, you may use the abrasive | polishing agent which contains Fe-type oxidizing agent in a silica type particle as said abrasive | polishing agent containing Fe ion.
본 발명에 의하면, 티탄의 화학적기계적연마(Chemical Mechanical Polishing, CMP)공정에서 Fe이온으로 오염된 웨이퍼의 세정공정에 있어서, Fe이온에 대해서 킬레이트효과를 가지며, 수산, 킬레이트제 첨가 구연산, 폴리아미노카르복실산 중 적어도 하나를 함유하는 세정액을 사용해서 세정을 행한다.According to the present invention, in the cleaning process of a wafer contaminated with Fe ions in the Chemical Mechanical Polishing (CMP) process of titanium, it has a chelating effect on the Fe ions, and is added with hydroxy acid, chelating agent added citric acid, polyaminocar The washing is carried out using a washing liquid containing at least one of the acids.
본 발명을 실시하는 것에 의해, 매립되는 금속배선 형성시의 CMP법에 의한 연마로 오염된 웨이퍼 표면의 금속이온을 제거하는 것이 가능하다.By carrying out the present invention, it is possible to remove metal ions on the surface of the wafer contaminated by polishing by the CMP method at the time of forming the embedded metal wiring.
이하, 본 발명의 실시형태에 관해서 도면을 참조해서 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail with reference to drawings.
(실시형태)Embodiment
도 1a∼1c는 본 발명의 일 실시형태에 따른 반도체장치의 제조방법을 공정순으로 설명하는 단면도들이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention in order of process.
상기 도들에 도시하듯이, 본 발명의 일 실시형태에 따른 반도체기판의 제조방법은, 층간절연막 형성공정과, 플러그형성공정과, 세정공정을 포함한다.As shown in the above figures, a method for manufacturing a semiconductor substrate according to one embodiment of the present invention includes an interlayer insulating film forming step, a plug forming step, and a cleaning step.
상기 층간절연막 형성공정은, 제 1의 금속배선(3)이 형성된 반도체기판(1)상에 제 1의 층간절연막(4)을 퇴적 형성하는 처리를 행하는 공정이며, 상기 플러그형성공정은, 층간절연막(4)에 비어홀(5)을 개구해서 도전막을 매립하며, Fe이온을 포함하는 알루미나입자의 연마제를 사용한 화학적기계적연마법(Chemical Mechanical Polishing, CMP)으로 플러그를 형성하는 처리를 행하는 공정이다. 또, 상기 세정공정은, Fe이온에 대해서 킬레이트효과를 가지는 세정액을 사용해서 반도체기판(1)을 세정하는 처리를 행하는 공정이다.The interlayer insulating film forming step is a step of depositing and forming a first interlayer insulating film 4 on the semiconductor substrate 1 on which the first metal wiring 3 is formed. The plug forming step is an interlayer insulating film. The via hole 5 is opened in (4), and a conductive film is embedded, and a plug forming process is performed by chemical mechanical polishing (CMP) using an abrasive of alumina particles containing Fe ions. The cleaning step is a step of cleaning the semiconductor substrate 1 by using a cleaning liquid having a chelating effect on Fe ions.
다음으로, 본 발명의 일 실시형태에 따른 반도체기판의 제조방법을 도 1a∼1c에 의해 상세히 설명한다. 우선, 도 1a에 도시하듯이, 층간절연막 형성공정에서는, 제 1의 금속배선(3)이 형성된 반도체기판(웨이퍼)(1)상에 제 1의 층간절연막(4)을 퇴적 형성하는 처리를 행한다.Next, the manufacturing method of the semiconductor substrate which concerns on one Embodiment of this invention is demonstrated in detail with reference to FIGS. 1A-1C. First, as shown in FIG. 1A, in the interlayer insulating film forming step, a process of depositing and forming a first interlayer insulating film 4 on a semiconductor substrate (wafer) 1 on which the first metal wiring 3 is formed is performed. .
다음으로, 플러그형성공정에서는, 도 1b에 도시하듯이 층간절연막(4)에 비어홀(5)을 개구해서 도전막을 매립하며, 또, 도 1c에 도시하듯이 Fe이온을 함유하는 알루미나입자의 연마제를 사용한 화학적기계적연마법(Chemical Mechanical Polishing, CMP)에 의한 연마를 행해서 플러그(5a)를 형성하는 처리를 행한다.Next, in the plug forming step, as shown in FIG. 1B, the via hole 5 is opened in the interlayer insulating film 4 to fill the conductive film. Further, as shown in FIG. 1C, an abrasive of alumina particles containing Fe ions is used. The process of forming the plug 5a is performed by grinding | polishing by the used chemical mechanical polishing (CMP).
또, 세정공정에서는, 상기 플러그형성공정을 거치고 플러그(5a)가 형성된 웨이퍼(1)를, Fe이온에 대해서 킬레이트효과를 가지는 세정액을 사용해서 세정하는 처리를 행한다.In the cleaning step, the wafer 1 on which the plug 5a is formed is subjected to the above-described plug forming step, and the wafer 1 is cleaned using a cleaning liquid having a chelating effect on Fe ions.
이상과 같이 본 발명의 실시형태에 의하면, 금속의 화학적기계적연마법으로서 Fe이온으로 오염된 웨이퍼(1)의 세정공정에 있어서, Fe이온에 대해서 킬레이트효과를 가지며, 수산, 킬레이트제 첨가 구연산, 폴리아미노카르복실산 중 적어도 하나를 함유하는 세정액을 사용해서 세정을 행하기 때문에, 매립되는 금속배선형성시에 오염된 웨이퍼(1) 표면의 금속이온을 제거할 수 있다.As described above, according to the embodiment of the present invention, in the cleaning step of the wafer 1 contaminated with Fe ions as a chemical mechanical polishing method of the metal, it has a chelate effect on the Fe ions, and adds hydroxy acid, chelating agent added citric acid, poly Since cleaning is performed using a cleaning liquid containing at least one of aminocarboxylic acids, metal ions on the surface of the contaminated wafer 1 can be removed at the time of forming the metal wiring to be embedded.
(실시예 1)(Example 1)
다음으로 본 발명의 일 실시형태의 구체 예를 실시예 1로 하여 도 1a∼1c에 기초해서 설명한다. 우선, 도 1a에 도시하듯이, 제 1의 금속배선(3)이 형성된 웨이퍼(1)상에 제 1의 층간절연막(4)을 형성하고, 층간절연막(4)을 평탄화한다. 2는 실리콘산화막이다.Next, the specific example of one Embodiment of this invention is described as Example 1 based on FIGS. 1A-1C. First, as shown in FIG. 1A, the first interlayer insulating film 4 is formed on the wafer 1 on which the first metal wiring 3 is formed, and the interlayer insulating film 4 is planarized. 2 is a silicon oxide film.
다음으로, 도 1b에 도시하듯이, 웨이퍼(1)상의 층간절연막(4)을 평탄화 한 후, 층간절연막(4)에 비어홀(5)을 개구하며, 기판 전면에, 밀착층으로서 질화티탄막(6)을 500Å성막하며, 이어서, 질화티탄막(6)상에 텅스텐막(7)을 5000Å 순차 퇴적하여 성막한다.Next, as shown in FIG. 1B, after the planarization of the interlayer insulating film 4 on the wafer 1, the via hole 5 is opened in the interlayer insulating film 4, and the titanium nitride film (adhesive layer) is formed on the entire surface of the substrate. 6) is formed into a film of 500Å, and then a tungsten film (7) is deposited on the titanium nitride film (6) in order of 5000Å.
다음으로, 알루미나입자농도 5중량%에 산화제로서 Fe2(NO3)3(초산 제 2철)을 사용한 알루미나입자 슬러리를 사용해서 CMP법으로 텅스텐막(7)과 질화티탄막(6)을 전면 연마하고, 층간절연막(4)의 비어홀(5)내에, 텅스텐막(7) 및 질화티탄막(6)으로 이루어진 플러그(5a)를 형성한다.Next, the tungsten film 7 and the titanium nitride film 6 were fronted by a CMP method using an alumina particle slurry using Fe 2 (NO 3 ) 3 (ferric acetate) as an oxidizing agent at a concentration of 5% by weight of alumina particles. The plug 5a made of the tungsten film 7 and the titanium nitride film 6 is formed in the via hole 5 of the interlayer insulating film 4.
다음으로, 텅스텐막(7) 및 질화티탄막(6)을 CMP법으로 연마해서 플러그(5a)가 형성된 웨이퍼(1)의 표면에 대해서, Fe이온 제거효과가 우수한 세정액 농도 10중량%의 수산을 사용해서 브러시에 의해 스크랩세정을 행한다.Next, the tungsten film 7 and the titanium nitride film 6 were polished by the CMP method, and 10% by weight of oxalic acid having a concentration of 10% by weight of a cleaning solution having excellent Fe ion removal effect was applied to the surface of the wafer 1 on which the plug 5a was formed. Scrap cleaning with a brush is used.
또, 도 1c에 도시하듯이, 웨이퍼(1)의 표면에 질화티탄막 500Å과 Al-Cu막 4500Å을 연속으로 스패터 해서, 제 2의 금속배선(8)을 형성한다. 제 2의 금속배선(8)은, 플러그(5a)를 매개해서 하층의 제 1의 금속배선(3)에 도통 접속된다.In addition, as shown in FIG. 1C, on the surface of the wafer 1, a titanium nitride film 500 ms and an Al-Cu film 4500 ms are successively sputtered to form a second metal wiring 8. The second metal wiring 8 is electrically connected to the first metal wiring 3 in the lower layer via the plug 5a.
또, 도 1a∼1c에 도시하는 본 발명의 실시예 1에서는, Fe이온 제거효과가 우수한 세정액으로서 농도 10중량%의 수산을 사용하지만, 그 농도는 1중량%∼30중량%의 범위이면 동일한 효과를 획득할 수 있다. 또, Fe이온을 함유하는 연마제로서, 알루미나입자에 Fe계 산화제(초산 제 2철)를 사용하지만, 실리카계 입자에 Fe이온을 함유하고 있는 연마제를 사용해도 동일한 효과를 획득할 수 있다.In Example 1 of the present invention shown in Figs. 1A to 1C, although 10% by weight of oxalic acid is used as the washing liquid having an excellent effect of removing Fe ions, the same effect as long as the concentration is in the range of 1% to 30% by weight. Can be obtained. As the abrasive containing Fe ions, the Fe-based oxidizing agent (ferric acetate) is used for the alumina particles, but the same effect can be obtained by using the abrasive containing Fe ions in the silica-based particles.
또, 도 1a∼1c에 도시하는 본 발명의 실시예 1에서는, 밀착층(6)으로서 막두께가 500Å의 질화티탄막을 사용하지만, 그 막두께는 250∼500Å의 범위이면 되며, 질화티탄막과 티탄막이 적층되어도 동일의 효과를 가질 수 있다. 또한, 기판 전면에 성막한 텅스텐막(7)의 막두께는 5000Å으로 하지만, 그 막 두께는 4000∼8000Å의 범위이면 좋다. 또, CMP법의 연마조건은, 기판을 보지하는 정반의 회전수가 10∼70rpm, 연마용 브러시를 보지하는 캐리어의 회전수가 10∼70rpm, 연마 시에 기판에 가하는 하중이 2∼8psi, 표면 하중이 0∼4psi, 슬러리(연마제)의 유량이 50∼200cc/min의 범위이면 좋다.In the first embodiment of the present invention shown in FIGS. 1A to 1C, the titanium nitride film having a film thickness of 500 kPa is used as the adhesion layer 6, but the film thickness may be in the range of 250 to 500 kPa. Even if a titanium film is laminated, it can have the same effect. In addition, although the film thickness of the tungsten film 7 formed into the whole surface of the board | substrate shall be 5000 kPa, the film thickness should just be a range of 4000-8000 kPa. The polishing conditions of the CMP method are 10 to 70 rpm for the surface plate holding the substrate, 10 to 70 rpm for the carrier holding the polishing brush, 2 to 8 psi load applied to the substrate during polishing, and a surface load. The flow rate of 0 to 4 psi and slurry (polishing agent) may be in the range of 50 to 200 cc / min.
(실시예 2)(Example 2)
다음으로 본 발명의 실시예 2를 도 2a∼2c에 기초해서 설명한다. 우선, 도 2a에 도시하듯이, 제 1의 금속배선(3)이 형성된 웨이퍼(1)상에 제 1의 층간절연막(4)을 형성하고, 층간절연막(4)을 평탄화한다.Next, Example 2 of this invention is demonstrated based on FIGS. 2A-2C. First, as shown in FIG. 2A, the first interlayer insulating film 4 is formed on the wafer 1 on which the first metal wiring 3 is formed, and the interlayer insulating film 4 is planarized.
다음으로, 도 2b에 도시하듯이, 웨이퍼(1)상의 층간절연막(4)을 평탄화한 후, 층간절연막(4)에 비어홀(5)을 개구해서, 기판 전면에, 밀착층으로서 질화티탄막(6)을 500Å 성막하고, 이어서, 질화티탄막(6)상에 텅스텐막(7)을 5000Å 순차 퇴적해서 성막한다.Next, as shown in FIG. 2B, after the planarization of the interlayer insulating film 4 on the wafer 1, the via hole 5 is opened in the interlayer insulating film 4, and the titanium nitride film (adhesive layer) is formed on the entire surface of the substrate. 6) is deposited to 500 mW, and then a tungsten film (7) is deposited on the titanium nitride film (6) in order of 5000 m to form a film.
다음으로, 알루미나입자 농도 5중량%에 산화제로서 Fe2(NO3)3(초산 제 2철)을 사용한 알루미나입자 슬러리를 사용하고 CMP법으로 텅스텐막(7)과 질화티탄막(6)을 전면 연마하고, 층간절연막(4)의 비어홀(5) 내에, 텅스텐막(7) 및 질화티탄막(6)으로 이루어진 플러그(5a)를 형성한다.Next, an alumina particle slurry using Fe 2 (NO 3 ) 3 (ferric acetate) as an oxidizing agent was used at a concentration of 5% by weight of alumina particles. The plug 5a made of the tungsten film 7 and the titanium nitride film 6 is formed in the via hole 5 of the interlayer insulating film 4.
다음으로, 텅스텐막(7) 및 질화티탄막(6)을 CMP법으로 연마해서 플러그(5a)가 형성된 웨이퍼(1)의 표면에 대해서, Fe이온 제거효과가 우수한 세정액농도 10중량%의 폴리아미노카르복실산을 사용해서 브러시에 의해 스크랩세정을 행한다.Next, the tungsten film 7 and the titanium nitride film 6 were polished by the CMP method to the surface of the wafer 1 on which the plug 5a was formed. Scrap cleaning is performed by brush using a carboxylic acid.
또, 도 2c에 도시하듯이, 웨이퍼(1)의 표면에 질화티탄막 500Å과 Al-Cu막 4500Å을 연속으로 스패터 해서, 제 2의 금속배선(8)을 형성한다. 제 2의 금속배선(8)은, 플러그(5a)를 매개해서 하층의 제 1의 금속배선(3)에 도통 접속된다.As shown in Fig. 2C, a second metal wiring 8 is formed on the surface of the wafer 1 by successively sparing a titanium nitride film 500 ms and an Al-Cu film 4500 ms. The second metal wiring 8 is electrically connected to the first metal wiring 3 in the lower layer via the plug 5a.
또, 도 2a∼2c에 도시한 본 발명에 따른 실시예 2에서는, Fe이온 제거효과가 우수한 세정액으로서 농도 10중량%의 폴리아미노카르복실산을 사용하지만, 그 농도는 1중량%∼30중량%의 범위이면 동일한 효과를 획득할 수 있다. 또, Fe이온을 함유하는 연마제로서 알루미나입자에 Fe계 산화제(초산 제 2철)를 사용하지만, 실리카계 입자에 Fe이온을 함유하고 있는 연마제를 사용해도 동일의 효과를 획득 할 수 있다.In addition, in Example 2 according to the present invention shown in Figs. 2A to 2C, a polyamino carboxylic acid having a concentration of 10% by weight is used as a washing liquid having an excellent effect of removing Fe ions, but the concentration is 1% by weight to 30% by weight. The same effect can be obtained if it is in the range of. In addition, although Fe-type oxidizing agent (ferric acetate) is used for an alumina particle as an abrasive containing Fe ion, the same effect can be acquired even if it uses the abrasive containing Fe ion in a silica type particle.
또, 밀착층(6)으로서 막두께가 500Å인 질화티탄막을 사용하지만, 그 막두께는 250∼500Å의 범위이면 좋고, 질화티탄막과 티탄막을 적층해도 동일한 효과를 획득할 수 있다. 또, 기판 전면에 성막한 텅스텐막(7)의 막두께는 5000Å으로 하지만, 그 막두께는 4000∼8000Å의 범위이면 좋다. 또, CMP법의 연마조건은, 기판을 보지하는 정반의 회전수가 10∼70rpm, 연마용 브러시를 보지하는 캐리어의 회전수가 10∼70rpm, 연마 시에 기판에 가해지는 하중이 2∼8psi, 표면하중이 0∼4psi, 슬러리(연마제)의 유량이 50∼200cc/min의 범위이면 좋다.As the adhesion layer 6, a titanium nitride film having a film thickness of 500 kPa is used, but the film thickness may be in the range of 250 to 500 kPa, and the same effect can be obtained by laminating a titanium nitride film and a titanium film. The film thickness of the tungsten film 7 formed on the entire surface of the substrate is 5000 kPa, but the film thickness may be in the range of 4000 to 8000 kPa. The polishing conditions of the CMP method are 10 to 70 rpm for the surface plate holding the substrate, 10 to 70 rpm for the carrier holding the polishing brush, 2 to 8 psi load applied to the substrate during polishing, and a surface load. The flow rate of the 0 to 4 psi and the slurry (polishing agent) may be in the range of 50 to 200 cc / min.
(실시예 3)(Example 3)
다음으로 본 발명의 실시예 3을 도 3a∼3c에 기초해서 설명한다. 우선, 도 3a에 도시하듯이, 제 1의 금속배선(3)이 형성된 웨이퍼(1)상에 제 1의 층간절연막(4)을 형성하고, 층간절연막(4)을 평탄화한다.Next, Example 3 of this invention is demonstrated based on FIGS. 3A-3C. First, as shown in FIG. 3A, the first interlayer insulating film 4 is formed on the wafer 1 on which the first metal wiring 3 is formed, and the interlayer insulating film 4 is planarized.
다음으로, 도 3b에 도시하듯이, 웨이퍼(1)상의 층간절연막(4)을 평탄화 한 후, 층간절연막(4)에 비어홀(5)을 개구하고, 기판 전면에, 밀착층으로서 질화티탄막(6)을 500Å성막하고, 이어서 질화티탄막(6)상에 텅스텐막(7)을 5000Å 순차 퇴적해서 성막한다.Next, as shown in FIG. 3B, after the planarization of the interlayer insulating film 4 on the wafer 1, the via hole 5 is opened in the interlayer insulating film 4, and the titanium nitride film (adhesive layer) is formed on the entire surface of the substrate. 6) is formed into a film of 500 t. Then, a tungsten film (7) is deposited on the titanium nitride film (6) in order of 5000 m to form a film.
다음으로, 알루미나입자 농도 5중량%에 산화제로서 Fe2(NO3)3(초산 제 2철)을 사용한 알루미나입자 슬러리를 사용해서 CMP법으로 텅스텐막(7)과 질화티탄막(6)을 전면 연마하고, 층간절연막(4)의 비어홀(5) 내에, 텅스텐막(7) 및 질화티탄막(6)으로 이루어진 플러그(5a)를 형성한다.Next, the tungsten film 7 and the titanium nitride film 6 were fronted by a CMP method using an alumina particle slurry using Fe 2 (NO 3 ) 3 (ferric acetate) as an oxidizing agent at a concentration of 5% by weight of alumina particles. The plug 5a made of the tungsten film 7 and the titanium nitride film 6 is formed in the via hole 5 of the interlayer insulating film 4.
다음으로, 텅스텐막(7) 및 질화티탄막(6)을 CMP법으로 연마하고 플러그(5a)가 형성된 웨이퍼(1)의 표면에 대해서, Fe이온 제거효과가 우수한 세정액 농도 10중량%의 킬레이트제 함유의 구연산을 사용해서 브러시에 의한 스크랩세정을 행한다.Next, a chelating agent having a concentration of 10% by weight of a cleaning liquid having excellent Fe ion removal effect on the surface of the wafer 1 on which the tungsten film 7 and the titanium nitride film 6 were polished by the CMP method and the plug 5a was formed. Scrap cleaning with a brush is performed using citric acid.
또, 도 3c에 도시하듯이, 웨이퍼(1)의 표면에 질화티탄막 500Å과 Al-Cu막 4500Å을 연속으로 스패터 하고, 제 2의 금속배선(8)을 형성한다. 제 2의 금속배선(8)은, 플러그(5a)를 매개해서 하층의 제 1의 금속배선(3)에 도통 접속된다.As shown in Fig. 3C, on the surface of the wafer 1, 500 ns of titanium nitride films and 4500 ns of Al-Cu films are successively sputtered to form a second metal wiring 8. The second metal wiring 8 is electrically connected to the first metal wiring 3 in the lower layer via the plug 5a.
또, 도 3a∼3c에 도시한 본 발명에 따른 실시예 3에서는, Fe이온 제거효과가 우수한 세정액으로서 농도 10중량%의 킬레이트제 함유의 구연산을 사용하지만, 그 농도는 1중량%∼30중량%의 범위이면 동일한 효과를 획득할 수 있다. 또, Fe이온을 함유하는 연마제로서 알루미나입자에 Fe계 산화제(초산 제 2철)를 사용하지만, 실리카계 입자에 Fe이온을 함유하고 있는 연마제를 사용해도 동일한 효과를 획득할 수 있다.In addition, in Example 3 according to the present invention shown in Figs. 3A to 3C, citric acid containing a chelating agent having a concentration of 10% by weight is used as a washing liquid having excellent Fe ion removal effect, but the concentration is 1% by weight to 30% by weight. The same effect can be obtained if it is in the range of. In addition, although Fe-type oxidizing agent (ferric acetate) is used for alumina particles as an abrasive containing Fe ion, the same effect can be acquired also if it uses the abrasive containing Fe ion in silica type particle | grains.
또, 밀착층(6)으로서 막두께가 500Å인 질화티탄막을 사용하지만, 그 막 두께는 250∼500Å의 범위이면 좋고, 질화티탄막과 티탄막의 적층으로도 동일한 효과를 획득할 수 있다. 또, 기판 전면에 성막한 텅스텐막(7)의 막두께는 5000Å으로 하지만, 그 막두께는 4000∼8000Å의 범위이면 좋다. 또, CMP법의 연마조건은, 기판을 보지하는 정반의 회전수가 10∼70rpm 연마용 브러시를 보지하는 캐리어의 회전수가 10∼70rpm, 연마 시에 기판에 가하는 하중이 2∼8psi, 표면하중이 0∼4psi, 슬러리(연마제)의 유량이 50∼200cc/min의 범위이면 좋다.As the adhesion layer 6, a titanium nitride film having a film thickness of 500 kPa is used, but the film thickness should be in the range of 250 to 500 kPa, and the same effect can be obtained by laminating a titanium nitride film and a titanium film. The film thickness of the tungsten film 7 formed on the entire surface of the substrate is 5000 kPa, but the film thickness may be in the range of 4000 to 8000 kPa. The polishing conditions of the CMP method are 10 to 70 rpm for the platen holding the substrate, 10 to 70 rpm for the carrier holding the polishing brush, 2 to 8 psi load applied to the substrate during polishing, and zero surface load. The flow rate of -4 psi and the slurry (polishing agent) may be in the range of 50 to 200 cc / min.
이상 설명하듯이, 본 발명에 의하면, CMP법에 의해 금속이온, 특히, Fe이온으로 오염된 반도체기판을, 수산, 킬레이트제 첨가 구연산, 폴리아미노카르복실산 중 적어도 하나를 함유하는 세정액을 사용해서 세정하기 때문에, 연마 후의 반도체기판으로부터 Fe이온을 제거할 수 있다. 게다가, 반도체기판으로부터 Fe이온을 제거하는 때에 반도체기판에 손상을 주지 않는다.As described above, according to the present invention, a semiconductor substrate contaminated with metal ions, in particular Fe ions, by a CMP method is used by using a cleaning solution containing at least one of hydroxyl, chelating agent-added citric acid, and polyaminocarboxylic acid. In order to clean, Fe ions can be removed from the polished semiconductor substrate. In addition, the removal of Fe ions from the semiconductor substrate does not damage the semiconductor substrate.
그 이유는, 금속이온에 대해서 킬레이트효과를 가지며, 수산, 킬레이트제 첨가 구연산, 폴리아미노카르복실산을 세정액으로서 사용하는 것에 의해, 하지에 손상을 주지 않으면서 Fe이온만을 제거할 수 있기 때문이다.The reason for this is that it has a chelate effect on metal ions, and only Fe ions can be removed without damaging the base by using hydroxyl, chelating agent-added citric acid and polyaminocarboxylic acid as the cleaning liquid.
또, Fe이온의 제거에 의해 반도체제조라인 내의 오염을 방지할 수 있으며, 디바이스특성의 향상과 수율의 향상을 도모할 수 있다.In addition, by removing Fe ions, contamination in the semiconductor manufacturing line can be prevented, and device characteristics and yield can be improved.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9-341314 | 1997-12-11 | ||
| JP9341314A JPH11176777A (en) | 1997-12-11 | 1997-12-11 | Manufacture of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19990063001A true KR19990063001A (en) | 1999-07-26 |
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|---|---|---|---|
| KR1019980054456A KR19990063001A (en) | 1997-12-11 | 1998-12-11 | Manufacturing Method of Semiconductor Device |
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| JP (1) | JPH11176777A (en) |
| KR (1) | KR19990063001A (en) |
| CN (1) | CN1227403A (en) |
| TW (1) | TW396439B (en) |
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| JP3917593B2 (en) | 2004-02-05 | 2007-05-23 | 株式会社東芝 | Manufacturing method of semiconductor device |
| JP5767898B2 (en) * | 2011-08-12 | 2015-08-26 | 株式会社東芝 | Manufacturing method of semiconductor device |
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1997
- 1997-12-11 JP JP9341314A patent/JPH11176777A/en active Pending
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1998
- 1998-12-10 TW TW087120558A patent/TW396439B/en active
- 1998-12-11 KR KR1019980054456A patent/KR19990063001A/en not_active Application Discontinuation
- 1998-12-11 CN CN98125269A patent/CN1227403A/en active Pending
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| CN1227403A (en) | 1999-09-01 |
| TW396439B (en) | 2000-07-01 |
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